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1//==- RISCVSchedSiFiveP800.td - SiFiveP800 Scheduling Defs ---*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10 11/// c is true if mx has the worst case behavior compared to LMULs in MxList.12/// On the SiFiveP800, the worst case LMUL is the Largest LMUL13/// and the worst case sew is the smallest SEW for that LMUL.14class SiFiveP800IsWorstCaseMX<string mx, list<string> MxList> {15 string LLMUL = LargestLMUL<MxList>.r;16 bit c = !eq(mx, LLMUL);17}18 19class SiFiveP800IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {20 string LLMUL = LargestLMUL<MxList>.r;21 int SSEW = SmallestSEW<mx, isF>.r;22 bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));23}24 25// 1 Micro-Op per cycle.26class SiFiveP800GetLMulCycles<string mx> {27 int c = !cond(28 !eq(mx, "M1") : 1,29 !eq(mx, "M2") : 2,30 !eq(mx, "M4") : 4,31 !eq(mx, "M8") : 8,32 !eq(mx, "MF2") : 1,33 !eq(mx, "MF4") : 1,34 !eq(mx, "MF8") : 135 );36}37 38// Latency for segmented loads and stores are calculated as vl.39class SiFiveP800GetCyclesSegmented<string mx, int sew> {40 defvar VLEN = 128;41 int c = !cond(42 !eq(mx, "M1") : !div(VLEN, sew),43 !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),44 !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),45 !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),46 !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),47 !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),48 !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),49 );50}51 52class SiFiveP800VSM3CCycles<string mx> {53 // c = ceil(LMUL / 2)54 int c = !cond(!eq(mx, "M2") : 1,55 !eq(mx, "M4") : 2,56 !eq(mx, "M8") : 4,57 true : 1);58}59 60// SiFiveP800 machine model for scheduling and other instruction cost heuristics.61def SiFiveP800Model : SchedMachineModel {62 let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.63 let MicroOpBufferSize = 288; // Max micro-ops that can be buffered.64 let LoadLatency = 4; // Cycles for loads to access the cache.65 let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.66 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,67 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,68 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,69 HasVendorXSfvqmaccqoq, HasVendorXSfvqmaccdod];70 let CompleteModel = false;71}72 73let SchedModel = SiFiveP800Model in {74 75def SiFiveP800IEXQ0 : ProcResource<1>;76def SiFiveP800IEXQ1 : ProcResource<1>;77def SiFiveP800IEXQ2 : ProcResource<1>;78def SiFiveP800IEXQ3 : ProcResource<1>;79def SiFiveP800IEXQ4 : ProcResource<1>;80def SiFiveP800IEXQ5 : ProcResource<1>;81def SiFiveP800FEXQ0 : ProcResource<1>;82def SiFiveP800FEXQ1 : ProcResource<1>;83 84// Two Load/Store ports that can issue either two loads, two stores, or one load85// and one store.86def SiFiveP800LDST : ProcResource<2>;87// One additional port that can only handle loads.88def SiFiveP800LD : ProcResource<1>;89def SiFiveP800Load : ProcResGroup<[SiFiveP800LDST, SiFiveP800LD]>;90 91// 6-wide pipeline with 6 ALU pipes.92def SiFiveP800IntArith : ProcResGroup<[SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3]>;93defvar SiFiveP800SYS = SiFiveP800IEXQ1;94defvar SiFiveP800CMOV = SiFiveP800IEXQ3;95defvar SiFiveP800I2F = SiFiveP800IEXQ3;96def SiFiveP800Mul : ProcResGroup<[SiFiveP800IEXQ1, SiFiveP800IEXQ3]>;97def SiFiveP800Branch : ProcResGroup<[SiFiveP800IEXQ4, SiFiveP800IEXQ5]>;98def SiFiveP800Div : ProcResource<1>;99 100def SiFiveP800FloatArith : ProcResGroup<[SiFiveP800FEXQ0, SiFiveP800FEXQ1]>;101defvar SiFiveP800F2I = SiFiveP800FEXQ0;102def SiFiveP800FloatDiv : ProcResource<1>;103 104// Vector pipeline105// VEXQ0 handle Mask, Simple Slide instructions,106// VEXQ1 handle Complex Slide, Permutation, Reductions, Divide instructions.107// Other vector instructions can be done in VEXQ0 and VEXQ1.108def SiFiveP800VEXQ0 : ProcResource<1>;109def SiFiveP800VEXQ1 : ProcResource<1>;110def SiFiveP800VectorArith : ProcResGroup<[SiFiveP800VEXQ0, SiFiveP800VEXQ1]>;111 112def SiFiveP800VLD : ProcResource<1>;113def SiFiveP800VST : ProcResource<1>;114def SiFiveP800VDiv : ProcResource<1>;115def SiFiveP800VFloatDiv : ProcResource<1>;116 117// Integer arithmetic and logic118def : WriteRes<WriteIALU, [SiFiveP800IntArith]>;119def : WriteRes<WriteIALU32, [SiFiveP800IntArith]>;120def : WriteRes<WriteShiftImm, [SiFiveP800IntArith]>;121def : WriteRes<WriteShiftImm32, [SiFiveP800IntArith]>;122def : WriteRes<WriteShiftReg, [SiFiveP800IntArith]>;123def : WriteRes<WriteShiftReg32, [SiFiveP800IntArith]>;124// Branching125def : WriteRes<WriteJmp, [SiFiveP800Branch]>;126def : WriteRes<WriteJal, [SiFiveP800Branch]>;127def : WriteRes<WriteJalr, [SiFiveP800Branch]>;128 129// CMOV130def P800WriteCMOV : SchedWriteRes<[SiFiveP800Branch, SiFiveP800CMOV]> {131 let Latency = 2;132 let NumMicroOps = 2;133}134def : InstRW<[P800WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;135 136let Latency = 2 in {137// Integer multiplication138def : WriteRes<WriteIMul, [SiFiveP800Mul]>;139def : WriteRes<WriteIMul32, [SiFiveP800Mul]>;140// cpop[w] look exactly like multiply.141def : WriteRes<WriteCPOP, [SiFiveP800Mul]>;142def : WriteRes<WriteCPOP32, [SiFiveP800Mul]>;143}144 145// Integer division146def : WriteRes<WriteIDiv, [SiFiveP800IEXQ2, SiFiveP800Div]> {147 let Latency = 35;148 let ReleaseAtCycles = [1, 34];149}150def : WriteRes<WriteIDiv32, [SiFiveP800IEXQ2, SiFiveP800Div]> {151 let Latency = 20;152 let ReleaseAtCycles = [1, 19];153}154 155// Integer remainder156def : WriteRes<WriteIRem, [SiFiveP800IEXQ2, SiFiveP800Div]> {157 let Latency = 35;158 let ReleaseAtCycles = [1, 34];159}160def : WriteRes<WriteIRem32, [SiFiveP800IEXQ2, SiFiveP800Div]> {161 let Latency = 20;162 let ReleaseAtCycles = [1, 19];163}164 165// Bitmanip166def : WriteRes<WriteRotateImm, [SiFiveP800IntArith]>;167def : WriteRes<WriteRotateImm32, [SiFiveP800IntArith]>;168def : WriteRes<WriteRotateReg, [SiFiveP800IntArith]>;169def : WriteRes<WriteRotateReg32, [SiFiveP800IntArith]>;170 171def : WriteRes<WriteCLZ, [SiFiveP800IntArith]>;172def : WriteRes<WriteCLZ32, [SiFiveP800IntArith]>;173def : WriteRes<WriteCTZ, [SiFiveP800IntArith]>;174def : WriteRes<WriteCTZ32, [SiFiveP800IntArith]>;175 176def : WriteRes<WriteORCB, [SiFiveP800IntArith]>;177def : WriteRes<WriteIMinMax, [SiFiveP800IntArith]>;178 179def : WriteRes<WriteREV8, [SiFiveP800IntArith]>;180 181def : WriteRes<WriteSHXADD, [SiFiveP800IntArith]>;182def : WriteRes<WriteSHXADD32, [SiFiveP800IntArith]>;183 184def : WriteRes<WriteSingleBit, [SiFiveP800IntArith]>;185def : WriteRes<WriteSingleBitImm, [SiFiveP800IntArith]>;186def : WriteRes<WriteBEXT, [SiFiveP800IntArith]>;187def : WriteRes<WriteBEXTI, [SiFiveP800IntArith]>;188 189// Memory190def : WriteRes<WriteSTB, [SiFiveP800LDST]>;191def : WriteRes<WriteSTH, [SiFiveP800LDST]>;192def : WriteRes<WriteSTW, [SiFiveP800LDST]>;193def : WriteRes<WriteSTD, [SiFiveP800LDST]>;194def : WriteRes<WriteFST16, [SiFiveP800LDST]>;195def : WriteRes<WriteFST32, [SiFiveP800LDST]>;196def : WriteRes<WriteFST64, [SiFiveP800LDST]>;197 198let Latency = 4 in {199def : WriteRes<WriteLDB, [SiFiveP800Load]>;200def : WriteRes<WriteLDH, [SiFiveP800Load]>;201def : WriteRes<WriteLDW, [SiFiveP800Load]>;202def : WriteRes<WriteLDD, [SiFiveP800Load]>;203}204 205let Latency = 5 in {206def : WriteRes<WriteFLD16, [SiFiveP800Load]>;207def : WriteRes<WriteFLD32, [SiFiveP800Load]>;208def : WriteRes<WriteFLD64, [SiFiveP800Load]>;209}210 211// Atomic memory212def : WriteRes<WriteAtomicSTW, [SiFiveP800LDST]>;213def : WriteRes<WriteAtomicSTD, [SiFiveP800LDST]>;214 215let Latency = 7 in {216def : WriteRes<WriteAtomicW, [SiFiveP800LDST]>;217def : WriteRes<WriteAtomicD, [SiFiveP800LDST]>;218}219 220let Latency = 10 in {221def : WriteRes<WriteAtomicLDW, [SiFiveP800Load]>;222def : WriteRes<WriteAtomicLDD, [SiFiveP800Load]>;223}224 225// Floating point226let Latency = 2 in {227def : WriteRes<WriteFAdd16, [SiFiveP800FloatArith]>;228def : WriteRes<WriteFAdd32, [SiFiveP800FloatArith]>;229def : WriteRes<WriteFAdd64, [SiFiveP800FloatArith]>;230}231let Latency = 3 in {232def : WriteRes<WriteFMul16, [SiFiveP800FloatArith]>;233def : WriteRes<WriteFMul32, [SiFiveP800FloatArith]>;234def : WriteRes<WriteFMul64, [SiFiveP800FloatArith]>;235}236let Latency = 4 in {237def : WriteRes<WriteFMA16, [SiFiveP800FloatArith]>;238def : WriteRes<WriteFMA32, [SiFiveP800FloatArith]>;239def : WriteRes<WriteFMA64, [SiFiveP800FloatArith]>;240}241 242let Latency = 2 in {243def : WriteRes<WriteFSGNJ16, [SiFiveP800FloatArith]>;244def : WriteRes<WriteFSGNJ32, [SiFiveP800FloatArith]>;245def : WriteRes<WriteFSGNJ64, [SiFiveP800FloatArith]>;246 247def : WriteRes<WriteFMinMax16, [SiFiveP800FloatArith]>;248def : WriteRes<WriteFMinMax32, [SiFiveP800FloatArith]>;249def : WriteRes<WriteFMinMax64, [SiFiveP800FloatArith]>;250}251 252// Half precision.253def : WriteRes<WriteFDiv16, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {254 let Latency = 4;255 let ReleaseAtCycles = [1, 4];256}257def : WriteRes<WriteFSqrt16, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {258 let Latency = 8;259 let ReleaseAtCycles = [1, 7];260}261 262// Single precision.263def : WriteRes<WriteFDiv32, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {264 let Latency = 6;265 let ReleaseAtCycles = [1, 6];266}267def : WriteRes<WriteFSqrt32, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {268 let Latency = 14;269 let ReleaseAtCycles = [1, 13];270}271 272// Double precision273def : WriteRes<WriteFDiv64, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {274 let Latency = 11;275 let ReleaseAtCycles = [1, 11];276}277def : WriteRes<WriteFSqrt64, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {278 let Latency = 29;279 let ReleaseAtCycles = [1, 28];280}281 282// Conversions283let Latency = 2 in {284def : WriteRes<WriteFCvtI32ToF16, [SiFiveP800I2F]>;285def : WriteRes<WriteFCvtI32ToF32, [SiFiveP800I2F]>;286def : WriteRes<WriteFCvtI32ToF64, [SiFiveP800I2F]>;287def : WriteRes<WriteFCvtI64ToF16, [SiFiveP800I2F]>;288def : WriteRes<WriteFCvtI64ToF32, [SiFiveP800I2F]>;289def : WriteRes<WriteFCvtI64ToF64, [SiFiveP800I2F]>;290def : WriteRes<WriteFCvtF16ToI32, [SiFiveP800F2I]>;291def : WriteRes<WriteFCvtF16ToI64, [SiFiveP800F2I]>;292def : WriteRes<WriteFCvtF16ToF32, [SiFiveP800FloatArith]>;293def : WriteRes<WriteFCvtF16ToF64, [SiFiveP800FloatArith]>;294def : WriteRes<WriteFCvtF32ToI32, [SiFiveP800F2I]>;295def : WriteRes<WriteFCvtF32ToI64, [SiFiveP800F2I]>;296def : WriteRes<WriteFCvtF32ToF16, [SiFiveP800FloatArith]>;297def : WriteRes<WriteFCvtF32ToF64, [SiFiveP800FloatArith]>;298def : WriteRes<WriteFCvtF64ToI32, [SiFiveP800F2I]>;299def : WriteRes<WriteFCvtF64ToI64, [SiFiveP800F2I]>;300def : WriteRes<WriteFCvtF64ToF16, [SiFiveP800FloatArith]>;301def : WriteRes<WriteFCvtF64ToF32, [SiFiveP800FloatArith]>;302def : WriteRes<WriteFRoundF16, [SiFiveP800FloatArith]>;303def : WriteRes<WriteFRoundF32, [SiFiveP800FloatArith]>;304def : WriteRes<WriteFRoundF64, [SiFiveP800FloatArith]>;305 306def : WriteRes<WriteFClass16, [SiFiveP800F2I]>;307def : WriteRes<WriteFClass32, [SiFiveP800F2I]>;308def : WriteRes<WriteFClass64, [SiFiveP800F2I]>;309def : WriteRes<WriteFCmp16, [SiFiveP800F2I]>;310def : WriteRes<WriteFCmp32, [SiFiveP800F2I]>;311def : WriteRes<WriteFCmp64, [SiFiveP800F2I]>;312def : WriteRes<WriteFMovI16ToF16, [SiFiveP800I2F]>;313def : WriteRes<WriteFMovF16ToI16, [SiFiveP800F2I]>;314def : WriteRes<WriteFMovI32ToF32, [SiFiveP800I2F]>;315def : WriteRes<WriteFMovF32ToI32, [SiFiveP800F2I]>;316def : WriteRes<WriteFMovI64ToF64, [SiFiveP800I2F]>;317def : WriteRes<WriteFMovF64ToI64, [SiFiveP800F2I]>;318def : WriteRes<WriteFLI16, [SiFiveP800I2F]>;319def : WriteRes<WriteFLI32, [SiFiveP800I2F]>;320def : WriteRes<WriteFLI64, [SiFiveP800I2F]>;321}322 323// 6. Configuration-Setting Instructions324def : WriteRes<WriteVSETVLI, [SiFiveP800SYS]>;325def : WriteRes<WriteVSETIVLI, [SiFiveP800SYS]>;326def : WriteRes<WriteVSETVL, [SiFiveP800SYS]>;327 328// 7. Vector Loads and Stores329// FIXME: This unit is still being improved, currently330// it is based on stage numbers. Estimates are optimistic,331// latency may be longer.332foreach mx = SchedMxList in {333 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;334 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;335 let Latency = 8, ReleaseAtCycles = [LMulLat] in {336 defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP800VLD], mx, IsWorstCase>;337 defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP800VLD], mx, IsWorstCase>;338 defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP800VLD], mx, IsWorstCase>;339 }340 let Latency = 12, ReleaseAtCycles = [LMulLat] in {341 defm "" : LMULWriteResMX<"WriteVLDS8", [SiFiveP800VLD], mx, IsWorstCase>;342 defm "" : LMULWriteResMX<"WriteVLDS16", [SiFiveP800VLD], mx, IsWorstCase>;343 defm "" : LMULWriteResMX<"WriteVLDS32", [SiFiveP800VLD], mx, IsWorstCase>;344 defm "" : LMULWriteResMX<"WriteVLDS64", [SiFiveP800VLD], mx, IsWorstCase>;345 }346 let Latency = 12, ReleaseAtCycles = [LMulLat] in {347 defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFiveP800VLD], mx, IsWorstCase>;348 defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP800VLD], mx, IsWorstCase>;349 defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP800VLD], mx, IsWorstCase>;350 defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP800VLD], mx, IsWorstCase>;351 defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFiveP800VLD], mx, IsWorstCase>;352 defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP800VLD], mx, IsWorstCase>;353 defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP800VLD], mx, IsWorstCase>;354 defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP800VLD], mx, IsWorstCase>;355 }356}357 358foreach mx = SchedMxList in {359 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;360 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;361 let Latency = 8, ReleaseAtCycles = [LMulLat] in {362 defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP800VST], mx, IsWorstCase>;363 defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP800VST], mx, IsWorstCase>;364 }365 let Latency = 12, ReleaseAtCycles = [LMulLat] in {366 defm "" : LMULWriteResMX<"WriteVSTS8", [SiFiveP800VST], mx, IsWorstCase>;367 defm "" : LMULWriteResMX<"WriteVSTS16", [SiFiveP800VST], mx, IsWorstCase>;368 defm "" : LMULWriteResMX<"WriteVSTS32", [SiFiveP800VST], mx, IsWorstCase>;369 defm "" : LMULWriteResMX<"WriteVSTS64", [SiFiveP800VST], mx, IsWorstCase>;370 }371 let Latency = 12, ReleaseAtCycles = [LMulLat] in {372 defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFiveP800VST], mx, IsWorstCase>;373 defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP800VST], mx, IsWorstCase>;374 defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP800VST], mx, IsWorstCase>;375 defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP800VST], mx, IsWorstCase>;376 defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFiveP800VST], mx, IsWorstCase>;377 defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP800VST], mx, IsWorstCase>;378 defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP800VST], mx, IsWorstCase>;379 defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP800VST], mx, IsWorstCase>;380 }381}382 383foreach mx = SchedMxList in {384 foreach nf=2-8 in {385 foreach eew = [8, 16, 32, 64] in {386 defvar LMulLat = SiFiveP800GetCyclesSegmented<mx, eew>.c;387 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;388 let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {389 defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;390 defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;391 defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;392 defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;393 defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;394 }395 let Latency = !add(1, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {396 defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;397 defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;398 defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;399 defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;400 }401 }402 }403}404 405// Whole register move/load/store406foreach LMul = [1, 2, 4, 8] in {407 let Latency = 8, ReleaseAtCycles = [LMul] in {408 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP800VLD]>;409 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP800VST]>;410 }411 let Latency = 2, ReleaseAtCycles = [LMul] in {412 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP800VectorArith]>;413 }414}415 416// 11. Vector Integer Arithmetic Instructions417foreach mx = SchedMxList in {418 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;419 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;420 let Latency = 2, ReleaseAtCycles = [LMulLat] in {421 defm "" : LMULWriteResMX<"WriteVIALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;422 defm "" : LMULWriteResMX<"WriteVIALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;423 defm "" : LMULWriteResMX<"WriteVIALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;424 defm "" : LMULWriteResMX<"WriteVExtV", [SiFiveP800VectorArith], mx, IsWorstCase>;425 defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;426 defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;427 defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;428 defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP800VectorArith], mx, IsWorstCase>;429 defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP800VectorArith], mx, IsWorstCase>;430 defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP800VectorArith], mx, IsWorstCase>;431 defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP800VectorArith], mx, IsWorstCase>;432 defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP800VectorArith], mx, IsWorstCase>;433 defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP800VectorArith], mx, IsWorstCase>;434 defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFiveP800VectorArith], mx, IsWorstCase>;435 defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFiveP800VectorArith], mx, IsWorstCase>;436 defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFiveP800VectorArith], mx, IsWorstCase>;437 defm "" : LMULWriteResMX<"WriteVIMovV", [SiFiveP800VectorArith], mx, IsWorstCase>;438 defm "" : LMULWriteResMX<"WriteVIMovX", [SiFiveP800VectorArith], mx, IsWorstCase>;439 defm "" : LMULWriteResMX<"WriteVIMovI", [SiFiveP800VectorArith], mx, IsWorstCase>;440 }441 let Latency = 6, ReleaseAtCycles = [LMulLat] in {442 defm "" : LMULWriteResMX<"WriteVShiftV", [SiFiveP800VectorArith], mx, IsWorstCase>;443 defm "" : LMULWriteResMX<"WriteVShiftX", [SiFiveP800VectorArith], mx, IsWorstCase>;444 defm "" : LMULWriteResMX<"WriteVShiftI", [SiFiveP800VectorArith], mx, IsWorstCase>;445 defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFiveP800VectorArith], mx, IsWorstCase>;446 defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFiveP800VectorArith], mx, IsWorstCase>;447 defm "" : LMULWriteResMX<"WriteVIMulV", [SiFiveP800VectorArith], mx, IsWorstCase>;448 defm "" : LMULWriteResMX<"WriteVIMulX", [SiFiveP800VectorArith], mx, IsWorstCase>;449 defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFiveP800VectorArith], mx, IsWorstCase>;450 defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFiveP800VectorArith], mx, IsWorstCase>;451 }452}453// Widening454foreach mx = SchedMxListW in {455 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;456 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListW>.c;457 let Latency = 6, ReleaseAtCycles = [LMulLat] in {458 defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;459 defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;460 defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;461 defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFiveP800VectorArith], mx, IsWorstCase>;462 defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFiveP800VectorArith], mx, IsWorstCase>;463 defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFiveP800VectorArith], mx, IsWorstCase>;464 defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFiveP800VectorArith], mx, IsWorstCase>;465 }466}467 468// Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.469foreach mx = SchedMxList in {470 foreach sew = SchedSEWSet<mx>.val in {471 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;472 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;473 defvar DivMicroOpLat =474 !cond(!eq(sew, 8): 51, !eq(sew, 16): 45, !eq(sew, 32): 42,475 /* SEW=64 */ true: 72);476 defvar DivLatency = !mul(DivMicroOpLat, LMulLat);477 let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {478 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFiveP800VEXQ1, SiFiveP800VDiv], mx, sew, IsWorstCase>;479 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFiveP800VEXQ1, SiFiveP800VDiv], mx, sew, IsWorstCase>;480 }481 }482}483 484// Narrowing Shift and Clips485foreach mx = SchedMxListW in {486 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;487 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListW>.c;488 let Latency = 2, ReleaseAtCycles = [LMulLat] in {489 defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFiveP800VectorArith], mx, IsWorstCase>;490 defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFiveP800VectorArith], mx, IsWorstCase>;491 defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFiveP800VectorArith], mx, IsWorstCase>;492 defm "" : LMULWriteResMX<"WriteVNClipV", [SiFiveP800VectorArith], mx, IsWorstCase>;493 defm "" : LMULWriteResMX<"WriteVNClipX", [SiFiveP800VectorArith], mx, IsWorstCase>;494 defm "" : LMULWriteResMX<"WriteVNClipI", [SiFiveP800VectorArith], mx, IsWorstCase>;495 }496}497 498// 12. Vector Fixed-Point Arithmetic Instructions499foreach mx = SchedMxList in {500 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;501 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;502 let Latency = 6, ReleaseAtCycles = [LMulLat] in {503 defm "" : LMULWriteResMX<"WriteVSALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;504 defm "" : LMULWriteResMX<"WriteVSALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;505 defm "" : LMULWriteResMX<"WriteVSALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;506 defm "" : LMULWriteResMX<"WriteVAALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;507 defm "" : LMULWriteResMX<"WriteVAALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;508 defm "" : LMULWriteResMX<"WriteVSMulV", [SiFiveP800VectorArith], mx, IsWorstCase>;509 defm "" : LMULWriteResMX<"WriteVSMulX", [SiFiveP800VectorArith], mx, IsWorstCase>;510 defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFiveP800VectorArith], mx, IsWorstCase>;511 defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFiveP800VectorArith], mx, IsWorstCase>;512 defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFiveP800VectorArith], mx, IsWorstCase>;513 }514}515 516// 13. Vector Floating-Point Instructions517foreach mx = SchedMxListF in {518 foreach sew = SchedSEWSet<mx, isF=1>.val in {519 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;520 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;521 let Latency = 6, ReleaseAtCycles = [LMulLat] in {522 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;523 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;524 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;525 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;526 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;527 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;528 }529 }530}531foreach mx = SchedMxListF in {532 foreach sew = SchedSEWSet<mx, isF=1>.val in {533 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;534 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;535 let Latency = 2, ReleaseAtCycles = [LMulLat] in {536 defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;537 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;538 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;539 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;540 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;541 defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;542 }543 }544}545foreach mx = SchedMxList in {546 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;547 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;548 let Latency = 3, ReleaseAtCycles = [LMulLat] in549 defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP800VectorArith], mx, IsWorstCase>;550 let Latency = 2, ReleaseAtCycles = [LMulLat] in {551 defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFiveP800VectorArith], mx, IsWorstCase>;552 defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFiveP800VectorArith], mx, IsWorstCase>;553 }554 let Latency = 2, ReleaseAtCycles = [LMulLat] in {555 defm "" : LMULWriteResMX<"WriteVFClassV", [SiFiveP800VectorArith], mx, IsWorstCase>;556 defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFiveP800VectorArith], mx, IsWorstCase>;557 defm "" : LMULWriteResMX<"WriteVFMovV", [SiFiveP800VectorArith], mx, IsWorstCase>;558 }559}560 561// Widening562foreach mx = SchedMxListW in {563 foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {564 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;565 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;566 let Latency = 3, ReleaseAtCycles = [LMulLat] in567 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;568 }569}570foreach mx = SchedMxListFW in {571 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;572 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListFW>.c;573 let Latency = 6, ReleaseAtCycles = [LMulLat] in574 defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP800VectorArith], mx, IsWorstCase>;575}576foreach mx = SchedMxListFW in {577 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {578 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;579 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;580 let Latency = 6, ReleaseAtCycles = [LMulLat] in {581 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;582 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;583 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;584 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;585 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;586 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;587 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;588 }589 }590}591// Narrowing592foreach mx = SchedMxListW in {593 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;594 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListW>.c;595 let Latency = 3, ReleaseAtCycles = [LMulLat] in {596 defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFiveP800VectorArith], mx, IsWorstCase>;597 }598}599foreach mx = SchedMxListFW in {600 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {601 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;602 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;603 let Latency = 3, ReleaseAtCycles = [LMulLat] in {604 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;605 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;606 }607 }608}609 610// Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.611foreach mx = SchedMxListF in {612 foreach sew = SchedSEWSet<mx, 1>.val in {613 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;614 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;615 defvar DivMicroOpLat =616 !cond(!eq(sew, 16): 29, !eq(sew, 32): 25, /* SEW=64 */ true: 37);617 defvar DivLatency = !mul(DivMicroOpLat, LMulLat);618 let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {619 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFiveP800VEXQ1, SiFiveP800VFloatDiv], mx, sew, IsWorstCase>;620 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFiveP800VEXQ1, SiFiveP800VFloatDiv], mx, sew, IsWorstCase>;621 defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFiveP800VEXQ1, SiFiveP800VFloatDiv], mx, sew, IsWorstCase>;622 }623 }624}625 626// 14. Vector Reduction Operations627foreach mx = SchedMxList in {628 foreach sew = SchedSEWSet<mx>.val in {629 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;630 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;631 let Latency = !add(2, !mul(2, LMulLat)), ReleaseAtCycles = [LMulLat] in {632 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFiveP800VEXQ1],633 mx, sew, IsWorstCase>;634 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFiveP800VEXQ1],635 mx, sew, IsWorstCase>;636 }637 }638}639 640foreach mx = SchedMxListWRed in {641 foreach sew = SchedSEWSet<mx, 0, 1>.val in {642 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;643 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;644 let Latency = !add(2, !mul(2, LMulLat)), ReleaseAtCycles = [LMulLat] in {645 defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFiveP800VEXQ1],646 mx, sew, IsWorstCase>;647 }648 }649}650 651foreach mx = SchedMxListF in {652 foreach sew = SchedSEWSet<mx, 1>.val in {653 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;654 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;655 let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {656 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFiveP800VEXQ1],657 mx, sew, IsWorstCase>;658 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From",659 [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;660 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFiveP800VEXQ1],661 mx, sew, IsWorstCase>;662 }663 }664}665 666foreach mx = SchedMxListFWRed in {667 foreach sew = SchedSEWSet<mx, 1, 1>.val in {668 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;669 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;670 let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {671 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFiveP800VEXQ1],672 mx, sew, IsWorstCase>;673 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFiveP800VEXQ1],674 mx, sew, IsWorstCase>;675 }676 }677}678 679// 15. Vector Mask Instructions680foreach mx = SchedMxList in {681 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;682 let Latency = 2, ReleaseAtCycles = [1] in {683 defm "" : LMULWriteResMX<"WriteVMALUV", [SiFiveP800VEXQ0], mx, IsWorstCase>;684 defm "" : LMULWriteResMX<"WriteVMPopV", [SiFiveP800VEXQ0], mx, IsWorstCase>;685 defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFiveP800VEXQ0], mx, IsWorstCase>;686 defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFiveP800VEXQ0], mx, IsWorstCase>;687 }688 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;689 let Latency = 2, ReleaseAtCycles = [LMulLat] in {690 defm "" : LMULWriteResMX<"WriteVIotaV", [SiFiveP800VEXQ0], mx, IsWorstCase>;691 defm "" : LMULWriteResMX<"WriteVIdxV", [SiFiveP800VEXQ0], mx, IsWorstCase>;692 }693}694 695// 16. Vector Permutation Instructions696// Simple Slide697foreach mx = SchedMxList in {698 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;699 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;700 let Latency = 2, ReleaseAtCycles = [LMulLat] in {701 defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP800VEXQ0], mx, IsWorstCase>;702 }703 let Latency = 2, ReleaseAtCycles = [LMulLat] in {704 defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP800VEXQ0], mx, IsWorstCase>;705 defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP800VEXQ0], mx, IsWorstCase>;706 }707}708foreach mx = ["MF8", "MF4", "MF2", "M1"] in {709 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;710 let Latency = 2, ReleaseAtCycles = [1] in {711 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP800VEXQ0], mx, IsWorstCase>;712 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP800VEXQ0], mx, IsWorstCase>;713 }714}715 716// Complex Slide717foreach mx = ["M8", "M4", "M2"] in {718 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;719 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;720 let Latency = !add(4, LMulLat), ReleaseAtCycles = [LMulLat] in {721 // TODO: The latencies and RThroughput for VISlideUpX and VISlideDownX are likely722 // to be different in non-trivial LMUL. Update to the correct numbers here.723 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP800VEXQ1], mx, IsWorstCase>;724 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP800VEXQ1], mx, IsWorstCase>;725 }726}727 728let Latency = 2, ReleaseAtCycles = [1] in {729 def : WriteRes<WriteVMovXS, [SiFiveP800VectorArith]>;730 def : WriteRes<WriteVMovSX, [SiFiveP800VectorArith]>;731}732let Latency = 6, ReleaseAtCycles = [1] in {733 def : WriteRes<WriteVMovFS, [SiFiveP800VectorArith]>;734 def : WriteRes<WriteVMovSF, [SiFiveP800VectorArith]>;735}736 737// Simple Gather and Compress738foreach mx = ["MF8", "MF4", "MF2", "M1"] in {739 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;740 let Latency = 3, ReleaseAtCycles = [1] in {741 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP800VEXQ1], mx, IsWorstCase>;742 }743}744 745foreach mx = ["MF8", "MF4", "MF2", "M1"] in {746 foreach sew = SchedSEWSet<mx>.val in {747 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;748 let Latency = 3, ReleaseAtCycles = [1] in {749 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;750 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;751 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;752 }753 }754}755 756// Complex Gather and Compress757foreach mx = ["M2", "M4", "M8"] in {758 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;759 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;760 let Latency = 6, ReleaseAtCycles = [LMulLat] in {761 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP800VEXQ1], mx, IsWorstCase>;762 }763}764 765foreach mx = ["M2", "M4", "M8"] in {766 foreach sew = SchedSEWSet<mx>.val in {767 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;768 defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;769 let Latency = 6, ReleaseAtCycles = [LMulLat] in {770 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;771 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;772 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;773 }774 }775}776 777// Simple Vrgather.vi778foreach mx = SchedMxList in {779 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;780 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;781 let Latency = 3, ReleaseAtCycles = [LMulLat] in {782 defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFiveP800VEXQ1], mx, IsWorstCase>;783 }784}785 786// Vector Crypto787foreach mx = SchedMxList in {788 defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;789 defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;790 // Zvbb791 let Latency = 2, ReleaseAtCycles = [LMulLat] in {792 defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP800VectorArith], mx, IsWorstCase>;793 defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP800VectorArith], mx, IsWorstCase>;794 defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP800VectorArith], mx, IsWorstCase>;795 defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP800VectorArith], mx, IsWorstCase>;796 defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP800VectorArith], mx, IsWorstCase>;797 defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP800VectorArith], mx, IsWorstCase>;798 defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP800VectorArith], mx, IsWorstCase>;799 }800 // Zvbc801 let Latency = 2, ReleaseAtCycles = [LMulLat] in {802 defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP800VectorArith], mx, IsWorstCase>;803 defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP800VectorArith], mx, IsWorstCase>;804 }805 // Zvkb806 // VANDN uses WriteVIALU[V|X|I]807 let Latency = 2, ReleaseAtCycles = [LMulLat] in {808 defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP800VectorArith], mx, IsWorstCase>;809 defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP800VectorArith], mx, IsWorstCase>;810 defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP800VectorArith], mx, IsWorstCase>;811 defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP800VectorArith], mx, IsWorstCase>;812 defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP800VectorArith], mx, IsWorstCase>;813 }814 // Zvkg815 let Latency = 2, ReleaseAtCycles = [LMulLat] in {816 defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP800VectorArith], mx, IsWorstCase>;817 defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP800VectorArith], mx, IsWorstCase>;818 }819 // ZvknhaOrZvknhb820 let Latency = 3, ReleaseAtCycles = [LMulLat] in {821 defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP800VEXQ0], mx, IsWorstCase>;822 defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP800VEXQ0], mx, IsWorstCase>;823 defvar ZvknhSEWs = !listremove(SchedSEWSet<mx>.val, [8, 16]);824 // Largest SEW is the last element, assuming SchedSEWSet is sorted in ascending825 // order.826 defvar LargestZvknhSEW = !foldl(!head(ZvknhSEWs), ZvknhSEWs, last, curr, curr);827 foreach sew = ZvknhSEWs in {828 // The worst case for Zvknh[ab] is designated to the largest SEW and LMUL.829 defvar IsWorstCaseVSHA2MSV = !and(IsWorstCase, !eq(sew, LargestZvknhSEW));830 defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SiFiveP800VEXQ0], mx, sew,831 IsWorstCaseVSHA2MSV>;832 }833 }834 // Zvkned835 let Latency = 2, ReleaseAtCycles = [LMulLat] in {836 defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP800VectorArith], mx, IsWorstCase>;837 defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP800VectorArith], mx, IsWorstCase>;838 defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP800VectorArith], mx, IsWorstCase>;839 defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP800VectorArith], mx, IsWorstCase>;840 }841 // Zvksed842 let Latency = 3, ReleaseAtCycles = [SiFiveP800VSM3CCycles<mx>.c] in843 defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP800VEXQ0], mx, IsWorstCase>;844 let Latency = 6, ReleaseAtCycles = [LMulLat] in845 defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP800VEXQ0], mx, IsWorstCase>;846 let Latency = 3, ReleaseAtCycles = [LMulLat] in {847 defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP800VEXQ0], mx, IsWorstCase>;848 defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP800VEXQ0], mx, IsWorstCase>;849 }850}851 852// Others853def : WriteRes<WriteCSR, [SiFiveP800SYS]>;854def : WriteRes<WriteNop, []>;855def : WriteRes<WriteRdVLENB, [SiFiveP800SYS]>;856 857// FIXME: This could be better modeled by looking at the regclasses of the operands.858def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;859 860//===----------------------------------------------------------------------===//861// Bypass and advance862def : ReadAdvance<ReadJmp, 0>;863def : ReadAdvance<ReadJalr, 0>;864def : ReadAdvance<ReadCSR, 0>;865def : ReadAdvance<ReadStoreData, 0>;866def : ReadAdvance<ReadMemBase, 0>;867def : ReadAdvance<ReadIALU, 0>;868def : ReadAdvance<ReadIALU32, 0>;869def : ReadAdvance<ReadShiftImm, 0>;870def : ReadAdvance<ReadShiftImm32, 0>;871def : ReadAdvance<ReadShiftReg, 0>;872def : ReadAdvance<ReadShiftReg32, 0>;873def : ReadAdvance<ReadIDiv, 0>;874def : ReadAdvance<ReadIDiv32, 0>;875def : ReadAdvance<ReadIRem, 0>;876def : ReadAdvance<ReadIRem32, 0>;877def : ReadAdvance<ReadIMul, 0>;878def : ReadAdvance<ReadIMul32, 0>;879def : ReadAdvance<ReadAtomicWA, 0>;880def : ReadAdvance<ReadAtomicWD, 0>;881def : ReadAdvance<ReadAtomicDA, 0>;882def : ReadAdvance<ReadAtomicDD, 0>;883def : ReadAdvance<ReadAtomicLDW, 0>;884def : ReadAdvance<ReadAtomicLDD, 0>;885def : ReadAdvance<ReadAtomicSTW, 0>;886def : ReadAdvance<ReadAtomicSTD, 0>;887def : ReadAdvance<ReadFStoreData, 0>;888def : ReadAdvance<ReadFMemBase, 0>;889def : ReadAdvance<ReadFAdd16, 0>;890def : ReadAdvance<ReadFAdd32, 0>;891def : ReadAdvance<ReadFAdd64, 0>;892def : ReadAdvance<ReadFMul16, 0>;893def : ReadAdvance<ReadFMA16, 0>;894def : ReadAdvance<ReadFMA16Addend, 2, [WriteFMA16]>;895def : ReadAdvance<ReadFMul32, 0>;896def : ReadAdvance<ReadFMA32, 0>;897def : ReadAdvance<ReadFMA32Addend, 2, [WriteFMA32]>;898def : ReadAdvance<ReadFMul64, 0>;899def : ReadAdvance<ReadFMA64, 0>;900def : ReadAdvance<ReadFMA64Addend, 2, [WriteFMA64]>;901def : ReadAdvance<ReadFDiv16, 0>;902def : ReadAdvance<ReadFDiv32, 0>;903def : ReadAdvance<ReadFDiv64, 0>;904def : ReadAdvance<ReadFSqrt16, 0>;905def : ReadAdvance<ReadFSqrt32, 0>;906def : ReadAdvance<ReadFSqrt64, 0>;907def : ReadAdvance<ReadFCmp16, 0>;908def : ReadAdvance<ReadFCmp32, 0>;909def : ReadAdvance<ReadFCmp64, 0>;910def : ReadAdvance<ReadFSGNJ16, 0>;911def : ReadAdvance<ReadFSGNJ32, 0>;912def : ReadAdvance<ReadFSGNJ64, 0>;913def : ReadAdvance<ReadFMinMax16, 0>;914def : ReadAdvance<ReadFMinMax32, 0>;915def : ReadAdvance<ReadFMinMax64, 0>;916def : ReadAdvance<ReadFCvtF16ToI32, 0>;917def : ReadAdvance<ReadFCvtF16ToI64, 0>;918def : ReadAdvance<ReadFCvtF32ToI32, 0>;919def : ReadAdvance<ReadFCvtF32ToI64, 0>;920def : ReadAdvance<ReadFCvtF64ToI32, 0>;921def : ReadAdvance<ReadFCvtF64ToI64, 0>;922def : ReadAdvance<ReadFCvtI32ToF16, 0>;923def : ReadAdvance<ReadFCvtI32ToF32, 0>;924def : ReadAdvance<ReadFCvtI32ToF64, 0>;925def : ReadAdvance<ReadFCvtI64ToF16, 0>;926def : ReadAdvance<ReadFCvtI64ToF32, 0>;927def : ReadAdvance<ReadFCvtI64ToF64, 0>;928def : ReadAdvance<ReadFCvtF32ToF64, 0>;929def : ReadAdvance<ReadFCvtF64ToF32, 0>;930def : ReadAdvance<ReadFCvtF16ToF32, 0>;931def : ReadAdvance<ReadFCvtF32ToF16, 0>;932def : ReadAdvance<ReadFCvtF16ToF64, 0>;933def : ReadAdvance<ReadFCvtF64ToF16, 0>;934def : ReadAdvance<ReadFRoundF16, 0>;935def : ReadAdvance<ReadFRoundF32, 0>;936def : ReadAdvance<ReadFRoundF64, 0>;937def : ReadAdvance<ReadFMovF16ToI16, 0>;938def : ReadAdvance<ReadFMovI16ToF16, 0>;939def : ReadAdvance<ReadFMovF32ToI32, 0>;940def : ReadAdvance<ReadFMovI32ToF32, 0>;941def : ReadAdvance<ReadFMovF64ToI64, 0>;942def : ReadAdvance<ReadFMovI64ToF64, 0>;943def : ReadAdvance<ReadFClass16, 0>;944def : ReadAdvance<ReadFClass32, 0>;945def : ReadAdvance<ReadFClass64, 0>;946 947// Bitmanip948def : ReadAdvance<ReadRotateImm, 0>;949def : ReadAdvance<ReadRotateImm32, 0>;950def : ReadAdvance<ReadRotateReg, 0>;951def : ReadAdvance<ReadRotateReg32, 0>;952def : ReadAdvance<ReadCLZ, 0>;953def : ReadAdvance<ReadCLZ32, 0>;954def : ReadAdvance<ReadCTZ, 0>;955def : ReadAdvance<ReadCTZ32, 0>;956def : ReadAdvance<ReadCPOP, 0>;957def : ReadAdvance<ReadCPOP32, 0>;958def : ReadAdvance<ReadORCB, 0>;959def : ReadAdvance<ReadIMinMax, 0>;960def : ReadAdvance<ReadREV8, 0>;961def : ReadAdvance<ReadSHXADD, 0>;962def : ReadAdvance<ReadSHXADD32, 0>;963def : ReadAdvance<ReadSingleBit, 0>;964def : ReadAdvance<ReadSingleBitImm, 0>;965 966// 6. Configuration-Setting Instructions967def : ReadAdvance<ReadVSETVLI, 0>;968def : ReadAdvance<ReadVSETVL, 0>;969 970// 7. Vector Loads and Stores971def : ReadAdvance<ReadVLDX, 0>;972def : ReadAdvance<ReadVSTX, 0>;973defm "" : LMULReadAdvance<"ReadVSTEV", 0>;974defm "" : LMULReadAdvance<"ReadVSTM", 0>;975def : ReadAdvance<ReadVLDSX, 0>;976def : ReadAdvance<ReadVSTSX, 0>;977defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;978defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;979defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;980defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;981defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;982defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;983defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;984defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;985defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;986defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;987defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;988defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;989defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;990defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;991defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;992defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;993defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;994defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;995defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;996defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;997defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;998defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;999defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;1000defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;1001// LMUL Aware1002def : ReadAdvance<ReadVST1R, 0>;1003def : ReadAdvance<ReadVST2R, 0>;1004def : ReadAdvance<ReadVST4R, 0>;1005def : ReadAdvance<ReadVST8R, 0>;1006 1007// 12. Vector Integer Arithmetic Instructions1008defm : LMULReadAdvance<"ReadVIALUV", 0>;1009defm : LMULReadAdvance<"ReadVIALUX", 0>;1010defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;1011defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;1012defm : LMULReadAdvance<"ReadVExtV", 0>;1013defm : LMULReadAdvance<"ReadVICALUV", 0>;1014defm : LMULReadAdvance<"ReadVICALUX", 0>;1015defm : LMULReadAdvance<"ReadVShiftV", 0>;1016defm : LMULReadAdvance<"ReadVShiftX", 0>;1017defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;1018defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;1019defm : LMULReadAdvance<"ReadVICmpV", 0>;1020defm : LMULReadAdvance<"ReadVICmpX", 0>;1021defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;1022defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;1023defm : LMULReadAdvance<"ReadVIMulV", 0>;1024defm : LMULReadAdvance<"ReadVIMulX", 0>;1025defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;1026defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;1027defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;1028defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;1029defm : LMULReadAdvance<"ReadVIMulAddV", 0>;1030defm : LMULReadAdvance<"ReadVIMulAddX", 0>;1031defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;1032defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;1033defm : LMULReadAdvance<"ReadVIMergeV", 0>;1034defm : LMULReadAdvance<"ReadVIMergeX", 0>;1035defm : LMULReadAdvance<"ReadVIMovV", 0>;1036defm : LMULReadAdvance<"ReadVIMovX", 0>;1037 1038// 13. Vector Fixed-Point Arithmetic Instructions1039defm "" : LMULReadAdvance<"ReadVSALUV", 0>;1040defm "" : LMULReadAdvance<"ReadVSALUX", 0>;1041defm "" : LMULReadAdvance<"ReadVAALUV", 0>;1042defm "" : LMULReadAdvance<"ReadVAALUX", 0>;1043defm "" : LMULReadAdvance<"ReadVSMulV", 0>;1044defm "" : LMULReadAdvance<"ReadVSMulX", 0>;1045defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;1046defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;1047defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;1048defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;1049 1050// 14. Vector Floating-Point Instructions1051defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;1052defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;1053defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;1054defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;1055defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;1056defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;1057defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;1058defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;1059defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;1060defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;1061defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;1062defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;1063defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;1064defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;1065defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;1066defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;1067defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;1068defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;1069defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;1070defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;1071defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;1072defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;1073defm "" : LMULReadAdvance<"ReadVFClassV", 0>;1074defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;1075defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;1076defm "" : LMULReadAdvance<"ReadVFMovF", 0>;1077defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;1078defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;1079defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;1080defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;1081defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;1082defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;1083defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;1084defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;1085 1086// 15. Vector Reduction Operations1087def : ReadAdvance<ReadVIRedV, 0>;1088def : ReadAdvance<ReadVIRedV0, 0>;1089def : ReadAdvance<ReadVIWRedV, 0>;1090def : ReadAdvance<ReadVIWRedV0, 0>;1091def : ReadAdvance<ReadVFRedV, 0>;1092def : ReadAdvance<ReadVFRedV0, 0>;1093def : ReadAdvance<ReadVFRedOV, 0>;1094def : ReadAdvance<ReadVFRedOV0, 0>;1095def : ReadAdvance<ReadVFWRedV, 0>;1096def : ReadAdvance<ReadVFWRedV0, 0>;1097def : ReadAdvance<ReadVFWRedOV, 0>;1098def : ReadAdvance<ReadVFWRedOV0, 0>;1099 1100// 16. Vector Mask Instructions1101defm "" : LMULReadAdvance<"ReadVMALUV", 0>;1102defm "" : LMULReadAdvance<"ReadVMPopV", 0>;1103defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;1104defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;1105defm "" : LMULReadAdvance<"ReadVIotaV", 0>;1106 1107// 17. Vector Permutation Instructions1108def : ReadAdvance<ReadVMovXS, 0>;1109def : ReadAdvance<ReadVMovSX_V, 0>;1110def : ReadAdvance<ReadVMovSX_X, 0>;1111def : ReadAdvance<ReadVMovFS, 0>;1112def : ReadAdvance<ReadVMovSF_V, 0>;1113def : ReadAdvance<ReadVMovSF_F, 0>;1114defm "" : LMULReadAdvance<"ReadVISlideV", 0>;1115defm "" : LMULReadAdvance<"ReadVISlideX", 0>;1116defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;1117defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;1118defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;1119defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;1120defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;1121defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;1122defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;1123defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;1124defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;1125defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;1126// LMUL Aware1127def : ReadAdvance<ReadVMov1V, 0>;1128def : ReadAdvance<ReadVMov2V, 0>;1129def : ReadAdvance<ReadVMov4V, 0>;1130def : ReadAdvance<ReadVMov8V, 0>;1131 1132// Vector Crypto Extensions1133// Zvbb1134defm "" : LMULReadAdvance<"ReadVBREVV", 0>;1135defm "" : LMULReadAdvance<"ReadVCLZV", 0>;1136defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;1137defm "" : LMULReadAdvance<"ReadVCTZV", 0>;1138defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;1139defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;1140// Zvbc1141defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;1142defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;1143// Zvkb1144// VANDN uses ReadVIALU[V|X|I]1145defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;1146defm "" : LMULReadAdvance<"ReadVREV8V", 0>;1147defm "" : LMULReadAdvance<"ReadVRotV", 0>;1148defm "" : LMULReadAdvance<"ReadVRotX", 0>;1149// Zvkg1150defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;1151defm "" : LMULReadAdvance<"ReadVGMULV", 0>;1152// Zvknha or Zvknhb1153defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;1154defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;1155defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>;1156// Zvkned1157defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;1158defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;1159defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;1160defm "" : LMULReadAdvance<"ReadVAESZV", 0>;1161// Zvksed1162defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;1163defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;1164// Zbksh1165defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;1166defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;1167 1168// Others1169def : ReadAdvance<ReadVMask, 0>;1170def : ReadAdvance<ReadVPassthru_WorstCase, 0>;1171foreach mx = SchedMxList in {1172 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;1173 foreach sew = SchedSEWSet<mx>.val in1174 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;1175}1176 1177//===----------------------------------------------------------------------===//1178// Unsupported extensions1179defm : UnsupportedSchedQ;1180defm : UnsupportedSchedZabha;1181defm : UnsupportedSchedZbc;1182defm : UnsupportedSchedZbkb;1183defm : UnsupportedSchedZbkx;1184defm : UnsupportedSchedSFB;1185defm : UnsupportedSchedZfaWithQ;1186defm : UnsupportedSchedXsf;1187}1188