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1//=- RISCVSchedSpacemitX60.td - Spacemit X60 Scheduling Defs -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10//11// Scheduler model for the SpacemiT-X60 processor based on documentation of the12// C908 and experiments on real hardware (bpi-f3).13//14//===----------------------------------------------------------------------===//15 16//===----------------------------------------------------------------------===//17// Helpers18 19// Maps LMUL string to corresponding value from the Values array20// LMUL values map to array indices as follows:21// MF8 -> Values[0], MF4 -> Values[1], MF2 -> Values[2], M1 -> Values[3],22// M2 -> Values[4], M4 -> Values[5], M8 -> Values[6]23// Shorter lists are allowed, e.g., widening instructions don't work on M824class GetLMULValue<list<int> Values, string LMUL> {25 defvar Index = !cond(26 !eq(LMUL, "MF8"): 0,27 !eq(LMUL, "MF4"): 1,28 !eq(LMUL, "MF2"): 2,29 !eq(LMUL, "M1"): 3,30 !eq(LMUL, "M2"): 4,31 !eq(LMUL, "M4"): 5,32 !eq(LMUL, "M8"): 6,33 );34 35 assert !lt(Index, !size(Values)),36 "Missing LMUL value for '" # LMUL # "'. " #37 "Expected at least " # !add(Index, 1) # " elements, but got " #38 !size(Values) # ".";39 40 int c = Values[Index];41}42 43// Returns BaseValue for LMUL values before startLMUL, Value for startLMUL,44// then doubles Value for each subsequent LMUL45// Example: ConstValueUntilLMULThenDoubleBase<"M1", 2, 4, "M8"> returns:46// MF8->2, MF4->2, MF2->2, M1->4, M2->8, M4->16, M8->3247// This is useful for modeling scheduling parameters that scale with LMUL.48class ConstValueUntilLMULThenDoubleBase<string startLMUL, int BaseValue, int Value, string currentLMUL> {49 assert !le(BaseValue, Value), "BaseValue must be less-equal to Value";50 defvar startPos = GetLMULValue<[0, 1, 2, 3, 4, 5, 6], startLMUL>.c;51 defvar currentPos = GetLMULValue<[0, 1, 2, 3, 4, 5, 6], currentLMUL>.c;52 53 // Calculate the difference in positions54 defvar posDiff = !sub(currentPos, startPos);55 56 // Calculate Value * (2^posDiff)57 int c = !cond(58 !eq(posDiff, 0) : Value,59 !eq(posDiff, 1) : !mul(Value, 2),60 !eq(posDiff, 2) : !mul(Value, 4),61 !eq(posDiff, 3) : !mul(Value, 8),62 !eq(posDiff, 4) : !mul(Value, 16),63 !eq(posDiff, 5) : !mul(Value, 32),64 !eq(posDiff, 6) : !mul(Value, 64),65 true : BaseValue66 );67}68 69// Same as the previous function but BaseValue == Value70class ConstValueUntilLMULThenDouble<string startLMUL, int Value, string currentLMUL> {71 int c = ConstValueUntilLMULThenDoubleBase<startLMUL, Value, Value, currentLMUL>.c;72}73 74// Returns MF8->1, MF4->1, MF2->2, M1->4, M2->8, M4->16, M8->3275class ConstOneUntilMF4ThenDouble<string mx> {76 int c = ConstValueUntilLMULThenDouble<"MF4", 1, mx>.c;77}78 79// Returns MF8->1, MF4->1, MF2->1, M1->2, M2->4, M4->8, M8->1680class ConstOneUntilMF2ThenDouble<string mx> {81 int c = ConstValueUntilLMULThenDouble<"MF2", 1, mx>.c;82}83 84// Returns MF8->1, MF4->1, MF2->1, M1->1, M2->2, M4->4, M8->885class ConstOneUntilM1ThenDouble<string mx> {86 int c = ConstValueUntilLMULThenDouble<"M1", 1, mx>.c;87}88 89//===----------------------------------------------------------------------===//90// Latency helper classes91 92// Used for: arithmetic (add/sub/min/max), saturating/averaging, FP add/sub/min/max93class Get4458Latency<string mx> {94 int c = GetLMULValue<[/*MF8=*/4, /*MF4=*/4, /*MF2=*/4, /*M1=*/4, /*M2=*/4, /*M4=*/5, /*M8=*/8], mx>.c;95}96 97// Used for: widening operations (no M8)98class Get4588Latency<string mx> {99 int c = GetLMULValue<[/*MF8=*/4, /*MF4=*/4, /*MF2=*/4, /*M1=*/4, /*M2=*/5, /*M4=*/8], mx>.c;100}101 102// Used for: mask-producing comparisons, carry ops with mask, FP comparisons103class Get461018Latency<string mx> {104 int c = GetLMULValue<[/*MF8=*/4, /*MF4=*/4, /*MF2=*/4, /*M1=*/4, /*M2=*/6, /*M4=*/10, /*M8=*/18], mx>.c;105}106 107// Used for: FP FMA operations, complex FP ops108class Get6678Latency<string mx> {109 int c = GetLMULValue<[/*MF8=*/6, /*MF4=*/6, /*MF2=*/6, /*M1=*/6, /*M2=*/6, /*M4=*/7, /*M8=*/8], mx>.c;110}111 112//===----------------------------------------------------------------------===//113 114class SMX60IsWorstCaseMX<string mx, list<string> MxList> {115 string LLMUL = LargestLMUL<MxList>.r;116 bit c = !eq(mx, LLMUL);117}118 119class SMX60IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {120 string LLMUL = LargestLMUL<MxList>.r;121 int SSEW = SmallestSEW<mx, isF>.r;122 bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));123}124 125defvar SMX60VLEN = 256;126defvar SMX60DLEN = !div(SMX60VLEN, 2);127 128def SpacemitX60Model : SchedMachineModel {129 let IssueWidth = 2; // dual-issue130 let MicroOpBufferSize = 0; // in-order131 let LoadLatency = 3; // worse case: >= 3132 let MispredictPenalty = 9; // nine-stage133 134 let CompleteModel = 0;135 136 let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,137 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr];138}139 140let SchedModel = SpacemitX60Model in {141 142//===----------------------------------------------------------------------===//143// Define processor resources for Spacemit-X60144 145// Information gathered from the C908 user manual:146let BufferSize = 0 in {147 // The LSU supports dual issue for scalar store/load instructions148 def SMX60_LS : ProcResource<2>;149 150 // An IEU can decode and issue two instructions at the same time151 def SMX60_IEUA : ProcResource<1>;152 def SMX60_IEUB : ProcResource<1>;153 def SMX60_IEU : ProcResGroup<[SMX60_IEUA, SMX60_IEUB]>;154 155 // Although the X60 does appear to support multiple issue for at least some156 // floating point instructions, this model assumes single issue as157 // increasing it reduces the gains we saw in performance158 def SMX60_FP : ProcResource<1>;159 160 // Vector pipeline161 // Single issue for vector store/load instructions162 def SMX60_VLS : ProcResource<1>;163 164 // The C908 user manual says: "Vector floating-point units support vector165 // floating-point computation of different bits. In addition, vector integer166 // units are added". Developer confirmed it's a separate VIEU167 def SMX60_VIEU : ProcResource<1>;168 169 // The C908 user manual says: "The vector execution unit is developed by170 // extending the floating-point unit", so let's assume single issue for now171 def SMX60_VFP : ProcResource<1>;172}173 174//===----------------------------------------------------------------------===//175 176// Branching177def : WriteRes<WriteJmp, [SMX60_IEUA]>;178def : WriteRes<WriteJal, [SMX60_IEUA]>;179def : WriteRes<WriteJalr, [SMX60_IEUA]>;180 181// Integer arithmetic and logic182// Latency of ALU instructions is 1, but add.uw is 2183def : WriteRes<WriteIALU32, [SMX60_IEU]>;184def : WriteRes<WriteIALU, [SMX60_IEU]>;185def : WriteRes<WriteShiftImm32, [SMX60_IEU]>;186def : WriteRes<WriteShiftImm, [SMX60_IEU]>;187def : WriteRes<WriteShiftReg32, [SMX60_IEU]>;188def : WriteRes<WriteShiftReg, [SMX60_IEU]>;189 190// Integer multiplication191def : WriteRes<WriteIMul32, [SMX60_IEU]> { let Latency = 3; }192 193// The latency of mul is 5, while in mulh, mulhsu, mulhu is 6194// Worst case latency is used195def : WriteRes<WriteIMul, [SMX60_IEU]> { let Latency = 6; }196 197// Integer division/remainder198// TODO: Latency set based on C908 datasheet and hasn't been199// confirmed experimentally.200let Latency = 12, ReleaseAtCycles = [12] in {201 def : WriteRes<WriteIDiv32, [SMX60_IEUA]>;202 def : WriteRes<WriteIRem32, [SMX60_IEUA]>;203}204let Latency = 20, ReleaseAtCycles = [20] in {205 def : WriteRes<WriteIDiv, [SMX60_IEUA]>;206 def : WriteRes<WriteIRem, [SMX60_IEUA]>;207}208 209// Bitmanip210def : WriteRes<WriteRotateImm, [SMX60_IEU]>;211def : WriteRes<WriteRotateImm32, [SMX60_IEU]>;212def : WriteRes<WriteRotateReg, [SMX60_IEU]>;213def : WriteRes<WriteRotateReg32, [SMX60_IEU]>;214 215def : WriteRes<WriteCLZ, [SMX60_IEU]>;216def : WriteRes<WriteCLZ32, [SMX60_IEU]>;217def : WriteRes<WriteCTZ, [SMX60_IEU]>;218def : WriteRes<WriteCTZ32, [SMX60_IEU]>;219 220let Latency = 2 in {221 def : WriteRes<WriteCPOP, [SMX60_IEU]>;222 def : WriteRes<WriteCPOP32, [SMX60_IEU]>;223}224 225def : WriteRes<WriteORCB, [SMX60_IEU]>;226def : WriteRes<WriteIMinMax, [SMX60_IEU]>;227def : WriteRes<WriteREV8, [SMX60_IEU]>;228 229let Latency = 2 in {230 def : WriteRes<WriteSHXADD, [SMX60_IEU]>;231 def : WriteRes<WriteSHXADD32, [SMX60_IEU]>;232 def : WriteRes<WriteCLMUL, [SMX60_IEU]>;233}234 235// Single-bit instructions236def : WriteRes<WriteSingleBit, [SMX60_IEU]>;237def : WriteRes<WriteSingleBitImm, [SMX60_IEU]>;238def : WriteRes<WriteBEXT, [SMX60_IEU]>;239def : WriteRes<WriteBEXTI, [SMX60_IEU]>;240 241// Memory/Atomic memory242let Latency = 4 in {243 def : WriteRes<WriteSTB, [SMX60_LS]>;244 def : WriteRes<WriteSTH, [SMX60_LS]>;245 def : WriteRes<WriteSTW, [SMX60_LS]>;246 def : WriteRes<WriteSTD, [SMX60_LS]>;247 def : WriteRes<WriteFST16, [SMX60_LS]>;248 def : WriteRes<WriteFST32, [SMX60_LS]>;249 def : WriteRes<WriteFST64, [SMX60_LS]>;250 251 def : WriteRes<WriteLDB, [SMX60_LS]>;252 def : WriteRes<WriteLDH, [SMX60_LS]>;253 def : WriteRes<WriteLDW, [SMX60_LS]>;254 def : WriteRes<WriteLDD, [SMX60_LS]>;255 def : WriteRes<WriteFLD16, [SMX60_LS]>;256 def : WriteRes<WriteFLD32, [SMX60_LS]>;257 def : WriteRes<WriteFLD64, [SMX60_LS]>;258}259 260// Atomics261let Latency = 8 in {262 def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;263 def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;264 def : WriteRes<WriteAtomicLDW, [SMX60_LS]>;265 def : WriteRes<WriteAtomicLDD, [SMX60_LS]>;266}267 268let Latency = 12 in {269 def : WriteRes<WriteAtomicW, [SMX60_LS]>;270 def : WriteRes<WriteAtomicD, [SMX60_LS]>;271}272 273// Floating point units Half precision274let Latency = 4 in {275 def : WriteRes<WriteFAdd16, [SMX60_FP]>;276 def : WriteRes<WriteFMul16, [SMX60_FP]>;277 def : WriteRes<WriteFSGNJ16, [SMX60_FP]>;278 def : WriteRes<WriteFMinMax16, [SMX60_FP]>;279}280def : WriteRes<WriteFMA16, [SMX60_FP]> { let Latency = 5; }281 282let Latency = 12, ReleaseAtCycles = [12] in {283 def : WriteRes<WriteFDiv16, [SMX60_FP]>;284 def : WriteRes<WriteFSqrt16, [SMX60_FP]>;285}286 287// Single precision288let Latency = 4 in {289 def : WriteRes<WriteFAdd32, [SMX60_FP]>;290 def : WriteRes<WriteFMul32, [SMX60_FP]>;291 def : WriteRes<WriteFSGNJ32, [SMX60_FP]>;292 def : WriteRes<WriteFMinMax32, [SMX60_FP]>;293}294def : WriteRes<WriteFMA32, [SMX60_FP]> { let Latency = 5; }295 296let Latency = 15, ReleaseAtCycles = [15] in {297 def : WriteRes<WriteFDiv32, [SMX60_FP]>;298 def : WriteRes<WriteFSqrt32, [SMX60_FP]>;299}300 301// Double precision302let Latency = 5 in {303 def : WriteRes<WriteFAdd64, [SMX60_FP]>;304 def : WriteRes<WriteFMul64, [SMX60_FP]>;305 def : WriteRes<WriteFSGNJ64, [SMX60_FP]>;306}307def : WriteRes<WriteFMinMax64, [SMX60_FP]> { let Latency = 4; }308def : WriteRes<WriteFMA64, [SMX60_FP]> { let Latency = 6; }309 310let Latency = 22, ReleaseAtCycles = [22] in {311 def : WriteRes<WriteFDiv64, [SMX60_FP]>;312 def : WriteRes<WriteFSqrt64, [SMX60_FP]>;313}314 315// Conversions316let Latency = 6 in {317 def : WriteRes<WriteFCvtF16ToI32, [SMX60_IEU]>;318 def : WriteRes<WriteFCvtF32ToI32, [SMX60_IEU]>;319 def : WriteRes<WriteFCvtF32ToI64, [SMX60_IEU]>;320 def : WriteRes<WriteFCvtF64ToI64, [SMX60_IEU]>;321 def : WriteRes<WriteFCvtF64ToI32, [SMX60_IEU]>;322 def : WriteRes<WriteFCvtF16ToI64, [SMX60_IEU]>;323}324 325let Latency = 4 in {326 def : WriteRes<WriteFCvtI32ToF16, [SMX60_IEU]>;327 def : WriteRes<WriteFCvtI32ToF32, [SMX60_IEU]>;328 def : WriteRes<WriteFCvtI32ToF64, [SMX60_IEU]>;329 def : WriteRes<WriteFCvtI64ToF16, [SMX60_IEU]>;330 def : WriteRes<WriteFCvtI64ToF32, [SMX60_IEU]>;331 def : WriteRes<WriteFCvtI64ToF64, [SMX60_IEU]>;332 def : WriteRes<WriteFCvtF16ToF32, [SMX60_FP]>;333 def : WriteRes<WriteFCvtF16ToF64, [SMX60_FP]>;334 def : WriteRes<WriteFCvtF32ToF16, [SMX60_FP]>;335 def : WriteRes<WriteFCvtF32ToF64, [SMX60_FP]>;336 def : WriteRes<WriteFCvtF64ToF16, [SMX60_FP]>;337 def : WriteRes<WriteFCvtF64ToF32, [SMX60_FP]>;338}339 340let Latency = 6 in {341 def : WriteRes<WriteFClass16, [SMX60_FP]>;342 def : WriteRes<WriteFClass32, [SMX60_FP]>;343 def : WriteRes<WriteFClass64, [SMX60_FP]>;344 345 def : WriteRes<WriteFCmp16, [SMX60_FP]>;346 def : WriteRes<WriteFCmp32, [SMX60_FP]>;347 def : WriteRes<WriteFCmp64, [SMX60_FP]>;348 349 def : WriteRes<WriteFMovF32ToI32, [SMX60_IEU]>;350 def : WriteRes<WriteFMovF16ToI16, [SMX60_IEU]>;351}352 353let Latency = 4 in {354 def : WriteRes<WriteFMovI16ToF16, [SMX60_IEU]>;355 def : WriteRes<WriteFMovF64ToI64, [SMX60_IEU]>;356 def : WriteRes<WriteFMovI64ToF64, [SMX60_IEU]>;357 def : WriteRes<WriteFMovI32ToF32, [SMX60_IEU]>;358}359 360// 6. Configuration-Setting Instructions361def : WriteRes<WriteVSETVLI, [SMX60_IEUA]>;362def : WriteRes<WriteVSETIVLI, [SMX60_IEUA]>;363def : WriteRes<WriteVSETVL, [SMX60_IEUA]>;364 365// 7. Vector Loads and Stores366foreach mx = SchedMxList in {367 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;368 369 // Unit-stride loads and stores370 defm "" : LMULWriteResMX<"WriteVLDE", [SMX60_VLS], mx, IsWorstCase>;371 defm "" : LMULWriteResMX<"WriteVLDFF", [SMX60_VLS], mx, IsWorstCase>;372 defm "" : LMULWriteResMX<"WriteVSTE", [SMX60_VLS], mx, IsWorstCase>;373 374 // Mask loads and stores375 defm "" : LMULWriteResMX<"WriteVLDM", [SMX60_VLS], mx, IsWorstCase=!eq(mx, "M1")>;376 defm "" : LMULWriteResMX<"WriteVSTM", [SMX60_VLS], mx, IsWorstCase=!eq(mx, "M1")>;377 378 // Strided and indexed loads and stores379 foreach eew = [8, 16, 32, 64] in {380 defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SMX60_VLS], mx, IsWorstCase>;381 defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SMX60_VLS], mx, IsWorstCase>;382 defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SMX60_VLS], mx, IsWorstCase>;383 384 defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SMX60_VLS], mx, IsWorstCase>;385 defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SMX60_VLS], mx, IsWorstCase>;386 defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SMX60_VLS], mx, IsWorstCase>;387 }388}389 390// Segmented loads and stores391foreach mx = SchedMxList in {392 foreach nf=2-8 in {393 foreach eew = [8, 16, 32, 64] in {394 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;395 396 // Unit-stride segmented397 defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;398 defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;399 defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;400 401 // Strided/indexed segmented402 defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;403 defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;404 405 // Indexed segmented406 defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;407 defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;408 defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;409 defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" #eew, [SMX60_VLS], mx, IsWorstCase>;410 }411 }412}413 414// Whole register move/load/store415foreach LMul = [1, 2, 4, 8] in {416 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SMX60_VLS]>;417 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SMX60_VLS]>;418 419 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SMX60_VIEU]>;420}421 422// 11. Vector Integer Arithmetic Instructions423foreach mx = SchedMxList in {424 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;425 426 let Latency = Get4458Latency<mx>.c, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {427 defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SMX60_VIEU], mx, IsWorstCase>;428 defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SMX60_VIEU], mx, IsWorstCase>;429 }430 431 // Latency of vadd, vsub, vrsub: 4/4/5/8432 // ReleaseAtCycles of vadd, vsub, vrsub: 1/2/4/8433 // Latency of vand, vor, vxor: 4/4/8/16434 // ReleaseAtCycles of vand, vor, vxor: 2/4/8/16435 // They are grouped together, so we used the worst case 4/4/8/16 and 2/4/8/16436 // TODO: use InstRW to override individual instructions' scheduling data437 defvar VIALULat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;438 defvar VIALUOcc = ConstOneUntilMF2ThenDouble<mx>.c;439 let Latency = VIALULat, ReleaseAtCycles = [VIALUOcc] in {440 defm "" : LMULWriteResMX<"WriteVIALUV", [SMX60_VIEU], mx, IsWorstCase>;441 defm "" : LMULWriteResMX<"WriteVIALUX", [SMX60_VIEU], mx, IsWorstCase>;442 defm "" : LMULWriteResMX<"WriteVIALUI", [SMX60_VIEU], mx, IsWorstCase>;443 }444 445 defvar VILogicalLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;446 defvar VILogicalOcc = ConstValueUntilLMULThenDouble<"MF2", 1, mx>.c;447 let Latency = VILogicalLat, ReleaseAtCycles = [VILogicalOcc] in {448 defm "" : LMULWriteResMX<"WriteVExtV", [SMX60_VIEU], mx, IsWorstCase>;449 defm "" : LMULWriteResMX<"WriteVIMergeV", [SMX60_VIEU], mx, IsWorstCase>;450 defm "" : LMULWriteResMX<"WriteVIMergeX", [SMX60_VIEU], mx, IsWorstCase>;451 defm "" : LMULWriteResMX<"WriteVIMergeI", [SMX60_VIEU], mx, IsWorstCase>;452 defm "" : LMULWriteResMX<"WriteVIMovV", [SMX60_VIEU], mx, IsWorstCase>;453 defm "" : LMULWriteResMX<"WriteVIMovX", [SMX60_VIEU], mx, IsWorstCase>;454 defm "" : LMULWriteResMX<"WriteVIMovI", [SMX60_VIEU], mx, IsWorstCase>;455 defm "" : LMULWriteResMX<"WriteVShiftV", [SMX60_VIEU], mx, IsWorstCase>;456 defm "" : LMULWriteResMX<"WriteVShiftX", [SMX60_VIEU], mx, IsWorstCase>;457 defm "" : LMULWriteResMX<"WriteVShiftI", [SMX60_VIEU], mx, IsWorstCase>;458 459 defm "" : LMULWriteResMX<"WriteVICALUV", [SMX60_VIEU], mx, IsWorstCase>;460 defm "" : LMULWriteResMX<"WriteVICALUX", [SMX60_VIEU], mx, IsWorstCase>;461 defm "" : LMULWriteResMX<"WriteVICALUI", [SMX60_VIEU], mx, IsWorstCase>;462 }463 464 // Slightly increase Occ when LMUL == M8465 defvar VICmpCarryOcc = GetLMULValue<[1, 1, 1, 2, 4, 8, 18], mx>.c;466 let Latency = Get461018Latency<mx>.c, ReleaseAtCycles = [VICmpCarryOcc] in {467 defm "" : LMULWriteResMX<"WriteVICALUMV", [SMX60_VIEU], mx, IsWorstCase>;468 defm "" : LMULWriteResMX<"WriteVICALUMX", [SMX60_VIEU], mx, IsWorstCase>;469 defm "" : LMULWriteResMX<"WriteVICALUMI", [SMX60_VIEU], mx, IsWorstCase>;470 defm "" : LMULWriteResMX<"WriteVICmpV", [SMX60_VIEU], mx, IsWorstCase>;471 defm "" : LMULWriteResMX<"WriteVICmpX", [SMX60_VIEU], mx, IsWorstCase>;472 defm "" : LMULWriteResMX<"WriteVICmpI", [SMX60_VIEU], mx, IsWorstCase>;473 }474 475 // Latency of vmacc, vmadd, vmul, vmulh, etc.: e8/e16 = 4/4/5/8, e32 = 5,5,5,8,476 // e64 = 7,8,16,32. We use the worst-case until we can split the SEW.477 // TODO: change WriteVIMulV, etc to be defined with LMULSEWSchedWrites478 defvar VIMulLat = ConstValueUntilLMULThenDoubleBase<"M2", 7, 8, mx>.c;479 // ReleaseAtCycles for vnmsac/vnmsub is 1/1/1/1/2/5 but we use the worse case480 // here since they are grouped together with vmacc/vmadd/vmul/vmulh.481 defvar VIMulOcc = ConstOneUntilM1ThenDouble<mx>.c;482 let Latency = VIMulLat, ReleaseAtCycles = [VIMulOcc] in {483 defm "" : LMULWriteResMX<"WriteVIMulV", [SMX60_VIEU], mx, IsWorstCase>;484 defm "" : LMULWriteResMX<"WriteVIMulX", [SMX60_VIEU], mx, IsWorstCase>;485 defm "" : LMULWriteResMX<"WriteVIMulAddV", [SMX60_VIEU], mx, IsWorstCase>;486 defm "" : LMULWriteResMX<"WriteVIMulAddX", [SMX60_VIEU], mx, IsWorstCase>;487 }488}489 490// Widening491// Pattern of vwmul, vwmacc, etc: e8/e16 = 4/4/5/8, e32 = 5,5,5,8492// We use the worst-case for all.493foreach mx = SchedMxListW in {494 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxListW>.c;495 496 defvar VIWideningOcc = ConstOneUntilMF2ThenDouble<mx>.c;497 let Latency = Get4588Latency<mx>.c, ReleaseAtCycles = [VIWideningOcc] in {498 defm "" : LMULWriteResMX<"WriteVIWALUV", [SMX60_VIEU], mx, IsWorstCase>;499 defm "" : LMULWriteResMX<"WriteVIWALUX", [SMX60_VIEU], mx, IsWorstCase>;500 defm "" : LMULWriteResMX<"WriteVIWALUI", [SMX60_VIEU], mx, IsWorstCase>;501 defm "" : LMULWriteResMX<"WriteVIWMulV", [SMX60_VIEU], mx, IsWorstCase>;502 defm "" : LMULWriteResMX<"WriteVIWMulX", [SMX60_VIEU], mx, IsWorstCase>;503 defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SMX60_VIEU], mx, IsWorstCase>;504 defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SMX60_VIEU], mx, IsWorstCase>;505 }506}507 508// Division and remainder operations509// Pattern of vdivu: 11/11/11/20/40/80/160510// Pattern of vdiv: 12/12/12/22/44/88/176511// Pattern of vremu: 12/12/12/22/44/88/176512// Pattern of vrem: 13/13/13/24/48/96/192513// We use for all: 12/12/12/24/48/96/192514// TODO: Create separate WriteVIRem to more closely match the latencies515foreach mx = SchedMxList in {516 foreach sew = SchedSEWSet<mx>.val in {517 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;518 519 // Not pipelined520 defvar VIDivLatAndOcc = ConstValueUntilLMULThenDouble<"MF2", 12, mx>.c;521 let Latency = VIDivLatAndOcc, ReleaseAtCycles = [VIDivLatAndOcc] in {522 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SMX60_VIEU], mx, sew, IsWorstCase>;523 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SMX60_VIEU], mx, sew, IsWorstCase>;524 }525 }526}527 528// Narrowing Shift and Clips529foreach mx = SchedMxListW in {530 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxListW>.c;531 532 defvar VNarrowingLat = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c;533 defvar VNarrowingOcc = ConstValueUntilLMULThenDouble<"MF4", 1, mx>.c;534 let Latency = VNarrowingLat, ReleaseAtCycles = [VNarrowingOcc] in {535 defm "" : LMULWriteResMX<"WriteVNShiftV", [SMX60_VIEU], mx, IsWorstCase>;536 defm "" : LMULWriteResMX<"WriteVNShiftX", [SMX60_VIEU], mx, IsWorstCase>;537 defm "" : LMULWriteResMX<"WriteVNShiftI", [SMX60_VIEU], mx, IsWorstCase>;538 defm "" : LMULWriteResMX<"WriteVNClipV", [SMX60_VIEU], mx, IsWorstCase>;539 defm "" : LMULWriteResMX<"WriteVNClipX", [SMX60_VIEU], mx, IsWorstCase>;540 defm "" : LMULWriteResMX<"WriteVNClipI", [SMX60_VIEU], mx, IsWorstCase>;541 }542}543 544// 12. Vector Fixed-Point Arithmetic Instructions545foreach mx = SchedMxList in {546 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;547 548 let Latency = Get4458Latency<mx>.c, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {549 defm "" : LMULWriteResMX<"WriteVSALUV", [SMX60_VIEU], mx, IsWorstCase>;550 defm "" : LMULWriteResMX<"WriteVSALUX", [SMX60_VIEU], mx, IsWorstCase>;551 defm "" : LMULWriteResMX<"WriteVSALUI", [SMX60_VIEU], mx, IsWorstCase>;552 defm "" : LMULWriteResMX<"WriteVAALUV", [SMX60_VIEU], mx, IsWorstCase>;553 defm "" : LMULWriteResMX<"WriteVAALUX", [SMX60_VIEU], mx, IsWorstCase>;554 }555 556 // Latency of vsmul: e8/e16 = 4/4/5/8, e32 = 5/5/5/8, e64 = 7/8/16/32557 // We use the worst-case until we can split the SEW.558 defvar VSMulLat = ConstValueUntilLMULThenDoubleBase<"M2", 7, 8, mx>.c;559 // Latency of vsmul: e8/e16/e32 = 1/2/4/8, e64 = 4/8/16/32560 // We use the worst-case until we can split the SEW.561 defvar VSMulOcc = ConstValueUntilLMULThenDoubleBase<"M1", 1, 4, mx>.c;562 // TODO: change WriteVSMulV/X to be defined with LMULSEWSchedWrites563 let Latency = VSMulLat, ReleaseAtCycles = [VSMulOcc] in {564 defm "" : LMULWriteResMX<"WriteVSMulV", [SMX60_VIEU], mx, IsWorstCase>;565 defm "" : LMULWriteResMX<"WriteVSMulX", [SMX60_VIEU], mx, IsWorstCase>;566 }567 568 defvar VSShiftLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;569 defvar VSShiftOcc = ConstOneUntilMF2ThenDouble<mx>.c;570 let Latency = VSShiftLat, ReleaseAtCycles = [VSShiftOcc] in {571 defm "" : LMULWriteResMX<"WriteVSShiftV", [SMX60_VIEU], mx, IsWorstCase>;572 defm "" : LMULWriteResMX<"WriteVSShiftX", [SMX60_VIEU], mx, IsWorstCase>;573 defm "" : LMULWriteResMX<"WriteVSShiftI", [SMX60_VIEU], mx, IsWorstCase>;574 }575}576 577// 13. Vector Floating-Point Instructions578foreach mx = SchedMxListF in {579 foreach sew = SchedSEWSet<mx, isF=1>.val in {580 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;581 582 defvar VFALULat = Get4458Latency<mx>.c;583 defvar VFALUOcc = ConstOneUntilM1ThenDouble<mx>.c;584 let Latency = VFALULat, ReleaseAtCycles = [VFALUOcc] in {585 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SMX60_VFP], mx, sew, IsWorstCase>;586 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SMX60_VFP], mx, sew, IsWorstCase>;587 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SMX60_VFP], mx, sew, IsWorstCase>;588 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SMX60_VFP], mx, sew, IsWorstCase>;589 }590 591 // Slightly increased latency for sew == 64592 defvar VFMulVLat = !if(!eq(sew, 64), ConstValueUntilLMULThenDoubleBase<"M8", 5, 8, mx>.c,593 Get4458Latency<mx>.c);594 let Latency = VFMulVLat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {595 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SMX60_VFP], mx, sew, IsWorstCase>;596 }597 // VFMulF has the same latency as VFMulV, but slighlty lower ReleaseAtCycles598 let Latency = VFMulVLat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {599 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SMX60_VFP], mx, sew, IsWorstCase>;600 }601 602 defvar VFSgnjLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;603 defvar VFSgnjOcc = ConstOneUntilMF2ThenDouble<mx>.c;604 let Latency = VFSgnjLat, ReleaseAtCycles = [VFSgnjOcc] in {605 defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SMX60_VFP], mx, sew, IsWorstCase>;606 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SMX60_VFP], mx, sew, IsWorstCase>;607 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SMX60_VFP], mx, sew, IsWorstCase>;608 defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SMX60_VFP], mx, sew, IsWorstCase>;609 }610 611 // The following covers vfmacc, vfmsac, and their vfn* variants in the same group, but the612 // ReleaseAtCycles takes one extra cycle for the vfn* variants.613 // TODO: Should we split them?614 // TODO: for some reason, the following cond is not working, and always use ConstValueUntilLMULThenDoubleBase<"M4", 5, 8, mx>.c615 defvar VFMulAddLatency = !if(!eq(sew, 64),616 Get6678Latency<mx>.c,617 ConstValueUntilLMULThenDoubleBase<"M8", 5, 8, mx>.c618 );619 let Latency = VFMulAddLatency, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {620 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SMX60_VFP], mx, sew, IsWorstCase>;621 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SMX60_VFP], mx, sew, IsWorstCase>;622 }623 }624}625 626foreach mx = SchedMxList in {627 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;628 629 // Slightly increased ReleaseAtCycles for M8: 18630 defvar VFCmpOcc = !if(!eq(mx, "M8"),631 !add(ConstOneUntilMF2ThenDouble<mx>.c, 2),632 ConstOneUntilMF2ThenDouble<mx>.c633 );634 let Latency = Get461018Latency<mx>.c, ReleaseAtCycles = [VFCmpOcc] in {635 defm "" : LMULWriteResMX<"WriteVFCmpV", [SMX60_VFP], mx, IsWorstCase>;636 defm "" : LMULWriteResMX<"WriteVFCmpF", [SMX60_VFP], mx, IsWorstCase>;637 }638 639 defvar VFClassLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;640 defvar VFClassOcc = ConstOneUntilMF2ThenDouble<mx>.c;641 let Latency = VFClassLat, ReleaseAtCycles = [VFClassOcc] in {642 defm "" : LMULWriteResMX<"WriteVFClassV", [SMX60_VFP], mx, IsWorstCase>;643 defm "" : LMULWriteResMX<"WriteVFMergeV", [SMX60_VFP], mx, IsWorstCase>;644 defm "" : LMULWriteResMX<"WriteVFMovV", [SMX60_VFP], mx, IsWorstCase>;645 defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SMX60_VFP], mx, IsWorstCase>;646 }647}648 649// Widening650foreach mx = SchedMxListW in {651 foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {652 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;653 654 defvar VFWCvtILat = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c;655 defvar VFWCvtIOcc = ConstOneUntilMF4ThenDouble<mx>.c;656 let Latency = VFWCvtILat, ReleaseAtCycles = [VFWCvtIOcc] in {657 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SMX60_VFP], mx, sew, IsWorstCase>;658 }659 }660}661 662foreach mx = SchedMxListFW in {663 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxListFW>.c;664 665 defvar VFWCvtFToIVLat = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c;666 defvar VFWCvtFToIVOcc = ConstOneUntilMF4ThenDouble<mx>.c;667 let Latency = VFWCvtFToIVLat, ReleaseAtCycles = [VFWCvtFToIVOcc] in {668 defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SMX60_VFP], mx, IsWorstCase>;669 }670}671 672foreach mx = SchedMxListFW in {673 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {674 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;675 676 defvar VFWCvtFToFVLat = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c;677 defvar VFWCvtFToFVOcc = ConstOneUntilMF4ThenDouble<mx>.c;678 let Latency = VFWCvtFToFVLat, ReleaseAtCycles = [VFWCvtFToFVOcc] in {679 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SMX60_VFP], mx, sew, IsWorstCase>;680 }681 682 // Latency for vfwsub/vfwadd.vv, vfwsub/vfwadd.vf: 4/4/4/5/8683 // ReleaseAtCycles for vfwsub/vfwadd.vv, vfwsub/vfwadd.vf: 1/1/2/4/8684 // Latency for vfwsub/vfwadd.wv, vfwsub/vfwadd.wf: 5/5/5/9/17685 // ReleaseAtCycles for vfwsub/vfwadd.wv, vfwsub/vfwadd.wf: 1/2/4/8/17686 // We use the worst-case687 defvar VFWALULat = !add(ConstValueUntilLMULThenDouble<"M1", 4, mx>.c, 1); // 5/5/9/17688 defvar VFWALUOcc = !if(!eq(mx, "M4"),689 !add(ConstOneUntilMF4ThenDouble<mx>.c, 1), // 2/4/8/17690 ConstOneUntilMF4ThenDouble<mx>.c691 );692 // TODO: Split .wf/.wv variants into separate scheduling classes693 let Latency = VFWALULat, ReleaseAtCycles = [VFWALUOcc] in {694 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SMX60_VFP], mx, sew, IsWorstCase>;695 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SMX60_VFP], mx, sew, IsWorstCase>;696 }697 698 let Latency = Get4588Latency<mx>.c, ReleaseAtCycles = [ConstOneUntilMF2ThenDouble<mx>.c] in {699 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SMX60_VFP], mx, sew, IsWorstCase>;700 }701 702 // Slightly increased latency for SEW == 32703 defvar VFWMullOcc = !if(!eq(sew, 32),704 GetLMULValue<[1, 1, 1, 3, 5, 9, 18], mx>.c,705 ConstOneUntilMF2ThenDouble<mx>.c706 );707 defvar VFWMulVLat = ConstValueUntilLMULThenDoubleBase<"M8", 5, 8, mx>.c;708 let Latency = VFWMulVLat, ReleaseAtCycles = [VFWMullOcc] in {709 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SMX60_VFP], mx, sew, IsWorstCase>;710 }711 712 // Latency for vfwmacc, vfwnmacc, etc: e16 = 5/5/5/8; e32 = 6/6/7/8713 defvar VFWMulAddVLat = !if(!eq(sew, 16),714 ConstValueUntilLMULThenDoubleBase<"M4", 5, 8, mx>.c,715 Get6678Latency<mx>.c716 );717 let Latency = VFWMulAddVLat, ReleaseAtCycles = [ConstOneUntilMF2ThenDouble<mx>.c] in {718 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SMX60_VFP], mx, sew, IsWorstCase>;719 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SMX60_VFP], mx, sew, IsWorstCase>;720 }721 }722}723 724// Narrowing725foreach mx = SchedMxListW in {726 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxListW>.c;727 728 defvar VFNCvtFToIVLat = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c;729 defvar VFNCvtFToIVOcc = ConstOneUntilMF4ThenDouble<mx>.c;730 let Latency = VFNCvtFToIVLat, ReleaseAtCycles = [VFNCvtFToIVOcc] in {731 defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SMX60_VFP], mx, IsWorstCase>;732 }733}734 735foreach mx = SchedMxListFW in {736 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {737 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;738 739 defvar VFNCvtToFVLat = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c;740 defvar VFNCvtToFVOcc = ConstOneUntilMF4ThenDouble<mx>.c;741 let Latency = VFNCvtToFVLat, ReleaseAtCycles = [VFNCvtToFVOcc] in {742 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SMX60_VFP], mx, sew, IsWorstCase>;743 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SMX60_VFP], mx, sew, IsWorstCase>;744 }745 }746}747 748// Vector Floating-Point Division and Square Root749foreach mx = SchedMxListF in {750 foreach sew = SchedSEWSet<mx, 1>.val in {751 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;752 753 // Compute ReleaseAtCycles based on SEW754 // Latency for vfdiv.vf: e16/e32 = 12/24/48/96; e64 = 18/36/72/144755 // Latency for vfrdiv.vf: e16/e32 = 12/24/48/96; e64 = 40/80/160/320756 // We use the worst-case, vfdiv.vf is penalized in e64757 // TODO: split vfdiv.vf and vfrdiv.vf into separate scheduling classes758 defvar VFDivFFactor = !if(!eq(sew, 64), 40, 12);759 defvar VFDivFLatAndOcc = !mul(ConstOneUntilM1ThenDouble<mx>.c, VFDivFFactor);760 let Latency = VFDivFLatAndOcc, ReleaseAtCycles = [VFDivFLatAndOcc] in {761 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SMX60_VFP], mx, sew, IsWorstCase>;762 }763 764 defvar VFDivVFactor = !if(!eq(sew, 16), 12, 40);765 defvar VFDivVLatAndOcc = !mul(ConstOneUntilM1ThenDouble<mx>.c, VFDivVFactor);766 let Latency = VFDivVLatAndOcc, ReleaseAtCycles = [VFDivVLatAndOcc] in {767 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SMX60_VFP], mx, sew, IsWorstCase>;768 }769 }770}771 772// Pattern for vfsqrt.v: e16 = 18/36/72/144; e32 = 38/76/152/304; e64 = 40/80/160/320773foreach mx = SchedMxListF in {774 foreach sew = SchedSEWSet<mx, 1>.val in {775 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;776 777 defvar VFSqrtVFactor = !if(!eq(sew, 16), 12, 40);778 defvar VFSqrtVLatAndOcc = !mul(ConstOneUntilM1ThenDouble<mx>.c, VFSqrtVFactor);779 let Latency = VFSqrtVLatAndOcc, ReleaseAtCycles = [VFSqrtVLatAndOcc] in {780 defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SMX60_VFP], mx, sew, IsWorstCase>;781 }782 }783}784 785// 14. Vector Reduction Operations786foreach mx = SchedMxList in {787 foreach sew = SchedSEWSet<mx>.val in {788 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;789 790 defvar VIRedLat = GetLMULValue<[5, 5, 5, 7, 11, 19, 35], mx>.c;791 defvar VIRedOcc = GetLMULValue<[1, 1, 2, 2, 4, 10, 35], mx>.c;792 let Latency = VIRedLat, ReleaseAtCycles = [VIRedOcc] in {793 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SMX60_VIEU], mx, sew, IsWorstCase>;794 795 // Pattern for vredsum: 5/5/5/7/11/19/35796 // Pattern for vredand, vredor, vredxor: 4/4/4/6/10/18/34797 // They are grouped together, so we use the worst-case vredsum latency.798 // TODO: split vredand, vredor, vredxor into separate scheduling classe.799 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SMX60_VIEU], mx, sew, IsWorstCase>;800 }801 }802}803 804foreach mx = SchedMxListWRed in {805 foreach sew = SchedSEWSet<mx, 0, 1>.val in {806 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;807 808 defvar VIRedLat = GetLMULValue<[5, 5, 5, 7, 11, 19, 35], mx>.c;809 defvar VIRedOcc = GetLMULValue<[1, 1, 2, 2, 4, 10, 35], mx>.c;810 let Latency = VIRedLat, ReleaseAtCycles = [VIRedOcc] in {811 defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SMX60_VIEU], mx, sew, IsWorstCase>;812 }813 }814}815 816foreach mx = SchedMxListF in {817 foreach sew = SchedSEWSet<mx, 1>.val in {818 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;819 820 // Latency for vfredmax.vs, vfredmin.vs: 12/12/15/21/33/57821 // Latency for vfredusum.vs is slightly lower for e16/e32822 // We use the worst-case823 defvar VFRedLat = GetLMULValue<[12, 12, 12, 15, 21, 33, 57], mx>.c;824 defvar VFRedOcc = GetLMULValue<[8, 8, 8, 8, 14, 20, 57], mx>.c;825 let Latency = VFRedLat, ReleaseAtCycles = [VFRedOcc] in {826 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SMX60_VFP], mx, sew, IsWorstCase>;827 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SMX60_VFP], mx, sew, IsWorstCase>;828 }829 }830}831 832foreach mx = SchedMxListF in {833 foreach sew = SchedSEWSet<mx, 1>.val in {834 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;835 836 // Compute latency based on SEW837 defvar VFRedOV_FromLat = !cond(838 !eq(sew, 16) : ConstValueUntilLMULThenDouble<"MF4", 12, mx>.c,839 !eq(sew, 32) : ConstValueUntilLMULThenDouble<"MF2", 12, mx>.c,840 !eq(sew, 64) : ConstValueUntilLMULThenDouble<"M1", 12, mx>.c841 );842 defvar VFRedOV_FromOcc = !cond(843 !eq(sew, 16) : GetLMULValue<[8, 8, 20, 24, 48, 96, 384], mx>.c,844 !eq(sew, 32) : GetLMULValue<[8, 8, 8, 12, 24, 48, 192], mx>.c,845 !eq(sew, 64) : GetLMULValue<[6, 6, 6, 6, 12, 24, 96], mx>.c846 );847 let Latency = VFRedOV_FromLat, ReleaseAtCycles = [VFRedOV_FromOcc] in {848 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SMX60_VFP], mx, sew, IsWorstCase>;849 }850 }851}852 853foreach mx = SchedMxListFWRed in {854 foreach sew = SchedSEWSet<mx, 1, 1>.val in {855 defvar IsWorstCase = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;856 857 defvar VFRedOVLat = !cond(858 !eq(sew, 16) : ConstValueUntilLMULThenDouble<"MF4", 16, mx>.c,859 !eq(sew, 32) : ConstValueUntilLMULThenDouble<"MF2", 16, mx>.c,860 );861 defvar VFRedOVOcc = !cond(862 !eq(sew, 16) : GetLMULValue<[11, 11, 27, 32, 64, 128, 512], mx>.c,863 !eq(sew, 32) : GetLMULValue<[11, 11, 11, 16, 32, 64, 256], mx>.c,864 );865 let Latency = VFRedOVLat, ReleaseAtCycles = [VFRedOVOcc] in {866 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SMX60_VFP], mx, sew, IsWorstCase>;867 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SMX60_VFP], mx, sew, IsWorstCase>;868 }869 }870}871 872// 15. Vector Mask Instructions873foreach mx = SchedMxList in {874 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;875 876 let Latency = 4 in {877 defm "" : LMULWriteResMX<"WriteVMALUV", [SMX60_VIEU], mx, IsWorstCase>;878 }879 let Latency = 4, ReleaseAtCycles = [ConstValueUntilLMULThenDouble<"M2", 1, mx>.c] in {880 defm "" : LMULWriteResMX<"WriteVMSFSV", [SMX60_VIEU], mx, IsWorstCase>;881 }882 883 let Latency = 6, ReleaseAtCycles = [2] in {884 defm "" : LMULWriteResMX<"WriteVMPopV", [SMX60_VIEU], mx, IsWorstCase>;885 defm "" : LMULWriteResMX<"WriteVMFFSV", [SMX60_VIEU], mx, IsWorstCase>;886 }887 888 defvar VIotaLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;889 defvar VIotaOcc = ConstOneUntilMF2ThenDouble<mx>.c;890 let Latency = VIotaLat, ReleaseAtCycles = [VIotaOcc] in {891 defm "" : LMULWriteResMX<"WriteVIotaV", [SMX60_VIEU], mx, IsWorstCase>;892 defm "" : LMULWriteResMX<"WriteVIdxV", [SMX60_VIEU], mx, IsWorstCase>;893 }894}895 896// 16. Vector Permutation Instructions897// Slide898foreach mx = SchedMxList in {899 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;900 901 // Latency for slide up: 4/4/8/16, ReleaseAtCycles is 2/4/8/16902 defvar VSlideUpLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;903 defvar VSlideUpOcc = ConstOneUntilMF2ThenDouble<mx>.c;904 let Latency = VSlideUpLat, ReleaseAtCycles =[VSlideUpOcc] in {905 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SMX60_VIEU], mx, IsWorstCase>;906 }907 908 // Latency for slide down: 4/5/9/17, ReleaseAtCycles is 3/5/9/17909 defvar VSlideDownLat = GetLMULValue<[4, 4, 4, 4, 5, 9, 17], mx>.c;910 defvar VSlideDownOcc = GetLMULValue<[1, 1, 1, 3, 5, 9, 17], mx>.c;911 let Latency = VSlideDownLat, ReleaseAtCycles =[VSlideDownOcc] in {912 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SMX60_VIEU], mx, IsWorstCase>;913 }914 // The following group slide up and down together, so we use the worst-case915 // (slide down) for all.916 let Latency = VSlideDownLat, ReleaseAtCycles =[VSlideDownOcc] in {917 defm "" : LMULWriteResMX<"WriteVSlideI", [SMX60_VIEU], mx, IsWorstCase>;918 defm "" : LMULWriteResMX<"WriteVISlide1X", [SMX60_VIEU], mx, IsWorstCase>;919 920 defm "" : LMULWriteResMX<"WriteVFSlide1F", [SMX60_VFP], mx, IsWorstCase>;921 }922}923 924// ReleaseAtCycles is 2/2/2/2/2/3/6, but we can't set based on MX for now925// TODO: Split this into separate WriteRes for each MX926let Latency = 6, ReleaseAtCycles = [6] in {927 def : WriteRes<WriteVMovXS, [SMX60_VIEU]>;928}929 930// ReleaseAtCycles is 1/1/1/1/1/2/4, but we can't set based on MX for now931// TODO: Split this into separate WriteRes for each MX932let Latency = 4, ReleaseAtCycles = [4] in {933 def : WriteRes<WriteVMovSX, [SMX60_VIEU]>;934 def : WriteRes<WriteVMovFS, [SMX60_VIEU]>;935 def : WriteRes<WriteVMovSF, [SMX60_VIEU]>;936}937 938// Integer LMUL Gather and Compress939foreach mx = SchedMxList in {940 defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;941 942 defvar VRGatherLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;943 let Latency = VRGatherLat, ReleaseAtCycles = [ConstOneUntilMF2ThenDouble<mx>.c] in {944 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SMX60_VIEU], mx, IsWorstCase>;945 defm "" : LMULWriteResMX<"WriteVRGatherVI", [SMX60_VIEU], mx, IsWorstCase>;946 }947 948 foreach sew = SchedSEWSet<mx>.val in {949 defvar IsWorstCaseSEW = SMX60IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;950 951 defvar VRGatherVVLat = GetLMULValue<[4, 4, 4, 4, 16, 64, 256], mx>.c;952 defvar VRGatherVVOcc = GetLMULValue<[1, 1, 1, 4, 16, 64, 256], mx>.c;953 let Latency = VRGatherVVLat, ReleaseAtCycles = [VRGatherVVOcc] in {954 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SMX60_VIEU], mx, sew, IsWorstCaseSEW>;955 }956 // For sew == 8, latency is half of the other cases, except for the fractional LMULs (const 4 cycles)957 defvar VRGatherEI16Lat = !if(!eq(sew, 8),958 GetLMULValue<[4, 4, 4, 8, 32, 128, 256], mx>.c,959 GetLMULValue<[4, 4, 4, 4, 16, 64, 256], mx>.c);960 defvar VRGatherEI16Occ = !if(!eq(sew, 8),961 GetLMULValue<[1, 1, 2, 8, 32, 128, 256], mx>.c,962 GetLMULValue<[1, 1, 1, 4, 16, 64, 256], mx>.c);963 let Latency = VRGatherEI16Lat, ReleaseAtCycles = [VRGatherEI16Occ] in {964 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SMX60_VIEU], mx, sew, IsWorstCaseSEW>;965 }966 967 defvar VCompressVLat = GetLMULValue<[4, 4, 4, 4, 10, 36, 136], mx>.c;968 defvar VCompressVOcc = GetLMULValue<[1, 1, 1, 3, 10, 36, 136], mx>.c;969 let Latency = VCompressVLat, ReleaseAtCycles = [VCompressVOcc] in {970 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SMX60_VIEU], mx, sew, IsWorstCaseSEW>;971 }972 }973}974 975// Others976def : WriteRes<WriteCSR, [SMX60_IEU]>;977def : WriteRes<WriteNop, [SMX60_IEU]>;978def : WriteRes<WriteRdVLENB, [SMX60_IEUA]>;979 980// Give COPY instructions an execution resource.981// FIXME: This could be better modeled by looking at the regclasses of the operands.982def : InstRW<[WriteIALU], (instrs COPY)>;983 984//===----------------------------------------------------------------------===//985// Bypass and advance986def : ReadAdvance<ReadJmp, 0>;987def : ReadAdvance<ReadJalr, 0>;988def : ReadAdvance<ReadCSR, 0>;989def : ReadAdvance<ReadStoreData, 0>;990def : ReadAdvance<ReadMemBase, 0>;991def : ReadAdvance<ReadIALU, 0>;992def : ReadAdvance<ReadIALU32, 0>;993def : ReadAdvance<ReadShiftImm, 0>;994def : ReadAdvance<ReadShiftImm32, 0>;995def : ReadAdvance<ReadShiftReg, 0>;996def : ReadAdvance<ReadShiftReg32, 0>;997def : ReadAdvance<ReadIDiv, 0>;998def : ReadAdvance<ReadIDiv32, 0>;999def : ReadAdvance<ReadIRem, 0>;1000def : ReadAdvance<ReadIRem32, 0>;1001def : ReadAdvance<ReadIMul, 0>;1002def : ReadAdvance<ReadIMul32, 0>;1003def : ReadAdvance<ReadAtomicWA, 0>;1004def : ReadAdvance<ReadAtomicWD, 0>;1005def : ReadAdvance<ReadAtomicDA, 0>;1006def : ReadAdvance<ReadAtomicDD, 0>;1007def : ReadAdvance<ReadAtomicLDW, 0>;1008def : ReadAdvance<ReadAtomicLDD, 0>;1009def : ReadAdvance<ReadAtomicSTW, 0>;1010def : ReadAdvance<ReadAtomicSTD, 0>;1011def : ReadAdvance<ReadFStoreData, 0>;1012def : ReadAdvance<ReadFMemBase, 0>;1013def : ReadAdvance<ReadFAdd16, 0>;1014def : ReadAdvance<ReadFAdd32, 0>;1015def : ReadAdvance<ReadFAdd64, 0>;1016def : ReadAdvance<ReadFMul16, 0>;1017def : ReadAdvance<ReadFMA16, 0>;1018def : ReadAdvance<ReadFMA16Addend, 0>;1019def : ReadAdvance<ReadFMul32, 0>;1020def : ReadAdvance<ReadFMul64, 0>;1021def : ReadAdvance<ReadFMA32, 0>;1022def : ReadAdvance<ReadFMA32Addend, 0>;1023def : ReadAdvance<ReadFMA64, 0>;1024def : ReadAdvance<ReadFMA64Addend, 0>;1025def : ReadAdvance<ReadFDiv16, 0>;1026def : ReadAdvance<ReadFDiv32, 0>;1027def : ReadAdvance<ReadFDiv64, 0>;1028def : ReadAdvance<ReadFSqrt16, 0>;1029def : ReadAdvance<ReadFSqrt32, 0>;1030def : ReadAdvance<ReadFSqrt64, 0>;1031def : ReadAdvance<ReadFCmp16, 0>;1032def : ReadAdvance<ReadFCmp32, 0>;1033def : ReadAdvance<ReadFCmp64, 0>;1034def : ReadAdvance<ReadFSGNJ16, 0>;1035def : ReadAdvance<ReadFSGNJ32, 0>;1036def : ReadAdvance<ReadFSGNJ64, 0>;1037def : ReadAdvance<ReadFMinMax16, 0>;1038def : ReadAdvance<ReadFMinMax32, 0>;1039def : ReadAdvance<ReadFMinMax64, 0>;1040def : ReadAdvance<ReadFCvtF16ToI32, 0>;1041def : ReadAdvance<ReadFCvtF16ToI64, 0>;1042def : ReadAdvance<ReadFCvtF32ToI32, 0>;1043def : ReadAdvance<ReadFCvtF32ToI64, 0>;1044def : ReadAdvance<ReadFCvtF64ToI32, 0>;1045def : ReadAdvance<ReadFCvtF64ToI64, 0>;1046def : ReadAdvance<ReadFCvtI32ToF16, 0>;1047def : ReadAdvance<ReadFCvtI32ToF32, 0>;1048def : ReadAdvance<ReadFCvtI32ToF64, 0>;1049def : ReadAdvance<ReadFCvtI64ToF16, 0>;1050def : ReadAdvance<ReadFCvtI64ToF32, 0>;1051def : ReadAdvance<ReadFCvtI64ToF64, 0>;1052def : ReadAdvance<ReadFCvtF32ToF64, 0>;1053def : ReadAdvance<ReadFCvtF64ToF32, 0>;1054def : ReadAdvance<ReadFCvtF16ToF32, 0>;1055def : ReadAdvance<ReadFCvtF32ToF16, 0>;1056def : ReadAdvance<ReadFCvtF16ToF64, 0>;1057def : ReadAdvance<ReadFCvtF64ToF16, 0>;1058def : ReadAdvance<ReadFMovF16ToI16, 0>;1059def : ReadAdvance<ReadFMovI16ToF16, 0>;1060def : ReadAdvance<ReadFMovF32ToI32, 0>;1061def : ReadAdvance<ReadFMovI32ToF32, 0>;1062def : ReadAdvance<ReadFMovF64ToI64, 0>;1063def : ReadAdvance<ReadFMovI64ToF64, 0>;1064def : ReadAdvance<ReadFClass16, 0>;1065def : ReadAdvance<ReadFClass32, 0>;1066def : ReadAdvance<ReadFClass64, 0>;1067 1068// Bitmanip1069def : ReadAdvance<ReadRotateImm, 0>;1070def : ReadAdvance<ReadRotateImm32, 0>;1071def : ReadAdvance<ReadRotateReg, 0>;1072def : ReadAdvance<ReadRotateReg32, 0>;1073def : ReadAdvance<ReadCLZ, 0>;1074def : ReadAdvance<ReadCLZ32, 0>;1075def : ReadAdvance<ReadCTZ, 0>;1076def : ReadAdvance<ReadCTZ32, 0>;1077def : ReadAdvance<ReadCPOP, 0>;1078def : ReadAdvance<ReadCPOP32, 0>;1079def : ReadAdvance<ReadORCB, 0>;1080def : ReadAdvance<ReadIMinMax, 0>;1081def : ReadAdvance<ReadREV8, 0>;1082def : ReadAdvance<ReadSHXADD, 0>;1083def : ReadAdvance<ReadSHXADD32, 0>;1084def : ReadAdvance<ReadCLMUL, 0>;1085// Single-bit instructions1086def : ReadAdvance<ReadSingleBit, 0>;1087def : ReadAdvance<ReadSingleBitImm, 0>;1088 1089// 6. Configuration-Setting Instructions1090def : ReadAdvance<ReadVSETVLI, 0>;1091def : ReadAdvance<ReadVSETVL, 0>;1092 1093// 7. Vector Loads and Stores1094def : ReadAdvance<ReadVLDX, 0>;1095def : ReadAdvance<ReadVSTX, 0>;1096defm "" : LMULReadAdvance<"ReadVSTEV", 0>;1097defm "" : LMULReadAdvance<"ReadVSTM", 0>;1098def : ReadAdvance<ReadVLDSX, 0>;1099def : ReadAdvance<ReadVSTSX, 0>;1100defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;1101defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;1102defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;1103defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;1104defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;1105defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;1106defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;1107defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;1108defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;1109defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;1110defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;1111defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;1112defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;1113defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;1114defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;1115defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;1116defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;1117defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;1118defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;1119defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;1120defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;1121defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;1122defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;1123defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;1124// LMUL Aware1125def : ReadAdvance<ReadVST1R, 0>;1126def : ReadAdvance<ReadVST2R, 0>;1127def : ReadAdvance<ReadVST4R, 0>;1128def : ReadAdvance<ReadVST8R, 0>;1129 1130// 12. Vector Integer Arithmetic Instructions1131defm : LMULReadAdvance<"ReadVIALUV", 0>;1132defm : LMULReadAdvance<"ReadVIALUX", 0>;1133defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;1134defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;1135defm : LMULReadAdvance<"ReadVExtV", 0>;1136defm : LMULReadAdvance<"ReadVICALUV", 0>;1137defm : LMULReadAdvance<"ReadVICALUX", 0>;1138defm : LMULReadAdvance<"ReadVShiftV", 0>;1139defm : LMULReadAdvance<"ReadVShiftX", 0>;1140defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;1141defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;1142defm : LMULReadAdvance<"ReadVICmpV", 0>;1143defm : LMULReadAdvance<"ReadVICmpX", 0>;1144defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;1145defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;1146defm : LMULReadAdvance<"ReadVIMulV", 0>;1147defm : LMULReadAdvance<"ReadVIMulX", 0>;1148defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;1149defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;1150defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;1151defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;1152defm : LMULReadAdvance<"ReadVIMulAddV", 0>;1153defm : LMULReadAdvance<"ReadVIMulAddX", 0>;1154defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;1155defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;1156defm : LMULReadAdvance<"ReadVIMergeV", 0>;1157defm : LMULReadAdvance<"ReadVIMergeX", 0>;1158defm : LMULReadAdvance<"ReadVIMovV", 0>;1159defm : LMULReadAdvance<"ReadVIMovX", 0>;1160 1161// 13. Vector Fixed-Point Arithmetic Instructions1162defm "" : LMULReadAdvance<"ReadVSALUV", 0>;1163defm "" : LMULReadAdvance<"ReadVSALUX", 0>;1164defm "" : LMULReadAdvance<"ReadVAALUV", 0>;1165defm "" : LMULReadAdvance<"ReadVAALUX", 0>;1166defm "" : LMULReadAdvance<"ReadVSMulV", 0>;1167defm "" : LMULReadAdvance<"ReadVSMulX", 0>;1168defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;1169defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;1170defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;1171defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;1172 1173// 14. Vector Floating-Point Instructions1174defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;1175defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;1176defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;1177defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;1178defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;1179defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;1180defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;1181defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;1182defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;1183defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;1184defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;1185defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;1186defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;1187defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;1188defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;1189defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;1190defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;1191defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;1192defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;1193defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;1194defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;1195defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;1196defm "" : LMULReadAdvance<"ReadVFClassV", 0>;1197defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;1198defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;1199defm "" : LMULReadAdvance<"ReadVFMovF", 0>;1200defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;1201defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;1202defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;1203defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;1204defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;1205defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;1206defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;1207defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;1208 1209// 15. Vector Reduction Operations1210def : ReadAdvance<ReadVIRedV, 0>;1211def : ReadAdvance<ReadVIRedV0, 0>;1212def : ReadAdvance<ReadVIWRedV, 0>;1213def : ReadAdvance<ReadVIWRedV0, 0>;1214def : ReadAdvance<ReadVFRedV, 0>;1215def : ReadAdvance<ReadVFRedV0, 0>;1216def : ReadAdvance<ReadVFRedOV, 0>;1217def : ReadAdvance<ReadVFRedOV0, 0>;1218def : ReadAdvance<ReadVFWRedV, 0>;1219def : ReadAdvance<ReadVFWRedV0, 0>;1220def : ReadAdvance<ReadVFWRedOV, 0>;1221def : ReadAdvance<ReadVFWRedOV0, 0>;1222 1223// 16. Vector Mask Instructions1224defm "" : LMULReadAdvance<"ReadVMALUV", 0>;1225defm "" : LMULReadAdvance<"ReadVMPopV", 0>;1226defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;1227defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;1228defm "" : LMULReadAdvance<"ReadVIotaV", 0>;1229 1230// 17. Vector Permutation Instructions1231def : ReadAdvance<ReadVMovXS, 0>;1232def : ReadAdvance<ReadVMovSX_V, 0>;1233def : ReadAdvance<ReadVMovSX_X, 0>;1234def : ReadAdvance<ReadVMovFS, 0>;1235def : ReadAdvance<ReadVMovSF_V, 0>;1236def : ReadAdvance<ReadVMovSF_F, 0>;1237defm "" : LMULReadAdvance<"ReadVISlideV", 0>;1238defm "" : LMULReadAdvance<"ReadVISlideX", 0>;1239defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;1240defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;1241defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;1242defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;1243defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;1244defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;1245defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;1246defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;1247defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;1248defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;1249// LMUL Aware1250def : ReadAdvance<ReadVMov1V, 0>;1251def : ReadAdvance<ReadVMov2V, 0>;1252def : ReadAdvance<ReadVMov4V, 0>;1253def : ReadAdvance<ReadVMov8V, 0>;1254 1255// Others1256def : ReadAdvance<ReadVMask, 0>;1257def : ReadAdvance<ReadVPassthru_WorstCase, 0>;1258foreach mx = SchedMxList in {1259 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;1260 foreach sew = SchedSEWSet<mx>.val in1261 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;1262}1263 1264//===----------------------------------------------------------------------===//1265// Unsupported extensions1266defm : UnsupportedSchedQ;1267defm : UnsupportedSchedZabha;1268defm : UnsupportedSchedZbkb;1269defm : UnsupportedSchedZbkx;1270defm : UnsupportedSchedZfa;1271defm : UnsupportedSchedZvk;1272defm : UnsupportedSchedSFB;1273defm : UnsupportedSchedXsf;1274}1275