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1//=- RISCVSchedTTAscalonD8.td - TT Ascalon D8 Sched Defs -----*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10 11class AscalonIsWorstCaseMX<string mx, list<string> MxList> {12 defvar LLMUL = LargestLMUL<MxList>.r;13 bit c = !eq(mx, LLMUL);14}15 16class AscalonIsWorstCaseMXSEW<string mx, int sew, list<string> MxList,17 bit isF = 0> {18 defvar LLMUL = LargestLMUL<MxList>.r;19 defvar SSEW = SmallestSEW<mx, isF>.r;20 bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));21}22 23/// Cycle counts that scale with LMUL with LMUL=1 having the same latency as24/// fractional LMULs25class AscalonGetCyclesLMUL<string mx, int base> {26 int c = !cond(27 !eq(mx, "M1") : base,28 !eq(mx, "M2") : !mul(base, 2),29 !eq(mx, "M4") : !mul(base, 4),30 !eq(mx, "M8") : !mul(base, 8),31 !eq(mx, "MF2") : base,32 !eq(mx, "MF4") : base,33 !eq(mx, "MF8") : base34 );35}36 37/// Linear LMUL scaling starting from smallest fractional LMUL38class AscalonGetCyclesLMULFractional<string mx, int base> {39 int c = !cond(40 !eq(mx, "MF8") : base,41 !eq(mx, "MF4") : !mul(base, 2),42 !eq(mx, "MF2") : !mul(base, 4),43 !eq(mx, "M1") : !mul(base, 8),44 !eq(mx, "M2") : !mul(base, 16),45 !eq(mx, "M4") : !mul(base, 32),46 !eq(mx, "M8") : !mul(base, 64)47 );48}49 50class AscalonGetCyclesDefault<string mx> {51 int c = AscalonGetCyclesLMUL<mx, 1>.c;52}53 54class AscalonGetCyclesNarrowing<string mx> {55 int c = !cond(56 !eq(mx, "M1") : 4,57 !eq(mx, "M2") : 8,58 !eq(mx, "M4") : 16,59 !eq(mx, "MF2") : 2,60 !eq(mx, "MF4") : 1,61 !eq(mx, "MF8") : 162 );63}64 65 66class AscalonGetCyclesDivOrSqrt<string mx, int sew> {67 int c = !cond(68 !eq(sew, 8) : AscalonGetCyclesLMUL<mx, 7>.c,69 !eq(sew, 16) : AscalonGetCyclesLMUL<mx, 6>.c,70 !eq(sew, 32) : AscalonGetCyclesLMUL<mx, 5>.c,71 !eq(sew, 64) : AscalonGetCyclesLMUL<mx, 8>.c72 );73}74 75class AscalonGetCyclesVRGatherVV<string mx> {76 int c = !cond(77 !eq(mx, "M1") : 2,78 !eq(mx, "M2") : 4,79 !eq(mx, "M4") : 12,80 !eq(mx, "M8") : 48,81 !eq(mx, "MF2") : 2,82 !eq(mx, "MF4") : 2,83 !eq(mx, "MF8") : 284 );85}86 87class AscalonGetCyclesStridedSegmented<string mx, int sew> {88 int c = !cond(89 !eq(sew, 8) : AscalonGetCyclesLMULFractional<mx, 4>.c,90 !eq(sew, 16) : AscalonGetCyclesLMULFractional<mx, 2>.c,91 !eq(sew, 32) : AscalonGetCyclesLMULFractional<mx, 1>.c,92 !eq(sew, 64) : AscalonGetCyclesLMULFractional<mx, 1>.c93 );94}95 96//===----------------------------------------------------------------------===//97 98def TTAscalonD8Model : SchedMachineModel {99 let IssueWidth = 8; // 8-way decode and dispatch100 let MicroOpBufferSize = 256; // 256 micro-op re-order buffer101 let LoadLatency = 4; // Optimistic load latency102 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch103 104 let CompleteModel = false;105 106 // TODO: supported, but haven't added scheduling info yet.107 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,108 HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,109 HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,110 HasStdExtZkr];111}112 113let SchedModel = TTAscalonD8Model in {114 115//===----------------------------------------------------------------------===//116// Define each kind of processor resource and number available.117 118let BufferSize = 16 in {119 def AscalonLS : ProcResource<3>;120 def AscalonFXA : ProcResource<1>; // ALU, FP/VEC -> INT, MUL, DIV, CSR121 def AscalonFXB : ProcResource<1>; // ALU, INT -> FP/VEC122 def AscalonFXC : ProcResource<2>; // ALU, BR123 def AscalonFXD : ProcResource<2>; // ALU124 def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXD]>;125 // FP126 def AscalonFPA : ProcResource<1>; // Pipe A also handles FP/VEC -> INT127 def AscalonFPB : ProcResource<1>;128 def AscalonFP : ProcResGroup<[AscalonFPA, AscalonFPB]>;129 // Vector130 def AscalonVA : ProcResource<1>;131 def AscalonVB : ProcResource<1>;132 def AscalonV : ProcResGroup<[AscalonVA, AscalonVB]>;133}134 135 136//===----------------------------------------------------------------------===//137 138// Branching139def : WriteRes<WriteJmp, [AscalonFXC]>;140def : WriteRes<WriteJal, [AscalonFXC]>;141def : WriteRes<WriteJalr, [AscalonFXC]>;142 143// Integer arithmetic and logic144def : WriteRes<WriteIALU32, [AscalonFX]>;145def : WriteRes<WriteIALU, [AscalonFX]>;146def : WriteRes<WriteShiftImm32, [AscalonFX]>;147def : WriteRes<WriteShiftImm, [AscalonFX]>;148def : WriteRes<WriteShiftReg32, [AscalonFX]>;149def : WriteRes<WriteShiftReg, [AscalonFX]>;150 151// Integer multiplication152let Latency = 3 in {153def : WriteRes<WriteIMul, [AscalonFXA]>;154def : WriteRes<WriteIMul32, [AscalonFXA]>;155}156 157// Integer division158// Worst case latency is used.159 160let Latency = 7, ReleaseAtCycles = [7] in {161 def : WriteRes<WriteIDiv32, [AscalonFXA]>;162 def : WriteRes<WriteIDiv, [AscalonFXA]>;163 def : WriteRes<WriteIRem32, [AscalonFXA]>;164 def : WriteRes<WriteIRem, [AscalonFXA]>;165}166 167// Bitmanip168def : WriteRes<WriteRotateImm, [AscalonFX]>;169def : WriteRes<WriteRotateImm32, [AscalonFX]>;170def : WriteRes<WriteRotateReg, [AscalonFX]>;171def : WriteRes<WriteRotateReg32, [AscalonFX]>;172 173def : WriteRes<WriteCLZ, [AscalonFX]>;174def : WriteRes<WriteCLZ32, [AscalonFX]>;175def : WriteRes<WriteCTZ, [AscalonFX]>;176def : WriteRes<WriteCTZ32, [AscalonFX]>;177 178def : WriteRes<WriteCPOP, [AscalonFX]>;179def : WriteRes<WriteCPOP32, [AscalonFX]>;180 181def : WriteRes<WriteORCB, [AscalonFX]>;182 183def : WriteRes<WriteIMinMax, [AscalonFX]>;184 185def : WriteRes<WriteREV8, [AscalonFX]>;186 187def : WriteRes<WriteSHXADD, [AscalonFX]>;188def : WriteRes<WriteSHXADD32, [AscalonFX]>;189 190// Single-bit instructions191def : WriteRes<WriteSingleBit, [AscalonFX]>;192def : WriteRes<WriteSingleBitImm, [AscalonFX]>;193def : WriteRes<WriteBEXT, [AscalonFX]>;194def : WriteRes<WriteBEXTI, [AscalonFX]>;195 196// Memory197def : WriteRes<WriteSTB, [AscalonLS]>;198def : WriteRes<WriteSTH, [AscalonLS]>;199def : WriteRes<WriteSTW, [AscalonLS]>;200def : WriteRes<WriteSTD, [AscalonLS]>;201def : WriteRes<WriteFST16, [AscalonLS]>;202def : WriteRes<WriteFST32, [AscalonLS]>;203def : WriteRes<WriteFST64, [AscalonLS]>;204 205let Latency = 4 in {206def : WriteRes<WriteLDB, [AscalonLS]>;207def : WriteRes<WriteLDH, [AscalonLS]>;208def : WriteRes<WriteLDW, [AscalonLS]>;209def : WriteRes<WriteLDD, [AscalonLS]>;210def : WriteRes<WriteFLD16, [AscalonLS]>;211def : WriteRes<WriteFLD32, [AscalonLS]>;212def : WriteRes<WriteFLD64, [AscalonLS]>;213}214 215// Atomic memory216def : WriteRes<WriteAtomicSTW, [AscalonLS]>;217def : WriteRes<WriteAtomicSTD, [AscalonLS]>;218 219let Latency = 4 in {220def : WriteRes<WriteAtomicW, [AscalonLS]>;221def : WriteRes<WriteAtomicD, [AscalonLS]>;222def : WriteRes<WriteAtomicLDW, [AscalonLS]>;223def : WriteRes<WriteAtomicLDD, [AscalonLS]>;224}225 226// Half precision.227let Latency = 3 in {228def : WriteRes<WriteFAdd16, [AscalonFP]>;229def : WriteRes<WriteFMul16, [AscalonFP]>;230def : WriteRes<WriteFMA16, [AscalonFP]>;231def : WriteRes<WriteFSGNJ16, [AscalonFP]>;232def : WriteRes<WriteFMinMax16, [AscalonFP]>;233}234 235let Latency = 7, ReleaseAtCycles = [7] in {236def : WriteRes<WriteFDiv16, [AscalonFP]>;237def : WriteRes<WriteFSqrt16, [AscalonFP]>;238}239 240// Single precision.241let Latency = 3 in {242def : WriteRes<WriteFAdd32, [AscalonFP]>;243def : WriteRes<WriteFMul32, [AscalonFP]>;244def : WriteRes<WriteFMA32, [AscalonFP]>;245def : WriteRes<WriteFSGNJ32, [AscalonFP]>;246def : WriteRes<WriteFMinMax32, [AscalonFP]>;247}248 249let Latency = 7, ReleaseAtCycles = [7] in {250def : WriteRes<WriteFDiv32, [AscalonFP]>;251def : WriteRes<WriteFSqrt32, [AscalonFP]>;252}253 254// Double precision255let Latency = 3 in {256def : WriteRes<WriteFAdd64, [AscalonFP]>;257def : WriteRes<WriteFMul64, [AscalonFP]>;258def : WriteRes<WriteFMA64, [AscalonFP]>;259def : WriteRes<WriteFSGNJ64, [AscalonFP]>;260def : WriteRes<WriteFMinMax64, [AscalonFP]>;261}262 263let Latency = 12, ReleaseAtCycles = [12] in {264def : WriteRes<WriteFDiv64, [AscalonFP]>;265def : WriteRes<WriteFSqrt64, [AscalonFP]>;266}267 268// Conversions269def : WriteRes<WriteFCvtI32ToF16, [AscalonFXB]>;270def : WriteRes<WriteFCvtI32ToF32, [AscalonFXB]>;271def : WriteRes<WriteFCvtI32ToF64, [AscalonFXB]>;272def : WriteRes<WriteFCvtI64ToF16, [AscalonFXB]>;273def : WriteRes<WriteFCvtI64ToF32, [AscalonFXB]>;274def : WriteRes<WriteFCvtI64ToF64, [AscalonFXB]>;275def : WriteRes<WriteFCvtF16ToI32, [AscalonFXA]>;276def : WriteRes<WriteFCvtF16ToI64, [AscalonFXA]>;277def : WriteRes<WriteFCvtF16ToF32, [AscalonFP]>;278def : WriteRes<WriteFCvtF16ToF64, [AscalonFP]>;279def : WriteRes<WriteFCvtF32ToI32, [AscalonFXA]>;280def : WriteRes<WriteFCvtF32ToI64, [AscalonFXA]>;281def : WriteRes<WriteFCvtF32ToF16, [AscalonFP]>;282def : WriteRes<WriteFCvtF32ToF64, [AscalonFP]>;283def : WriteRes<WriteFCvtF64ToI32, [AscalonFXA]>;284def : WriteRes<WriteFCvtF64ToI64, [AscalonFXA]>;285def : WriteRes<WriteFCvtF64ToF16, [AscalonFP]>;286def : WriteRes<WriteFCvtF64ToF32, [AscalonFP]>;287 288def : WriteRes<WriteFClass16, [AscalonFP]>;289def : WriteRes<WriteFClass32, [AscalonFP]>;290def : WriteRes<WriteFClass64, [AscalonFP]>;291def : WriteRes<WriteFCmp16, [AscalonFP]>;292def : WriteRes<WriteFCmp32, [AscalonFP]>;293def : WriteRes<WriteFCmp64, [AscalonFP]>;294 295def : WriteRes<WriteFMovI16ToF16, [AscalonFXB]>;296def : WriteRes<WriteFMovF16ToI16, [AscalonFXA]>;297def : WriteRes<WriteFMovI32ToF32, [AscalonFXB]>;298def : WriteRes<WriteFMovF32ToI32, [AscalonFXA]>;299def : WriteRes<WriteFMovI64ToF64, [AscalonFXB]>;300def : WriteRes<WriteFMovF64ToI64, [AscalonFXA]>;301 302// Others303def : WriteRes<WriteCSR, [AscalonFXA]>;304def : WriteRes<WriteNop, [AscalonFX]>;305 306def : InstRW<[WriteIALU], (instrs COPY)>;307 308//===----------------------------------------------------------------------===//309// Bypass and advance310def : ReadAdvance<ReadJmp, 0>;311def : ReadAdvance<ReadJalr, 0>;312def : ReadAdvance<ReadCSR, 0>;313def : ReadAdvance<ReadStoreData, 0>;314def : ReadAdvance<ReadMemBase, 0>;315def : ReadAdvance<ReadIALU, 0>;316def : ReadAdvance<ReadIALU32, 0>;317def : ReadAdvance<ReadShiftImm, 0>;318def : ReadAdvance<ReadShiftImm32, 0>;319def : ReadAdvance<ReadShiftReg, 0>;320def : ReadAdvance<ReadShiftReg32, 0>;321def : ReadAdvance<ReadIDiv, 0>;322def : ReadAdvance<ReadIDiv32, 0>;323def : ReadAdvance<ReadIRem, 0>;324def : ReadAdvance<ReadIRem32, 0>;325def : ReadAdvance<ReadIMul, 0>;326def : ReadAdvance<ReadIMul32, 0>;327def : ReadAdvance<ReadAtomicWA, 0>;328def : ReadAdvance<ReadAtomicWD, 0>;329def : ReadAdvance<ReadAtomicDA, 0>;330def : ReadAdvance<ReadAtomicDD, 0>;331def : ReadAdvance<ReadAtomicLDW, 0>;332def : ReadAdvance<ReadAtomicLDD, 0>;333def : ReadAdvance<ReadAtomicSTW, 0>;334def : ReadAdvance<ReadAtomicSTD, 0>;335def : ReadAdvance<ReadFStoreData, 0>;336def : ReadAdvance<ReadFMemBase, 0>;337def : ReadAdvance<ReadFAdd16, 0>;338def : ReadAdvance<ReadFAdd32, 0>;339def : ReadAdvance<ReadFAdd64, 0>;340def : ReadAdvance<ReadFMul16, 0>;341def : ReadAdvance<ReadFMA16, 0>;342def : ReadAdvance<ReadFMA16Addend, 0>;343def : ReadAdvance<ReadFMul32, 0>;344def : ReadAdvance<ReadFMul64, 0>;345def : ReadAdvance<ReadFMA32, 0>;346def : ReadAdvance<ReadFMA32Addend, 0>;347def : ReadAdvance<ReadFMA64, 0>;348def : ReadAdvance<ReadFMA64Addend, 0>;349def : ReadAdvance<ReadFDiv16, 0>;350def : ReadAdvance<ReadFDiv32, 0>;351def : ReadAdvance<ReadFDiv64, 0>;352def : ReadAdvance<ReadFSqrt16, 0>;353def : ReadAdvance<ReadFSqrt32, 0>;354def : ReadAdvance<ReadFSqrt64, 0>;355def : ReadAdvance<ReadFCmp16, 0>;356def : ReadAdvance<ReadFCmp32, 0>;357def : ReadAdvance<ReadFCmp64, 0>;358def : ReadAdvance<ReadFSGNJ16, 0>;359def : ReadAdvance<ReadFSGNJ32, 0>;360def : ReadAdvance<ReadFSGNJ64, 0>;361def : ReadAdvance<ReadFMinMax16, 0>;362def : ReadAdvance<ReadFMinMax32, 0>;363def : ReadAdvance<ReadFMinMax64, 0>;364def : ReadAdvance<ReadFCvtF16ToI32, 0>;365def : ReadAdvance<ReadFCvtF16ToI64, 0>;366def : ReadAdvance<ReadFCvtF32ToI32, 0>;367def : ReadAdvance<ReadFCvtF32ToI64, 0>;368def : ReadAdvance<ReadFCvtF64ToI32, 0>;369def : ReadAdvance<ReadFCvtF64ToI64, 0>;370def : ReadAdvance<ReadFCvtI32ToF16, 0>;371def : ReadAdvance<ReadFCvtI32ToF32, 0>;372def : ReadAdvance<ReadFCvtI32ToF64, 0>;373def : ReadAdvance<ReadFCvtI64ToF16, 0>;374def : ReadAdvance<ReadFCvtI64ToF32, 0>;375def : ReadAdvance<ReadFCvtI64ToF64, 0>;376def : ReadAdvance<ReadFCvtF32ToF64, 0>;377def : ReadAdvance<ReadFCvtF64ToF32, 0>;378def : ReadAdvance<ReadFCvtF16ToF32, 0>;379def : ReadAdvance<ReadFCvtF32ToF16, 0>;380def : ReadAdvance<ReadFCvtF16ToF64, 0>;381def : ReadAdvance<ReadFCvtF64ToF16, 0>;382def : ReadAdvance<ReadFMovF16ToI16, 0>;383def : ReadAdvance<ReadFMovI16ToF16, 0>;384def : ReadAdvance<ReadFMovF32ToI32, 0>;385def : ReadAdvance<ReadFMovI32ToF32, 0>;386def : ReadAdvance<ReadFMovF64ToI64, 0>;387def : ReadAdvance<ReadFMovI64ToF64, 0>;388def : ReadAdvance<ReadFClass16, 0>;389def : ReadAdvance<ReadFClass32, 0>;390def : ReadAdvance<ReadFClass64, 0>;391 392// Bitmanip393def : ReadAdvance<ReadRotateImm, 0>;394def : ReadAdvance<ReadRotateImm32, 0>;395def : ReadAdvance<ReadRotateReg, 0>;396def : ReadAdvance<ReadRotateReg32, 0>;397def : ReadAdvance<ReadCLZ, 0>;398def : ReadAdvance<ReadCLZ32, 0>;399def : ReadAdvance<ReadCTZ, 0>;400def : ReadAdvance<ReadCTZ32, 0>;401def : ReadAdvance<ReadCPOP, 0>;402def : ReadAdvance<ReadCPOP32, 0>;403def : ReadAdvance<ReadORCB, 0>;404def : ReadAdvance<ReadIMinMax, 0>;405def : ReadAdvance<ReadREV8, 0>;406def : ReadAdvance<ReadSHXADD, 0>;407def : ReadAdvance<ReadSHXADD32, 0>;408// Single-bit instructions409def : ReadAdvance<ReadSingleBit, 0>;410def : ReadAdvance<ReadSingleBitImm, 0>;411 412//===----------------------------------------------------------------------===//413// Vector414def : WriteRes<WriteRdVLENB, [AscalonFXA]>;415 416// Configuration-Setting Instructions417def : WriteRes<WriteVSETVLI, [AscalonV]>;418def : WriteRes<WriteVSETIVLI, [AscalonV]>;419let Latency = 2 in {420 def : WriteRes<WriteVSETVL, [AscalonV]>;421}422 423// Vector Loads and Stores424foreach mx = SchedMxList in {425 defvar Cycles = AscalonGetCyclesDefault<mx>.c;426 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;427 let Latency = Cycles in {428 defm "" : LMULWriteResMX<"WriteVLDE", [AscalonLS], mx, IsWorstCase>;429 defm "" : LMULWriteResMX<"WriteVLDFF", [AscalonLS], mx, IsWorstCase>;430 }431 defm "" : LMULWriteResMX<"WriteVSTE", [AscalonLS], mx, IsWorstCase>;432}433 434foreach mx = SchedMxList in {435 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;436 defm "" : LMULWriteResMX<"WriteVLDM", [AscalonLS], mx, IsWorstCase>;437 defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;438}439 440foreach mx = SchedMxList in {441 defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;442 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;443 let Latency = Cycles in {444 defm "" : LMULWriteResMX<"WriteVLDS8", [AscalonLS], mx, IsWorstCase>;445 defm "" : LMULWriteResMX<"WriteVLDUX8", [AscalonLS], mx, IsWorstCase>;446 defm "" : LMULWriteResMX<"WriteVLDOX8", [AscalonLS], mx, IsWorstCase>;447 defm "" : LMULWriteResMX<"WriteVSTS8", [AscalonLS], mx, IsWorstCase>;448 defm "" : LMULWriteResMX<"WriteVSTUX8", [AscalonLS], mx, IsWorstCase>;449 defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;450 }451}452foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {453 defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;454 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;455 let Latency = Cycles in {456 defm "" : LMULWriteResMX<"WriteVLDS16", [AscalonLS], mx, IsWorstCase>;457 defm "" : LMULWriteResMX<"WriteVLDUX16", [AscalonLS], mx, IsWorstCase>;458 defm "" : LMULWriteResMX<"WriteVLDOX16", [AscalonLS], mx, IsWorstCase>;459 defm "" : LMULWriteResMX<"WriteVSTS16", [AscalonLS], mx, IsWorstCase>;460 defm "" : LMULWriteResMX<"WriteVSTUX16", [AscalonLS], mx, IsWorstCase>;461 defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;462 }463}464foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {465 defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;466 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;467 let Latency = Cycles in {468 defm "" : LMULWriteResMX<"WriteVLDS32", [AscalonLS], mx, IsWorstCase>;469 defm "" : LMULWriteResMX<"WriteVLDUX32", [AscalonLS], mx, IsWorstCase>;470 defm "" : LMULWriteResMX<"WriteVLDOX32", [AscalonLS], mx, IsWorstCase>;471 defm "" : LMULWriteResMX<"WriteVSTS32", [AscalonLS], mx, IsWorstCase>;472 defm "" : LMULWriteResMX<"WriteVSTUX32", [AscalonLS], mx, IsWorstCase>;473 defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;474 }475}476foreach mx = ["M1", "M2", "M4", "M8"] in {477 defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;478 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;479 let Latency = Cycles in {480 defm "" : LMULWriteResMX<"WriteVLDS64", [AscalonLS], mx, IsWorstCase>;481 defm "" : LMULWriteResMX<"WriteVLDUX64", [AscalonLS], mx, IsWorstCase>;482 defm "" : LMULWriteResMX<"WriteVLDOX64", [AscalonLS], mx, IsWorstCase>;483 defm "" : LMULWriteResMX<"WriteVSTS64", [AscalonLS], mx, IsWorstCase>;484 defm "" : LMULWriteResMX<"WriteVSTUX64", [AscalonLS], mx, IsWorstCase>;485 defm "" : LMULWriteResMX<"WriteVSTOX64", [AscalonLS], mx, IsWorstCase>;486 }487}488 489// VLD*R is not LMUL aware490def : WriteRes<WriteVLD1R, [AscalonLS]>;491def : WriteRes<WriteVLD2R, [AscalonLS]>;492def : WriteRes<WriteVLD4R, [AscalonLS]>;493def : WriteRes<WriteVLD8R, [AscalonLS]>;494// VST*R is not LMUL aware495def : WriteRes<WriteVST1R, [AscalonLS]>;496def : WriteRes<WriteVST2R, [AscalonLS]>;497def : WriteRes<WriteVST4R, [AscalonLS]>;498def : WriteRes<WriteVST8R, [AscalonLS]>;499 500// Segmented Loads and Stores501foreach mx = SchedMxList in {502 foreach eew = [8, 16, 32, 64] in {503 foreach nf=2-8 in {504 defvar Cycles = AscalonGetCyclesDefault<mx>.c;505 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;506 let Latency = Cycles in {507 defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;508 defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;509 }510 let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in511 defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;512 }513 }514}515foreach mx = SchedMxList in {516 foreach nf=2-8 in {517 foreach eew = [8, 16, 32, 64] in {518 defvar Cycles = AscalonGetCyclesStridedSegmented<mx, eew>.c;519 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;520 let Latency = Cycles in {521 defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;522 defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;523 defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;524 defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;525 defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;526 defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;527 }528 }529 }530}531 532// Vector Fixed-Point Arithmetic Instructions533foreach mx = SchedMxList in {534 defvar Cycles = AscalonGetCyclesDefault<mx>.c;535 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;536 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {537 defm "" : LMULWriteResMX<"WriteVSALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;538 defm "" : LMULWriteResMX<"WriteVSALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;539 defm "" : LMULWriteResMX<"WriteVSALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;540 defm "" : LMULWriteResMX<"WriteVAALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;541 defm "" : LMULWriteResMX<"WriteVAALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;542 defm "" : LMULWriteResMX<"WriteVSMulV", [AscalonFXA, AscalonV], mx, IsWorstCase>;543 defm "" : LMULWriteResMX<"WriteVSMulX", [AscalonFXA, AscalonV], mx, IsWorstCase>;544 defm "" : LMULWriteResMX<"WriteVSShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;545 defm "" : LMULWriteResMX<"WriteVSShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;546 defm "" : LMULWriteResMX<"WriteVSShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;547 }548}549// Narrowing550foreach mx = SchedMxListW in {551 defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;552 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;553 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {554 defm "" : LMULWriteResMX<"WriteVNClipV", [AscalonFX, AscalonV], mx, IsWorstCase>;555 defm "" : LMULWriteResMX<"WriteVNClipX", [AscalonFX, AscalonV], mx, IsWorstCase>;556 defm "" : LMULWriteResMX<"WriteVNClipI", [AscalonFX, AscalonV], mx, IsWorstCase>;557 }558}559 560// Configuration-Setting Instructions561def : ReadAdvance<ReadVSETVLI, 1>;562def : ReadAdvance<ReadVSETVL, 1>;563 564// Vector Loads and Stores565def : ReadAdvance<ReadVLDX, 0>;566def : ReadAdvance<ReadVSTX, 0>;567defm "" : LMULReadAdvance<"ReadVSTEV", 0>;568defm "" : LMULReadAdvance<"ReadVSTM", 0>;569def : ReadAdvance<ReadVLDSX, 0>;570def : ReadAdvance<ReadVSTSX, 0>;571defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;572defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;573defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;574defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;575defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;576defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;577defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;578defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;579defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;580defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;581defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;582defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;583defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;584defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;585defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;586defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;587defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;588defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;589defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;590defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;591defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;592defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;593defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;594defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;595// LMUL Aware596def : ReadAdvance<ReadVST1R, 0>;597def : ReadAdvance<ReadVST2R, 0>;598def : ReadAdvance<ReadVST4R, 0>;599def : ReadAdvance<ReadVST8R, 0>;600 601// Vector Integer Arithmetic Instructions602foreach mx = SchedMxList in {603 defvar Cycles = AscalonGetCyclesDefault<mx>.c;604 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;605 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {606 defm "" : LMULWriteResMX<"WriteVIALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;607 defm "" : LMULWriteResMX<"WriteVIALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;608 defm "" : LMULWriteResMX<"WriteVIALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;609 defm "" : LMULWriteResMX<"WriteVICALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;610 defm "" : LMULWriteResMX<"WriteVICALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;611 defm "" : LMULWriteResMX<"WriteVICALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;612 defm "" : LMULWriteResMX<"WriteVICALUMV", [AscalonFX, AscalonV], mx, IsWorstCase>;613 defm "" : LMULWriteResMX<"WriteVICALUMX", [AscalonFX, AscalonV], mx, IsWorstCase>;614 defm "" : LMULWriteResMX<"WriteVICALUMI", [AscalonFX, AscalonV], mx, IsWorstCase>;615 defm "" : LMULWriteResMX<"WriteVShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;616 defm "" : LMULWriteResMX<"WriteVShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;617 defm "" : LMULWriteResMX<"WriteVShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;618 defm "" : LMULWriteResMX<"WriteVIMinMaxV", [AscalonFX, AscalonV], mx, IsWorstCase>;619 defm "" : LMULWriteResMX<"WriteVIMinMaxX", [AscalonFX, AscalonV], mx, IsWorstCase>;620 defm "" : LMULWriteResMX<"WriteVIMulV", [AscalonFX, AscalonV], mx, IsWorstCase>;621 defm "" : LMULWriteResMX<"WriteVIMulX", [AscalonFX, AscalonV], mx, IsWorstCase>;622 defm "" : LMULWriteResMX<"WriteVIMulAddV", [AscalonFX, AscalonV], mx, IsWorstCase>;623 defm "" : LMULWriteResMX<"WriteVIMulAddX", [AscalonFX, AscalonV], mx, IsWorstCase>;624 defm "" : LMULWriteResMX<"WriteVIMergeV", [AscalonFX, AscalonV], mx, IsWorstCase>;625 defm "" : LMULWriteResMX<"WriteVIMergeX", [AscalonFX, AscalonV], mx, IsWorstCase>;626 defm "" : LMULWriteResMX<"WriteVIMergeI", [AscalonFX, AscalonV], mx, IsWorstCase>;627 defm "" : LMULWriteResMX<"WriteVIMovV", [AscalonFX, AscalonV], mx, IsWorstCase>;628 defm "" : LMULWriteResMX<"WriteVIMovX", [AscalonFX, AscalonV], mx, IsWorstCase>;629 defm "" : LMULWriteResMX<"WriteVIMovI", [AscalonFX, AscalonV], mx, IsWorstCase>;630 defm "" : LMULWriteResMX<"WriteVICmpV", [AscalonFX, AscalonV], mx, IsWorstCase>;631 defm "" : LMULWriteResMX<"WriteVICmpX", [AscalonFX, AscalonV], mx, IsWorstCase>;632 defm "" : LMULWriteResMX<"WriteVICmpI", [AscalonFX, AscalonV], mx, IsWorstCase>;633 }634}635foreach mx = SchedMxList in {636 defvar Cycles = AscalonGetCyclesDefault<mx>.c;637 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;638 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {639 defm "" : LMULWriteResMX<"WriteVExtV", [AscalonFX, AscalonV], mx, IsWorstCase>;640 }641}642foreach mx = SchedMxList in {643 foreach sew = SchedSEWSet<mx>.val in {644 defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;645 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;646 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {647 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;648 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;649 }650 }651}652 653// Widening654foreach mx = SchedMxListW in {655 defvar Cycles = AscalonGetCyclesDefault<mx>.c;656 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;657 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {658 defm "" : LMULWriteResMX<"WriteVIWALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;659 defm "" : LMULWriteResMX<"WriteVIWALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;660 defm "" : LMULWriteResMX<"WriteVIWALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;661 defm "" : LMULWriteResMX<"WriteVIWMulV", [AscalonFX, AscalonV], mx, IsWorstCase>;662 defm "" : LMULWriteResMX<"WriteVIWMulX", [AscalonFX, AscalonV], mx, IsWorstCase>;663 defm "" : LMULWriteResMX<"WriteVIWMulAddV", [AscalonFX, AscalonV], mx, IsWorstCase>;664 defm "" : LMULWriteResMX<"WriteVIWMulAddX", [AscalonFX, AscalonV], mx, IsWorstCase>;665 }666}667// Narrowing668foreach mx = SchedMxListW in {669 defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;670 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;671 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {672 defm "" : LMULWriteResMX<"WriteVNShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;673 defm "" : LMULWriteResMX<"WriteVNShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;674 defm "" : LMULWriteResMX<"WriteVNShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;675 }676}677 678// Vector Floating-Point Instructions679foreach mx = SchedMxListF in {680 foreach sew = SchedSEWSet<mx, isF=1>.val in {681 defvar Cycles = AscalonGetCyclesDefault<mx>.c;682 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;683 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {684 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;685 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;686 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;687 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;688 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;689 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;690 defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;691 defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;692 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;693 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;694 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;695 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;696 }697 }698}699foreach mx = SchedMxList in {700 defvar Cycles = AscalonGetCyclesDefault<mx>.c;701 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;702 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {703 defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;704 defm "" : LMULWriteResMX<"WriteVFClassV", [AscalonFP, AscalonV], mx, IsWorstCase>;705 defm "" : LMULWriteResMX<"WriteVFMergeV", [AscalonFP, AscalonV], mx, IsWorstCase>;706 defm "" : LMULWriteResMX<"WriteVFMovV", [AscalonFP, AscalonV], mx, IsWorstCase>;707 defm "" : LMULWriteResMX<"WriteVFCmpV", [AscalonFP, AscalonV], mx, IsWorstCase>;708 defm "" : LMULWriteResMX<"WriteVFCmpF", [AscalonFP, AscalonV], mx, IsWorstCase>;709 }710}711foreach mx = SchedMxListF in {712 foreach sew = SchedSEWSet<mx, isF=1>.val in {713 defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;714 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;715 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {716 defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;717 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;718 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;719 }720 }721}722 723// Widening724foreach mx = SchedMxListW in {725 foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {726 defvar Cycles = AscalonGetCyclesDefault<mx>.c;727 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;728 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in729 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;730 }731}732foreach mx = SchedMxListFW in {733 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {734 defvar Cycles = AscalonGetCyclesDefault<mx>.c;735 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;736 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {737 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;738 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;739 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;740 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;741 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;742 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;743 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;744 }745 }746 defvar Cycles = AscalonGetCyclesDefault<mx>.c;747 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListFW>.c;748 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in749 defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;750}751// Narrowing752foreach mx = SchedMxListW in {753 defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;754 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;755 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {756 defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;757 }758}759foreach mx = SchedMxListFW in {760 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {761 defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;762 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;763 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {764 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;765 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;766 }767 }768}769 770// Vector Reduction Instructions771foreach mx = SchedMxList in {772 foreach sew = SchedSEWSet<mx>.val in {773 defvar Cycles = AscalonGetCyclesDefault<mx>.c;774 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;775 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {776 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [AscalonFX, AscalonV],777 mx, sew, IsWorstCase>;778 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [AscalonFX, AscalonV],779 mx, sew, IsWorstCase>;780 }781 }782}783 784foreach mx = SchedMxListWRed in {785 foreach sew = SchedSEWSet<mx, 0, 1>.val in {786 defvar Cycles = AscalonGetCyclesDefault<mx>.c;787 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;788 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in789 defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [AscalonFX, AscalonV],790 mx, sew, IsWorstCase>;791 }792}793 794foreach mx = SchedMxListF in {795 foreach sew = SchedSEWSet<mx, 1>.val in {796 defvar RedCycles = AscalonGetCyclesDefault<mx>.c;797 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;798 let Latency = RedCycles, ReleaseAtCycles = [1, RedCycles] in {799 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [AscalonFX, AscalonV],800 mx, sew, IsWorstCase>;801 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [AscalonFX, AscalonV],802 mx, sew, IsWorstCase>;803 }804 defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;805 let Latency = OrdRedCycles, ReleaseAtCycles = [1, OrdRedCycles] in806 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [AscalonFX, AscalonV],807 mx, sew, IsWorstCase>;808 }809}810 811foreach mx = SchedMxListFWRed in {812 foreach sew = SchedSEWSet<mx, 1, 1>.val in {813 defvar RedCycles = AscalonGetCyclesDefault<mx>.c;814 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;815 let Latency = RedCycles, ReleaseAtCycles = [1, RedCycles] in816 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [AscalonFX, AscalonV],817 mx, sew, IsWorstCase>;818 defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;819 let Latency = OrdRedCycles, ReleaseAtCycles = [1, OrdRedCycles] in820 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [AscalonFX, AscalonV],821 mx, sew, IsWorstCase>;822 }823}824 825// Vector Mask Instructions826foreach mx = SchedMxList in {827 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;828 defm "" : LMULWriteResMX<"WriteVMALUV", [AscalonV], mx, IsWorstCase>;829 defm "" : LMULWriteResMX<"WriteVMSFSV", [AscalonV], mx, IsWorstCase>;830 let Latency = 2, ReleaseAtCycles = [1, 2] in {831 defm "" : LMULWriteResMX<"WriteVMPopV", [AscalonFX, AscalonV], mx, IsWorstCase>;832 defm "" : LMULWriteResMX<"WriteVMFFSV", [AscalonFX, AscalonV], mx, IsWorstCase>;833 }834}835foreach mx = SchedMxList in {836 defvar Cycles = AscalonGetCyclesDefault<mx>.c;837 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;838 let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {839 defm "" : LMULWriteResMX<"WriteVIotaV", [AscalonFX, AscalonV], mx, IsWorstCase>;840 defm "" : LMULWriteResMX<"WriteVIdxV", [AscalonFX, AscalonV], mx, IsWorstCase>;841 }842}843 844// Vector Permutation Instructions845let Latency = 2, ReleaseAtCycles = [1, 2] in {846 def : WriteRes<WriteVMovSX, [AscalonFX, AscalonV]>;847 def : WriteRes<WriteVMovXS, [AscalonFX, AscalonV]>;848 def : WriteRes<WriteVMovSF, [AscalonFX, AscalonV]>;849 def : WriteRes<WriteVMovFS, [AscalonFX, AscalonV]>;850}851foreach mx = SchedMxList in {852 defvar Cycles = AscalonGetCyclesDefault<mx>.c;853 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;854 let Latency = !mul(Cycles, 2), ReleaseAtCycles = [Cycles, !mul(Cycles, 2)] in {855 defm "" : LMULWriteResMX<"WriteVRGatherVX", [AscalonFX, AscalonV], mx, IsWorstCase>;856 defm "" : LMULWriteResMX<"WriteVRGatherVI", [AscalonFX, AscalonV], mx, IsWorstCase>;857 }858}859 860foreach mx = SchedMxList in {861 foreach sew = SchedSEWSet<mx>.val in {862 defvar Cycles = AscalonGetCyclesVRGatherVV<mx>.c;863 defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;864 let Latency = !add(Cycles, 3), ReleaseAtCycles = [1, !add(1, Cycles)] in {865 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;866 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;867 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;868 }869 }870}871 872foreach mx = SchedMxList in {873 defvar Cycles = AscalonGetCyclesDefault<mx>.c;874 defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;875 let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {876 defm "" : LMULWriteResMX<"WriteVSlideUpX", [AscalonFX, AscalonV], mx, IsWorstCase>;877 defm "" : LMULWriteResMX<"WriteVSlideDownX", [AscalonFX, AscalonV], mx, IsWorstCase>;878 defm "" : LMULWriteResMX<"WriteVSlideI", [AscalonFX, AscalonV], mx, IsWorstCase>;879 defm "" : LMULWriteResMX<"WriteVISlide1X", [AscalonFX, AscalonV], mx, IsWorstCase>;880 defm "" : LMULWriteResMX<"WriteVFSlide1F", [AscalonFX, AscalonV], mx, IsWorstCase>;881 }882}883 884// Whole vector register move, vmv<N>.v, not LMUL aware885let Latency = 1, ReleaseAtCycles = [1] in886 def : WriteRes<WriteVMov1V, [AscalonV]>;887let Latency = 2, ReleaseAtCycles = [2] in888 def : WriteRes<WriteVMov2V, [AscalonV]>;889let Latency = 4, ReleaseAtCycles = [4] in890 def : WriteRes<WriteVMov4V, [AscalonV]>;891let Latency = 8, ReleaseAtCycles = [8] in892 def : WriteRes<WriteVMov8V, [AscalonV]>;893 894// Vector Integer Arithmetic Instructions895defm : LMULReadAdvance<"ReadVIALUV", 0>;896defm : LMULReadAdvance<"ReadVIALUX", 0>;897defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;898defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;899defm : LMULReadAdvance<"ReadVExtV", 0>;900defm : LMULReadAdvance<"ReadVICALUV", 0>;901defm : LMULReadAdvance<"ReadVICALUX", 0>;902defm : LMULReadAdvance<"ReadVShiftV", 0>;903defm : LMULReadAdvance<"ReadVShiftX", 0>;904defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;905defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;906defm : LMULReadAdvance<"ReadVICmpV", 0>;907defm : LMULReadAdvance<"ReadVICmpX", 0>;908defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;909defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;910defm : LMULReadAdvance<"ReadVIMulV", 0>;911defm : LMULReadAdvance<"ReadVIMulX", 0>;912defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;913defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;914defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;915defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;916defm : LMULReadAdvance<"ReadVIMulAddV", 0>;917defm : LMULReadAdvance<"ReadVIMulAddX", 0>;918defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;919defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;920defm : LMULReadAdvance<"ReadVIMergeV", 0>;921defm : LMULReadAdvance<"ReadVIMergeX", 0>;922defm : LMULReadAdvance<"ReadVIMovV", 0>;923defm : LMULReadAdvance<"ReadVIMovX", 0>;924 925// Vector Fixed-Point Arithmetic Instructions926defm "" : LMULReadAdvance<"ReadVSALUV", 0>;927defm "" : LMULReadAdvance<"ReadVSALUX", 0>;928defm "" : LMULReadAdvance<"ReadVAALUV", 0>;929defm "" : LMULReadAdvance<"ReadVAALUX", 0>;930defm "" : LMULReadAdvance<"ReadVSMulV", 0>;931defm "" : LMULReadAdvance<"ReadVSMulX", 0>;932defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;933defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;934defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;935defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;936 937// Vector Floating-Point Instructions938defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;939defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;940defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;941defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;942defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;943defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;944defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;945defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;946defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;947defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;948defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;949defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;950defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;951defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;952defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;953defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;954defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;955defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;956defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;957defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;958defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;959defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;960defm "" : LMULReadAdvance<"ReadVFClassV", 0>;961defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;962defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;963defm "" : LMULReadAdvance<"ReadVFMovF", 0>;964defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;965defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;966defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;967defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;968defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;969defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;970defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;971defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;972 973// Vector Reduction Instructions974def : ReadAdvance<ReadVIRedV, 0>;975def : ReadAdvance<ReadVIRedV0, 0>;976def : ReadAdvance<ReadVIWRedV, 0>;977def : ReadAdvance<ReadVIWRedV0, 0>;978def : ReadAdvance<ReadVFRedV, 0>;979def : ReadAdvance<ReadVFRedV0, 0>;980def : ReadAdvance<ReadVFRedOV, 0>;981def : ReadAdvance<ReadVFRedOV0, 0>;982def : ReadAdvance<ReadVFWRedV, 0>;983def : ReadAdvance<ReadVFWRedV0, 0>;984def : ReadAdvance<ReadVFWRedOV, 0>;985def : ReadAdvance<ReadVFWRedOV0, 0>;986 987// Vector Mask Instructions988defm "" : LMULReadAdvance<"ReadVMALUV", 0>;989defm "" : LMULReadAdvance<"ReadVMPopV", 0>;990defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;991defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;992defm "" : LMULReadAdvance<"ReadVIotaV", 0>;993 994// Vector Permutation Instructions995def : ReadAdvance<ReadVMovXS, 0>;996def : ReadAdvance<ReadVMovSX_V, 0>;997def : ReadAdvance<ReadVMovSX_X, 0>;998def : ReadAdvance<ReadVMovFS, 0>;999def : ReadAdvance<ReadVMovSF_V, 0>;1000def : ReadAdvance<ReadVMovSF_F, 0>;1001defm "" : LMULReadAdvance<"ReadVISlideV", 0>;1002defm "" : LMULReadAdvance<"ReadVISlideX", 0>;1003defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;1004defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;1005defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;1006defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;1007defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;1008defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;1009defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;1010defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;1011defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;1012defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;1013// LMUL Aware1014def : ReadAdvance<ReadVMov1V, 0>;1015def : ReadAdvance<ReadVMov2V, 0>;1016def : ReadAdvance<ReadVMov4V, 0>;1017def : ReadAdvance<ReadVMov8V, 0>;1018 1019// Others1020def : ReadAdvance<ReadVMask, 0>;1021def : ReadAdvance<ReadVPassthru_WorstCase, 0>;1022foreach mx = SchedMxList in {1023 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;1024 foreach sew = SchedSEWSet<mx>.val in1025 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;1026}1027 1028//===----------------------------------------------------------------------===//1029// Unsupported extensions1030defm : UnsupportedSchedQ;1031defm : UnsupportedSchedZabha;1032defm : UnsupportedSchedZbc;1033defm : UnsupportedSchedZbkb;1034defm : UnsupportedSchedZbkx;1035defm : UnsupportedSchedZfa;1036defm : UnsupportedSchedZvk;1037defm : UnsupportedSchedSFB;1038defm : UnsupportedSchedXsf;1039}1040