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1//===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10/// Define scheduler resources associated with def operands.11 12defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];13// Used for widening and narrowing instructions as it doesn't contain M8.14defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);15// Used for widening reductions, which does contain M8.16defvar SchedMxListWRed = SchedMxList;17defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);18// Used for floating-point as it doesn't contain MF8.19defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);20// Used for widening floating-point Reduction as it doesn't contain MF8.21defvar SchedMxListFWRed = SchedMxListF;22 23class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {24 assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";25 defvar t = !cond(!eq(mx, "M1"): [8, 16, 32, 64],26 !eq(mx, "M2"): [8, 16, 32, 64],27 !eq(mx, "M4"): [8, 16, 32, 64],28 !eq(mx, "M8"): [8, 16, 32, 64],29 !eq(mx, "MF2"): [8, 16, 32],30 !eq(mx, "MF4"): [8, 16],31 !eq(mx, "MF8"): [8]);32 // For floating-point instructions, SEW won't be 8.33 defvar remove8 = !if(isF, !listremove(t, [8]), t);34 // For widening instructions, SEW will not be 64.35 defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8);36 list<int> val = remove64;37}38 39// Helper function to get the largest LMUL from MxList40// Precondition: MxList is sorted in ascending LMUL order.41class LargestLMUL<list<string> MxList> {42 // MX list is sorted from smallest to largest43 string r = !foldl(!head(MxList), MxList, last, curr, curr);44}45// Helper function to get the smallest SEW that can be used with LMUL mx46// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>47class SmallestSEW<string mx, bit isF = 0> {48 int r = !head(SchedSEWSet<mx, isF>.val);49}50 51// Creates WriteRes for (name, mx, resources) tuple52multiclass LMULWriteResMX<string name, list<ProcResourceKind> resources,53 string mx, bit IsWorstCase> {54 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;55 if IsWorstCase then56 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;57}58multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,59 string mx, int sew, bit IsWorstCase> {60 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;61 if IsWorstCase then62 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;63}64 65// Define a SchedAlias for the SchedWrite associated with (name, mx) whose66// behavior is aliased to a Variant. The Variant has Latency predLad and67// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has68// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite69// is created similarly if IsWorstCase is true.70multiclass LMULWriteResVariantImpl<string name, string writeResName, SchedPredicateBase Pred,71 list<ProcResourceKind> predResources,72 int predLat, list<int> predAcquireCycles,73 list<int> predReleaseCycles,74 list<ProcResourceKind> noPredResources,75 int noPredLat, list<int> noPredAcquireCycles,76 list<int> noPredReleaseCycles,77 bit IsWorstCase> {78 // Define the different behaviors79 def writeResName # "_Pred" : SchedWriteRes<predResources>{80 let Latency = predLat;81 let AcquireAtCycles = predAcquireCycles;82 let ReleaseAtCycles = predReleaseCycles;83 }84 def writeResName # "_NoPred" : SchedWriteRes<noPredResources> {85 let Latency = noPredLat;86 let AcquireAtCycles = noPredAcquireCycles;87 let ReleaseAtCycles = noPredReleaseCycles;88 }89 90 // Define SchedVars91 def writeResName # PredSchedVar92 : SchedVar<Pred, [!cast<SchedWriteRes>(NAME # writeResName # "_Pred")]>;93 def writeResName # NoPredSchedVar94 : SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # writeResName #"_NoPred")]>;95 // Allow multiclass to refer to SchedVars -- need to have NAME prefix.96 defvar PredSchedVar = !cast<SchedVar>(NAME # writeResName # PredSchedVar);97 defvar NoPredSchedVar = !cast<SchedVar>(NAME # writeResName # NoPredSchedVar);98 99 // Tie behavior to predicate100 def NAME # writeResName # "_Variant"101 : SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>;102 def : SchedAlias<103 !cast<SchedReadWrite>(writeResName),104 !cast<SchedReadWrite>(NAME # writeResName # "_Variant")>;105 106 if IsWorstCase then {107 def NAME # name # "_WorstCase_Variant"108 : SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>;109 def : SchedAlias<110 !cast<SchedReadWrite>(name # "_WorstCase"),111 !cast<SchedReadWrite>(NAME # name # "_WorstCase_Variant")>;112 }113}114 115multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,116 list<ProcResourceKind> predResources,117 int predLat, list<int> predAcquireCycles,118 list<int> predReleaseCycles,119 list<ProcResourceKind> noPredResources,120 int noPredLat, list<int> noPredAcquireCycles,121 list<int> noPredReleaseCycles,122 string mx, bit IsWorstCase> {123 defm "" : LMULWriteResVariantImpl<name, name # "_" # mx, Pred, predResources,124 predLat, predAcquireCycles,125 predReleaseCycles, noPredResources,126 noPredLat, noPredAcquireCycles,127 noPredReleaseCycles,128 IsWorstCase>;129}130 131multiclass LMULSEWWriteResMXSEWVariant<string name, SchedPredicateBase Pred,132 list<ProcResourceKind> predResources,133 int predLat, list<int> predAcquireCycles,134 list<int> predReleaseCycles,135 list<ProcResourceKind> noPredResources,136 int noPredLat, list<int> noPredAcquireCycles,137 list<int> noPredReleaseCycles,138 string mx, int sew, bit IsWorstCase> {139 defm "" : LMULWriteResVariantImpl<name, name # "_" # mx # "_E" # sew, Pred, predResources,140 predLat, predAcquireCycles,141 predReleaseCycles, noPredResources,142 noPredLat, noPredAcquireCycles,143 noPredReleaseCycles,144 IsWorstCase>;145}146 147// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and148// ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the149// SchedMxList variants above. Each multiclass is responsible for defining150// a record that represents the WorseCase behavior for name.151multiclass LMULSchedWritesImpl<string name, list<string> MxList> {152 def name # "_WorstCase" : SchedWrite;153 foreach mx = MxList in {154 def name # "_" # mx : SchedWrite;155 }156}157multiclass LMULSchedReadsImpl<string name, list<string> MxList> {158 def name # "_WorstCase" : SchedRead;159 foreach mx = MxList in {160 def name # "_" # mx : SchedRead;161 }162}163multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> {164 if !exists<SchedWrite>(name # "_WorstCase") then165 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;166 foreach mx = SchedMxList in {167 if !exists<SchedWrite>(name # "_" # mx) then168 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;169 }170}171multiclass LMULReadAdvanceImpl<string name, int val,172 list<SchedWrite> writes = []> {173 if !exists<SchedRead>(name # "_WorstCase") then174 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;175 foreach mx = SchedMxList in {176 if !exists<SchedRead>(name # "_" # mx) then177 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;178 }179}180 181// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and182// ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the183// SchedMxList variants above. Each multiclass is responsible for defining184// a record that represents the WorseCase behavior for name.185multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0,186 bit isWidening = 0> {187 def name # "_WorstCase" : SchedWrite;188 foreach mx = MxList in {189 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in190 def name # "_" # mx # "_E" # sew : SchedWrite;191 }192}193multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0,194 bit isWidening = 0> {195 def name # "_WorstCase" : SchedRead;196 foreach mx = MxList in {197 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in198 def name # "_" # mx # "_E" # sew : SchedRead;199 }200}201multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,202 list<string> MxList, bit isF = 0,203 bit isWidening = 0> {204 if !exists<SchedWrite>(name # "_WorstCase") then205 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;206 foreach mx = MxList in {207 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in208 if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then209 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;210 }211}212multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],213 list<string> MxList, bit isF = 0,214 bit isWidening = 0> {215 if !exists<SchedRead>(name # "_WorstCase") then216 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;217 foreach mx = MxList in {218 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in219 if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then220 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;221 }222}223// Define classes to define list containing all SchedWrites for each (name, LMUL)224// pair for each LMUL in each of the SchedMxList variants above and name in225// argument `names`. These classes can be used to construct a list of existing226// definitions of writes corresponding to each (name, LMUL) pair, that are needed227// by the ReadAdvance. For example:228// ```229// defm "" : LMULReadAdvance<"ReadVIALUX", 1,230// LMULSchedWriteList<["WriteVMovSX"]>.value>;231// ```232class LMULSchedWriteListImpl<list<string> names, list<string> MxList> {233 list<SchedWrite> value = !foldl([]<SchedWrite>,234 !foreach(name, names,235 !foreach(mx, MxList, !cast<SchedWrite>(name # "_" # mx))),236 all, writes, !listconcat(all, writes));237}238 239multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;240multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;241multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>242 : LMULWriteResImpl<name, resources>;243multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>244 : LMULReadAdvanceImpl<name, val, writes>;245class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;246 247multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>;248multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>;249multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources>250 : LMULSEWWriteResImpl<name, resources, SchedMxList>;251multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []>252 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxList>;253 254multiclass LMULSEWSchedWritesWRed<string name>255 : LMULSEWSchedWritesImpl<name, SchedMxListWRed, isWidening=1>;256multiclass LMULSEWWriteResWRed<string name, list<ProcResourceKind> resources>257 : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, isWidening=1>;258 259multiclass LMULSEWSchedWritesFWRed<string name>260 : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, isF=1, isWidening=1>;261multiclass LMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources>262 : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>;263 264multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, isF=1>;265multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, isF=1>;266multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources>267 : LMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>;268multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>269 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>;270 271multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;272multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;273multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>274 : LMULWriteResImpl<name, resources>;275multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>276 : LMULReadAdvanceImpl<name, val, writes>;277class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;278 279multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;280multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;281multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>282 : LMULWriteResImpl<name, resources>;283multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>284 : LMULReadAdvanceImpl<name, val, writes>;285class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;286 287multiclass LMULSEWSchedWritesW<string name>288 : LMULSEWSchedWritesImpl<name, SchedMxListW, isF = 0, isWidening = 1>;289multiclass LMULSEWSchedReadsW<string name>290 : LMULSEWSchedReadsImpl<name, SchedMxListW, isF = 0, isWidening = 1>;291multiclass LMULSEWWriteResW<string name, list<ProcResourceKind> resources>292 : LMULSEWWriteResImpl<name, resources, SchedMxListW, isF = 0,293 isWidening = 1>;294multiclass295 LMULSEWReadAdvanceW<string name, int val, list<SchedWrite> writes = []>296 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListW, isF = 0,297 isWidening = 1>;298 299multiclass LMULSEWSchedWritesFW<string name>300 : LMULSEWSchedWritesImpl<name, SchedMxListFW, isF = 1, isWidening = 1>;301multiclass LMULSEWSchedReadsFW<string name>302 : LMULSEWSchedReadsImpl<name, SchedMxListFW, isF = 1, isWidening = 1>;303multiclass LMULSEWWriteResFW<string name, list<ProcResourceKind> resources>304 : LMULSEWWriteResImpl<name, resources, SchedMxListFW, isF = 1,305 isWidening = 1>;306multiclass307 LMULSEWReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>308 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListFW, isF = 1,309 isWidening = 1>;310 311// 3.6 Vector Byte Length vlenb312def WriteRdVLENB : SchedWrite;313 314// 6. Configuration-Setting Instructions315def WriteVSETVLI : SchedWrite;316def WriteVSETIVLI : SchedWrite;317def WriteVSETVL : SchedWrite;318 319// 7. Vector Loads and Stores320// 7.4. Vector Unit-Stride Instructions321defm "" : LMULSchedWrites<"WriteVLDE">;322defm "" : LMULSchedWrites<"WriteVSTE">;323// 7.4.1. Vector Unit-Strided Mask324defm "" : LMULSchedWrites<"WriteVLDM">;325defm "" : LMULSchedWrites<"WriteVSTM">;326// 7.5. Vector Strided Instructions327defm "" : LMULSchedWrites<"WriteVLDS8">;328defm "" : LMULSchedWrites<"WriteVLDS16">;329defm "" : LMULSchedWrites<"WriteVLDS32">;330defm "" : LMULSchedWrites<"WriteVLDS64">;331defm "" : LMULSchedWrites<"WriteVSTS8">;332defm "" : LMULSchedWrites<"WriteVSTS16">;333defm "" : LMULSchedWrites<"WriteVSTS32">;334defm "" : LMULSchedWrites<"WriteVSTS64">;335// 7.6. Vector Indexed Instructions336defm "" : LMULSchedWrites<"WriteVLDUX8">;337defm "" : LMULSchedWrites<"WriteVLDUX16">;338defm "" : LMULSchedWrites<"WriteVLDUX32">;339defm "" : LMULSchedWrites<"WriteVLDUX64">;340defm "" : LMULSchedWrites<"WriteVLDOX8">;341defm "" : LMULSchedWrites<"WriteVLDOX16">;342defm "" : LMULSchedWrites<"WriteVLDOX32">;343defm "" : LMULSchedWrites<"WriteVLDOX64">;344defm "" : LMULSchedWrites<"WriteVSTUX8">;345defm "" : LMULSchedWrites<"WriteVSTUX16">;346defm "" : LMULSchedWrites<"WriteVSTUX32">;347defm "" : LMULSchedWrites<"WriteVSTUX64">;348defm "" : LMULSchedWrites<"WriteVSTOX8">;349defm "" : LMULSchedWrites<"WriteVSTOX16">;350defm "" : LMULSchedWrites<"WriteVSTOX32">;351defm "" : LMULSchedWrites<"WriteVSTOX64">;352// 7.7. Vector Unit-stride Fault-Only-First Loads353defm "" : LMULSchedWrites<"WriteVLDFF">;354// 7.8. Vector Segment Instructions355foreach nf=2-8 in {356 foreach eew = [8, 16, 32, 64] in {357 defm "" : LMULSchedWrites<"WriteVLSEG" # nf # e # eew>;358 defm "" : LMULSchedWrites<"WriteVSSEG" # nf # e # eew>;359 defm "" : LMULSchedWrites<"WriteVLSEGFF" # nf # e # eew>;360 defm "" : LMULSchedWrites<"WriteVLSSEG" # nf # e # eew>;361 defm "" : LMULSchedWrites<"WriteVSSSEG" # nf # e # eew>;362 defm "" : LMULSchedWrites<"WriteVLUXSEG" # nf # e # eew>;363 defm "" : LMULSchedWrites<"WriteVLOXSEG" # nf # e # eew>;364 defm "" : LMULSchedWrites<"WriteVSUXSEG" # nf # e # eew>;365 defm "" : LMULSchedWrites<"WriteVSOXSEG" # nf # e # eew>;366 }367}368// 7.9. Vector Whole Register Instructions369def WriteVLD1R : SchedWrite;370def WriteVLD2R : SchedWrite;371def WriteVLD4R : SchedWrite;372def WriteVLD8R : SchedWrite;373def WriteVST1R : SchedWrite;374def WriteVST2R : SchedWrite;375def WriteVST4R : SchedWrite;376def WriteVST8R : SchedWrite;377 378// 11. Vector Integer Arithmetic Instructions379// 11.1. Vector Single-Width Integer Add and Subtract380// 11.5. Vector Bitwise Logical Instructions381defm "" : LMULSchedWrites<"WriteVIALUV">;382defm "" : LMULSchedWrites<"WriteVIALUX">;383defm "" : LMULSchedWrites<"WriteVIALUI">;384// 11.2. Vector Widening Integer Add/Subtract385defm "" : LMULSchedWritesW<"WriteVIWALUV">;386defm "" : LMULSchedWritesW<"WriteVIWALUX">;387defm "" : LMULSchedWritesW<"WriteVIWALUI">;388// 11.3. Vector Integer Extension389defm "" : LMULSchedWrites<"WriteVExtV">;390// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions391defm "" : LMULSchedWrites<"WriteVICALUV">;392defm "" : LMULSchedWrites<"WriteVICALUX">;393defm "" : LMULSchedWrites<"WriteVICALUI">;394defm "" : LMULSchedWrites<"WriteVICALUMV">;395defm "" : LMULSchedWrites<"WriteVICALUMX">;396defm "" : LMULSchedWrites<"WriteVICALUMI">;397// 11.6. Vector Single-Width Bit Shift Instructions398defm "" : LMULSchedWrites<"WriteVShiftV">;399defm "" : LMULSchedWrites<"WriteVShiftX">;400defm "" : LMULSchedWrites<"WriteVShiftI">;401// 11.7. Vector Narrowing Integer Right Shift Instructions402defm "" : LMULSchedWritesW<"WriteVNShiftV">;403defm "" : LMULSchedWritesW<"WriteVNShiftX">;404defm "" : LMULSchedWritesW<"WriteVNShiftI">;405// 11.8. Vector Integer Comparison Instructions406defm "" : LMULSchedWrites<"WriteVICmpV">;407defm "" : LMULSchedWrites<"WriteVICmpX">;408defm "" : LMULSchedWrites<"WriteVICmpI">;409// 11.9. Vector Integer Min/Max Instructions410defm "" : LMULSchedWrites<"WriteVIMinMaxV">;411defm "" : LMULSchedWrites<"WriteVIMinMaxX">;412// 11.10. Vector Single-Width Integer Multiply Instructions413defm "" : LMULSchedWrites<"WriteVIMulV">;414defm "" : LMULSchedWrites<"WriteVIMulX">;415// 11.11. Vector Integer Divide Instructions416defm "" : LMULSEWSchedWrites<"WriteVIDivV">;417defm "" : LMULSEWSchedWrites<"WriteVIDivX">;418// 11.12. Vector Widening Integer Multiply Instructions419defm "" : LMULSchedWritesW<"WriteVIWMulV">;420defm "" : LMULSchedWritesW<"WriteVIWMulX">;421// 11.13. Vector Single-Width Integer Multiply-Add Instructions422defm "" : LMULSchedWrites<"WriteVIMulAddV">;423defm "" : LMULSchedWrites<"WriteVIMulAddX">;424// 11.14. Vector Widening Integer Multiply-Add Instructions425defm "" : LMULSchedWritesW<"WriteVIWMulAddV">;426defm "" : LMULSchedWritesW<"WriteVIWMulAddX">;427// 11.15. Vector Integer Merge Instructions428defm "" : LMULSchedWrites<"WriteVIMergeV">;429defm "" : LMULSchedWrites<"WriteVIMergeX">;430defm "" : LMULSchedWrites<"WriteVIMergeI">;431// 11.16. Vector Integer Move Instructions432defm "" : LMULSchedWrites<"WriteVIMovV">;433defm "" : LMULSchedWrites<"WriteVIMovX">;434defm "" : LMULSchedWrites<"WriteVIMovI">;435 436// 12. Vector Fixed-Point Arithmetic Instructions437// 12.1. Vector Single-Width Saturating Add and Subtract438defm "" : LMULSchedWrites<"WriteVSALUV">;439defm "" : LMULSchedWrites<"WriteVSALUX">;440defm "" : LMULSchedWrites<"WriteVSALUI">;441// 12.2. Vector Single-Width Averaging Add and Subtract442defm "" : LMULSchedWrites<"WriteVAALUV">;443defm "" : LMULSchedWrites<"WriteVAALUX">;444// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation445defm "" : LMULSchedWrites<"WriteVSMulV">;446defm "" : LMULSchedWrites<"WriteVSMulX">;447// 12.4. Vector Single-Width Scaling Shift Instructions448defm "" : LMULSchedWrites<"WriteVSShiftV">;449defm "" : LMULSchedWrites<"WriteVSShiftX">;450defm "" : LMULSchedWrites<"WriteVSShiftI">;451// 12.5. Vector Narrowing Fixed-Point Clip Instructions452defm "" : LMULSchedWritesW<"WriteVNClipV">;453defm "" : LMULSchedWritesW<"WriteVNClipX">;454defm "" : LMULSchedWritesW<"WriteVNClipI">;455 456// 13. Vector Floating-Point Instructions457// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions458defm "" : LMULSEWSchedWritesF<"WriteVFALUV">;459defm "" : LMULSEWSchedWritesF<"WriteVFALUF">;460// 13.3. Vector Widening Floating-Point Add/Subtract Instructions461defm "" : LMULSEWSchedWritesFW<"WriteVFWALUV">;462defm "" : LMULSEWSchedWritesFW<"WriteVFWALUF">;463// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions464defm "" : LMULSEWSchedWritesF<"WriteVFMulV">;465defm "" : LMULSEWSchedWritesF<"WriteVFMulF">;466defm "" : LMULSEWSchedWritesF<"WriteVFDivV">;467defm "" : LMULSEWSchedWritesF<"WriteVFDivF">;468// 13.5. Vector Widening Floating-Point Multiply469defm "" : LMULSEWSchedWritesFW<"WriteVFWMulV">;470defm "" : LMULSEWSchedWritesFW<"WriteVFWMulF">;471// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions472defm "" : LMULSEWSchedWritesF<"WriteVFMulAddV">;473defm "" : LMULSEWSchedWritesF<"WriteVFMulAddF">;474// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions475defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddV">;476defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddF">;477// 13.8. Vector Floating-Point Square-Root Instruction478defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">;479// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction480// 13.10. Vector Floating-Point Reciprocal Estimate Instruction481defm "" : LMULSEWSchedWritesF<"WriteVFRecpV">;482// 13.11. Vector Floating-Point MIN/MAX Instructions483defm "" : LMULSEWSchedWritesF<"WriteVFMinMaxV">;484defm "" : LMULSEWSchedWritesF<"WriteVFMinMaxF">;485// 13.12. Vector Floating-Point Sign-Injection Instructions486defm "" : LMULSEWSchedWritesF<"WriteVFSgnjV">;487defm "" : LMULSEWSchedWritesF<"WriteVFSgnjF">;488// 13.13. Vector Floating-Point Compare Instructions489defm "" : LMULSchedWrites<"WriteVFCmpV">;490defm "" : LMULSchedWrites<"WriteVFCmpF">;491// 13.14. Vector Floating-Point Classify Instruction492defm "" : LMULSchedWrites<"WriteVFClassV">;493// 13.15. Vector Floating-Point Merge Instruction494defm "" : LMULSchedWrites<"WriteVFMergeV">;495// 13.16. Vector Floating-Point Move Instruction496defm "" : LMULSchedWrites<"WriteVFMovV">;497// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions498defm "" : LMULSEWSchedWritesF<"WriteVFCvtIToFV">;499defm "" : LMULSchedWrites<"WriteVFCvtFToIV">;500// 13.18. Widening Floating-Point/Integer Type-Convert Instructions501defm "" : LMULSEWSchedWritesW<"WriteVFWCvtIToFV">;502defm "" : LMULSchedWritesFW<"WriteVFWCvtFToIV">;503defm "" : LMULSEWSchedWritesFW<"WriteVFWCvtFToFV">;504// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions505defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtIToFV">;506defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">;507defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtFToFV">;508 509// 14. Vector Reduction Operations510// The latency of reduction is determined by the size of the read resource.511// The LMUL range of read resource(VS2) for reduction operantion is between512// MF8 and M8. Use the _From suffix to indicate the number of the513// LMUL from VS2.514// 14.1. Vector Single-Width Integer Reduction Instructions515defm "" : LMULSEWSchedWrites<"WriteVIRedV_From">;516defm "" : LMULSEWSchedWrites<"WriteVIRedMinMaxV_From">;517// 14.2. Vector Widening Integer Reduction Instructions518defm "" : LMULSEWSchedWritesWRed<"WriteVIWRedV_From">;519// 14.3. Vector Single-Width Floating-Point Reduction Instructions520defm "" : LMULSEWSchedWritesF<"WriteVFRedV_From">;521defm "" : LMULSEWSchedWritesF<"WriteVFRedOV_From">;522defm "" : LMULSEWSchedWritesF<"WriteVFRedMinMaxV_From">;523// 14.4. Vector Widening Floating-Point Reduction Instructions524defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedV_From">;525defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedOV_From">;526 527// 15. Vector Mask Instructions528// 15.1. Vector Mask-Register Logical Instructions529defm "" : LMULSchedWrites<"WriteVMALUV">;530// 15.2. Vector Mask Population Count531defm "" : LMULSchedWrites<"WriteVMPopV">;532// 15.3. Vector Find-First-Set Mask Bit533defm "" : LMULSchedWrites<"WriteVMFFSV">;534// 15.4. Vector Set-Before-First Mask Bit535// 15.5. Vector Set-Including-First Mask Bit536// 15.6. Vector Set-only-First Mask Bit537defm "" : LMULSchedWrites<"WriteVMSFSV">;538// 15.8. Vector Iota Instruction539defm "" : LMULSchedWrites<"WriteVIotaV">;540// 15.9. Vector Element Index Instruction541defm "" : LMULSchedWrites<"WriteVIdxV">;542 543// 16. Vector Permutation Instructions544// 16.1. Integer Scalar Move Instructions545def WriteVMovSX : SchedWrite;546def WriteVMovXS : SchedWrite;547// 16.2. Floating-Point Scalar Move Instructions548def WriteVMovSF : SchedWrite;549def WriteVMovFS : SchedWrite;550// 16.3. Vector Slide Instructions551defm "" : LMULSchedWrites<"WriteVSlideUpX">;552defm "" : LMULSchedWrites<"WriteVSlideDownX">;553defm "" : LMULSchedWrites<"WriteVSlideI">;554defm "" : LMULSchedWrites<"WriteVISlide1X">;555defm "" : LMULSchedWrites<"WriteVFSlide1F">;556// 16.4. Vector Register Gather Instructions557defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;558defm "" : LMULSEWSchedWrites<"WriteVRGatherEI16VV">;559defm "" : LMULSchedWrites<"WriteVRGatherVX">;560defm "" : LMULSchedWrites<"WriteVRGatherVI">;561// 16.5. Vector Compress Instruction562defm "" : LMULSEWSchedWrites<"WriteVCompressV">;563// 16.6. Whole Vector Register Move564// These are already LMUL aware565def WriteVMov1V : SchedWrite;566def WriteVMov2V : SchedWrite;567def WriteVMov4V : SchedWrite;568def WriteVMov8V : SchedWrite;569 570//===----------------------------------------------------------------------===//571/// Define scheduler resources associated with use operands.572 573// 6. Configuration-Setting Instructions574def ReadVSETVLI : SchedRead;575def ReadVSETVL : SchedRead;576 577// 7. Vector Loads and Stores578def ReadVLDX : SchedRead;579def ReadVSTX : SchedRead;580// 7.4. Vector Unit-Stride Instructions581defm "" : LMULSchedReads<"ReadVSTEV">;582// 7.4.1. Vector Unit-Strided Mask583defm "" : LMULSchedReads<"ReadVSTM">;584// 7.5. Vector Strided Instructions585def ReadVLDSX : SchedRead;586def ReadVSTSX : SchedRead;587defm "" : LMULSchedReads<"ReadVSTS8V">;588defm "" : LMULSchedReads<"ReadVSTS16V">;589defm "" : LMULSchedReads<"ReadVSTS32V">;590defm "" : LMULSchedReads<"ReadVSTS64V">;591// 7.6. Vector Indexed Instructions592defm "" : LMULSchedReads<"ReadVLDUXV">;593defm "" : LMULSchedReads<"ReadVLDOXV">;594defm "" : LMULSchedReads<"ReadVSTUX8">;595defm "" : LMULSchedReads<"ReadVSTUX16">;596defm "" : LMULSchedReads<"ReadVSTUX32">;597defm "" : LMULSchedReads<"ReadVSTUX64">;598defm "" : LMULSchedReads<"ReadVSTUXV">;599defm "" : LMULSchedReads<"ReadVSTUX8V">;600defm "" : LMULSchedReads<"ReadVSTUX16V">;601defm "" : LMULSchedReads<"ReadVSTUX32V">;602defm "" : LMULSchedReads<"ReadVSTUX64V">;603defm "" : LMULSchedReads<"ReadVSTOX8">;604defm "" : LMULSchedReads<"ReadVSTOX16">;605defm "" : LMULSchedReads<"ReadVSTOX32">;606defm "" : LMULSchedReads<"ReadVSTOX64">;607defm "" : LMULSchedReads<"ReadVSTOXV">;608defm "" : LMULSchedReads<"ReadVSTOX8V">;609defm "" : LMULSchedReads<"ReadVSTOX16V">;610defm "" : LMULSchedReads<"ReadVSTOX32V">;611defm "" : LMULSchedReads<"ReadVSTOX64V">;612// 7.9. Vector Whole Register Instructions613// These are already LMUL aware614def ReadVST1R : SchedRead;615def ReadVST2R : SchedRead;616def ReadVST4R : SchedRead;617def ReadVST8R : SchedRead;618 619// 11. Vector Integer Arithmetic Instructions620// 11.1. Vector Single-Width Integer Add and Subtract621// 11.5. Vector Bitwise Logical Instructions622defm "" : LMULSchedReads<"ReadVIALUV">;623defm "" : LMULSchedReads<"ReadVIALUX">;624// 11.2. Vector Widening Integer Add/Subtract625defm "" : LMULSchedReadsW<"ReadVIWALUV">;626defm "" : LMULSchedReadsW<"ReadVIWALUX">;627// 11.3. Vector Integer Extension628defm "" : LMULSchedReads<"ReadVExtV">;629// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions630defm "" : LMULSchedReads<"ReadVICALUV">;631defm "" : LMULSchedReads<"ReadVICALUX">;632// 11.6. Vector Single-Width Bit Shift Instructions633defm "" : LMULSchedReads<"ReadVShiftV">;634defm "" : LMULSchedReads<"ReadVShiftX">;635// 11.7. Vector Narrowing Integer Right Shift Instructions636defm "" : LMULSchedReadsW<"ReadVNShiftV">;637defm "" : LMULSchedReadsW<"ReadVNShiftX">;638// 11.8. Vector Integer Comparison Instructions639defm "" : LMULSchedReads<"ReadVICmpV">;640defm "" : LMULSchedReads<"ReadVICmpX">;641// 11.9. Vector Integer Min/Max Instructions642defm "" : LMULSchedReads<"ReadVIMinMaxV">;643defm "" : LMULSchedReads<"ReadVIMinMaxX">;644// 11.10. Vector Single-Width Integer Multiply Instructions645defm "" : LMULSchedReads<"ReadVIMulV">;646defm "" : LMULSchedReads<"ReadVIMulX">;647// 11.11. Vector Integer Divide Instructions648defm "" : LMULSEWSchedReads<"ReadVIDivV">;649defm "" : LMULSEWSchedReads<"ReadVIDivX">;650// 11.12. Vector Widening Integer Multiply Instructions651defm "" : LMULSchedReadsW<"ReadVIWMulV">;652defm "" : LMULSchedReadsW<"ReadVIWMulX">;653// 11.13. Vector Single-Width Integer Multiply-Add Instructions654defm "" : LMULSchedReads<"ReadVIMulAddV">;655defm "" : LMULSchedReads<"ReadVIMulAddX">;656// 11.14. Vector Widening Integer Multiply-Add Instructions657defm "" : LMULSchedReadsW<"ReadVIWMulAddV">;658defm "" : LMULSchedReadsW<"ReadVIWMulAddX">;659// 11.15. Vector Integer Merge Instructions660defm "" : LMULSchedReads<"ReadVIMergeV">;661defm "" : LMULSchedReads<"ReadVIMergeX">;662// 11.16. Vector Integer Move Instructions663defm "" : LMULSchedReads<"ReadVIMovV">;664defm "" : LMULSchedReads<"ReadVIMovX">;665 666// 12. Vector Fixed-Point Arithmetic Instructions667// 12.1. Vector Single-Width Saturating Add and Subtract668defm "" : LMULSchedReads<"ReadVSALUV">;669defm "" : LMULSchedReads<"ReadVSALUX">;670// 12.2. Vector Single-Width Averaging Add and Subtract671defm "" : LMULSchedReads<"ReadVAALUV">;672defm "" : LMULSchedReads<"ReadVAALUX">;673// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation674defm "" : LMULSchedReads<"ReadVSMulV">;675defm "" : LMULSchedReads<"ReadVSMulX">;676// 12.4. Vector Single-Width Scaling Shift Instructions677defm "" : LMULSchedReads<"ReadVSShiftV">;678defm "" : LMULSchedReads<"ReadVSShiftX">;679// 12.5. Vector Narrowing Fixed-Point Clip Instructions680defm "" : LMULSchedReadsW<"ReadVNClipV">;681defm "" : LMULSchedReadsW<"ReadVNClipX">;682 683// 13. Vector Floating-Point Instructions684// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions685defm "" : LMULSEWSchedReadsF<"ReadVFALUV">;686defm "" : LMULSEWSchedReadsF<"ReadVFALUF">;687// 13.3. Vector Widening Floating-Point Add/Subtract Instructions688defm "" : LMULSEWSchedReadsFW<"ReadVFWALUV">;689defm "" : LMULSEWSchedReadsFW<"ReadVFWALUF">;690// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions691defm "" : LMULSEWSchedReadsF<"ReadVFMulV">;692defm "" : LMULSEWSchedReadsF<"ReadVFMulF">;693defm "" : LMULSEWSchedReadsF<"ReadVFDivV">;694defm "" : LMULSEWSchedReadsF<"ReadVFDivF">;695// 13.5. Vector Widening Floating-Point Multiply696defm "" : LMULSEWSchedReadsFW<"ReadVFWMulV">;697defm "" : LMULSEWSchedReadsFW<"ReadVFWMulF">;698// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions699defm "" : LMULSEWSchedReadsF<"ReadVFMulAddV">;700defm "" : LMULSEWSchedReadsF<"ReadVFMulAddF">;701// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions702defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddV">;703defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddF">;704// 13.8. Vector Floating-Point Square-Root Instruction705defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">;706// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction707// 13.10. Vector Floating-Point Reciprocal Estimate Instruction708defm "" : LMULSEWSchedReadsF<"ReadVFRecpV">;709// 13.11. Vector Floating-Point MIN/MAX Instructions710defm "" : LMULSEWSchedReadsF<"ReadVFMinMaxV">;711defm "" : LMULSEWSchedReadsF<"ReadVFMinMaxF">;712// 13.12. Vector Floating-Point Sign-Injection Instructions713defm "" : LMULSEWSchedReadsF<"ReadVFSgnjV">;714defm "" : LMULSEWSchedReadsF<"ReadVFSgnjF">;715// 13.13. Vector Floating-Point Compare Instructions716defm "" : LMULSchedReads<"ReadVFCmpV">;717defm "" : LMULSchedReads<"ReadVFCmpF">;718// 13.14. Vector Floating-Point Classify Instruction719defm "" : LMULSchedReads<"ReadVFClassV">;720// 13.15. Vector Floating-Point Merge Instruction721defm "" : LMULSchedReads<"ReadVFMergeV">;722defm "" : LMULSchedReads<"ReadVFMergeF">;723// 13.16. Vector Floating-Point Move Instruction724defm "" : LMULSchedReads<"ReadVFMovF">;725// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions726defm "" : LMULSEWSchedReadsF<"ReadVFCvtIToFV">;727defm "" : LMULSchedReads<"ReadVFCvtFToIV">;728// 13.18. Widening Floating-Point/Integer Type-Convert Instructions729defm "" : LMULSEWSchedReadsW<"ReadVFWCvtIToFV">;730defm "" : LMULSchedReadsFW<"ReadVFWCvtFToIV">;731defm "" : LMULSEWSchedReadsFW<"ReadVFWCvtFToFV">;732// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions733defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtIToFV">;734defm "" : LMULSchedReadsW<"ReadVFNCvtFToIV">;735defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtFToFV">;736 737// 14. Vector Reduction Operations738// 14.1. Vector Single-Width Integer Reduction Instructions739def ReadVIRedV : SchedRead;740def ReadVIRedV0 : SchedRead;741// 14.2. Vector Widening Integer Reduction Instructions742def ReadVIWRedV : SchedRead;743def ReadVIWRedV0 : SchedRead;744// 14.3. Vector Single-Width Floating-Point Reduction Instructions745def ReadVFRedV : SchedRead;746def ReadVFRedV0 : SchedRead;747def ReadVFRedOV : SchedRead;748def ReadVFRedOV0 : SchedRead;749def ReadVFRedMinMaxV : SchedRead;750// 14.4. Vector Widening Floating-Point Reduction Instructions751def ReadVFWRedV : SchedRead;752def ReadVFWRedV0 : SchedRead;753def ReadVFWRedOV : SchedRead;754def ReadVFWRedOV0 : SchedRead;755 756// 15. Vector Mask Instructions757// 15.1. Vector Mask-Register Logical Instructions758defm "" : LMULSchedReads<"ReadVMALUV">;759// 15.2. Vector Mask Population Count760defm "" : LMULSchedReads<"ReadVMPopV">;761// 15.3. Vector Find-First-Set Mask Bit762defm "" : LMULSchedReads<"ReadVMFFSV">;763// 15.4. Vector Set-Before-First Mask Bit764// 15.5. Vector Set-Including-First Mask Bit765// 15.6. Vector Set-only-First Mask Bit766defm "" : LMULSchedReads<"ReadVMSFSV">;767// 15.8. Vector Iota Instruction768defm "" : LMULSchedReads<"ReadVIotaV">;769 770// 16. Vector Permutation Instructions771// 16.1. Integer Scalar Move Instructions772def ReadVMovXS : SchedRead;773def ReadVMovSX_V : SchedRead;774def ReadVMovSX_X : SchedRead;775// 16.2. Floating-Point Scalar Move Instructions776def ReadVMovFS : SchedRead;777def ReadVMovSF_V : SchedRead;778def ReadVMovSF_F : SchedRead;779// 16.3. Vector Slide Instructions780defm "" : LMULSchedReads<"ReadVISlideV">;781defm "" : LMULSchedReads<"ReadVISlideX">;782defm "" : LMULSchedReads<"ReadVFSlideV">;783defm "" : LMULSchedReads<"ReadVFSlideF">;784// 16.4. Vector Register Gather Instructions785defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">;786defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">;787defm "" : LMULSEWSchedReads<"ReadVRGatherEI16VV_data">;788defm "" : LMULSEWSchedReads<"ReadVRGatherEI16VV_index">;789defm "" : LMULSchedReads<"ReadVRGatherVX_data">;790defm "" : LMULSchedReads<"ReadVRGatherVX_index">;791defm "" : LMULSchedReads<"ReadVRGatherVI_data">;792// 16.5. Vector Compress Instruction793defm "" : LMULSEWSchedReads<"ReadVCompressV">;794// 16.6. Whole Vector Register Move795// These are already LMUL aware796def ReadVMov1V : SchedRead;797def ReadVMov2V : SchedRead;798def ReadVMov4V : SchedRead;799def ReadVMov8V : SchedRead;800 801// Others802def ReadVMask : SchedRead;803def ReadVPassthru_WorstCase : SchedRead;804foreach mx = SchedMxList in {805 def ReadVPassthru_ # mx : SchedRead;806 foreach sew = SchedSEWSet<mx>.val in807 def ReadVPassthru_ # mx # "_E" # sew : SchedRead;808}809 810//===----------------------------------------------------------------------===//811/// Define default scheduler resources for V.812 813multiclass UnsupportedSchedV {814let Unsupported = true in {815 816// 3.6 Vector Byte Length vlenb817def : WriteRes<WriteRdVLENB, []>;818 819// 6. Configuration-Setting Instructions820def : WriteRes<WriteVSETVLI, []>;821def : WriteRes<WriteVSETIVLI, []>;822def : WriteRes<WriteVSETVL, []>;823 824// 7. Vector Loads and Stores825defm "" : LMULWriteRes<"WriteVLDE", []>;826defm "" : LMULWriteRes<"WriteVSTE", []>;827defm "" : LMULWriteRes<"WriteVLDM", []>;828defm "" : LMULWriteRes<"WriteVSTM", []>;829defm "" : LMULWriteRes<"WriteVLDS8", []>;830defm "" : LMULWriteRes<"WriteVLDS16", []>;831defm "" : LMULWriteRes<"WriteVLDS32", []>;832defm "" : LMULWriteRes<"WriteVLDS64", []>;833defm "" : LMULWriteRes<"WriteVSTS8", []>;834defm "" : LMULWriteRes<"WriteVSTS16", []>;835defm "" : LMULWriteRes<"WriteVSTS32", []>;836defm "" : LMULWriteRes<"WriteVSTS64", []>;837defm "" : LMULWriteRes<"WriteVLDUX8", []>;838defm "" : LMULWriteRes<"WriteVLDUX16", []>;839defm "" : LMULWriteRes<"WriteVLDUX32", []>;840defm "" : LMULWriteRes<"WriteVLDUX64", []>;841defm "" : LMULWriteRes<"WriteVLDOX8", []>;842defm "" : LMULWriteRes<"WriteVLDOX16", []>;843defm "" : LMULWriteRes<"WriteVLDOX32", []>;844defm "" : LMULWriteRes<"WriteVLDOX64", []>;845defm "" : LMULWriteRes<"WriteVSTUX8", []>;846defm "" : LMULWriteRes<"WriteVSTUX16", []>;847defm "" : LMULWriteRes<"WriteVSTUX32", []>;848defm "" : LMULWriteRes<"WriteVSTUX64", []>;849defm "" : LMULWriteRes<"WriteVSTOX8", []>;850defm "" : LMULWriteRes<"WriteVSTOX16", []>;851defm "" : LMULWriteRes<"WriteVSTOX32", []>;852defm "" : LMULWriteRes<"WriteVSTOX64", []>;853defm "" : LMULWriteRes<"WriteVLDFF", []>;854// These are already LMUL aware855def : WriteRes<WriteVLD1R, []>;856def : WriteRes<WriteVLD2R, []>;857def : WriteRes<WriteVLD4R, []>;858def : WriteRes<WriteVLD8R, []>;859def : WriteRes<WriteVST1R, []>;860def : WriteRes<WriteVST2R, []>;861def : WriteRes<WriteVST4R, []>;862def : WriteRes<WriteVST8R, []>;863// Vector Segment Loads and Stores864foreach nf=2-8 in {865 foreach eew = [8, 16, 32, 64] in {866 defm "" : LMULWriteRes <"WriteVLSEG" # nf # "e" # eew, []>;867 defm "" : LMULWriteRes <"WriteVLSEGFF" # nf # "e" # eew, []>;868 defm "" : LMULWriteRes <"WriteVSSEG" # nf # "e" # eew, []>;869 defm "" : LMULWriteRes <"WriteVLSSEG" # nf # "e" # eew, []>;870 defm "" : LMULWriteRes <"WriteVSSSEG" # nf # "e" # eew, []>;871 defm "" : LMULWriteRes <"WriteVLUXSEG" # nf # "e" # eew, []>;872 defm "" : LMULWriteRes <"WriteVLOXSEG" # nf # "e" # eew, []>;873 defm "" : LMULWriteRes <"WriteVSUXSEG" # nf # "e" # eew, []>;874 defm "" : LMULWriteRes <"WriteVSOXSEG" # nf # "e" # eew, []>;875 }876}877 878// 11. Vector Integer Arithmetic Instructions879defm "" : LMULWriteRes<"WriteVIALUV", []>;880defm "" : LMULWriteRes<"WriteVIALUX", []>;881defm "" : LMULWriteRes<"WriteVIALUI", []>;882defm "" : LMULWriteResW<"WriteVIWALUV", []>;883defm "" : LMULWriteResW<"WriteVIWALUX", []>;884defm "" : LMULWriteResW<"WriteVIWALUI", []>;885defm "" : LMULWriteRes<"WriteVExtV", []>;886defm "" : LMULWriteRes<"WriteVICALUV", []>;887defm "" : LMULWriteRes<"WriteVICALUX", []>;888defm "" : LMULWriteRes<"WriteVICALUI", []>;889defm "" : LMULWriteRes<"WriteVICALUMV", []>;890defm "" : LMULWriteRes<"WriteVICALUMX", []>;891defm "" : LMULWriteRes<"WriteVICALUMI", []>;892defm "" : LMULWriteRes<"WriteVShiftV", []>;893defm "" : LMULWriteRes<"WriteVShiftX", []>;894defm "" : LMULWriteRes<"WriteVShiftI", []>;895defm "" : LMULWriteResW<"WriteVNShiftV", []>;896defm "" : LMULWriteResW<"WriteVNShiftX", []>;897defm "" : LMULWriteResW<"WriteVNShiftI", []>;898defm "" : LMULWriteRes<"WriteVICmpV", []>;899defm "" : LMULWriteRes<"WriteVICmpX", []>;900defm "" : LMULWriteRes<"WriteVICmpI", []>;901defm "" : LMULWriteRes<"WriteVIMinMaxV", []>;902defm "" : LMULWriteRes<"WriteVIMinMaxX", []>;903defm "" : LMULWriteRes<"WriteVIMulV", []>;904defm "" : LMULWriteRes<"WriteVIMulX", []>;905defm "" : LMULSEWWriteRes<"WriteVIDivV", []>;906defm "" : LMULSEWWriteRes<"WriteVIDivX", []>;907defm "" : LMULWriteResW<"WriteVIWMulV", []>;908defm "" : LMULWriteResW<"WriteVIWMulX", []>;909defm "" : LMULWriteRes<"WriteVIMulAddV", []>;910defm "" : LMULWriteRes<"WriteVIMulAddX", []>;911defm "" : LMULWriteResW<"WriteVIWMulAddV", []>;912defm "" : LMULWriteResW<"WriteVIWMulAddX", []>;913defm "" : LMULWriteRes<"WriteVIMergeV", []>;914defm "" : LMULWriteRes<"WriteVIMergeX", []>;915defm "" : LMULWriteRes<"WriteVIMergeI", []>;916defm "" : LMULWriteRes<"WriteVIMovV", []>;917defm "" : LMULWriteRes<"WriteVIMovX", []>;918defm "" : LMULWriteRes<"WriteVIMovI", []>;919 920// 12. Vector Fixed-Point Arithmetic Instructions921defm "" : LMULWriteRes<"WriteVSALUV", []>;922defm "" : LMULWriteRes<"WriteVSALUX", []>;923defm "" : LMULWriteRes<"WriteVSALUI", []>;924defm "" : LMULWriteRes<"WriteVAALUV", []>;925defm "" : LMULWriteRes<"WriteVAALUX", []>;926defm "" : LMULWriteRes<"WriteVSMulV", []>;927defm "" : LMULWriteRes<"WriteVSMulX", []>;928defm "" : LMULWriteRes<"WriteVSShiftV", []>;929defm "" : LMULWriteRes<"WriteVSShiftX", []>;930defm "" : LMULWriteRes<"WriteVSShiftI", []>;931defm "" : LMULWriteResW<"WriteVNClipV", []>;932defm "" : LMULWriteResW<"WriteVNClipX", []>;933defm "" : LMULWriteResW<"WriteVNClipI", []>;934 935// 13. Vector Floating-Point Instructions936defm "" : LMULSEWWriteResF<"WriteVFALUV", []>;937defm "" : LMULSEWWriteResF<"WriteVFALUF", []>;938defm "" : LMULSEWWriteResFW<"WriteVFWALUV", []>;939defm "" : LMULSEWWriteResFW<"WriteVFWALUF", []>;940defm "" : LMULSEWWriteResF<"WriteVFMulV", []>;941defm "" : LMULSEWWriteResF<"WriteVFMulF", []>;942defm "" : LMULSEWWriteResF<"WriteVFDivV", []>;943defm "" : LMULSEWWriteResF<"WriteVFDivF", []>;944defm "" : LMULSEWWriteResFW<"WriteVFWMulV", []>;945defm "" : LMULSEWWriteResFW<"WriteVFWMulF", []>;946defm "" : LMULSEWWriteResF<"WriteVFMulAddV", []>;947defm "" : LMULSEWWriteResF<"WriteVFMulAddF", []>;948defm "" : LMULSEWWriteResFW<"WriteVFWMulAddV", []>;949defm "" : LMULSEWWriteResFW<"WriteVFWMulAddF", []>;950defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>;951defm "" : LMULSEWWriteResF<"WriteVFRecpV", []>;952defm "" : LMULSEWWriteResF<"WriteVFMinMaxV", []>;953defm "" : LMULSEWWriteResF<"WriteVFMinMaxF", []>;954defm "" : LMULSEWWriteResF<"WriteVFSgnjV", []>;955defm "" : LMULSEWWriteResF<"WriteVFSgnjF", []>;956defm "" : LMULWriteRes<"WriteVFCmpV", []>;957defm "" : LMULWriteRes<"WriteVFCmpF", []>;958defm "" : LMULWriteRes<"WriteVFClassV", []>;959defm "" : LMULWriteRes<"WriteVFMergeV", []>;960defm "" : LMULWriteRes<"WriteVFMovV", []>;961defm "" : LMULSEWWriteResF<"WriteVFCvtIToFV", []>;962defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>;963defm "" : LMULSEWWriteResW<"WriteVFWCvtIToFV", []>;964defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>;965defm "" : LMULSEWWriteResFW<"WriteVFWCvtFToFV", []>;966defm "" : LMULSEWWriteResFW<"WriteVFNCvtIToFV", []>;967defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>;968defm "" : LMULSEWWriteResFW<"WriteVFNCvtFToFV", []>;969 970// 14. Vector Reduction Operations971defm "" : LMULSEWWriteRes<"WriteVIRedV_From", []>;972defm "" : LMULSEWWriteRes<"WriteVIRedMinMaxV_From", []>;973defm "" : LMULSEWWriteResWRed<"WriteVIWRedV_From", []>;974defm "" : LMULSEWWriteResF<"WriteVFRedV_From", []>;975defm "" : LMULSEWWriteResF<"WriteVFRedOV_From", []>;976defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>;977defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", []>;978defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>;979 980// 15. Vector Mask Instructions981defm "" : LMULWriteRes<"WriteVMALUV", []>;982defm "" : LMULWriteRes<"WriteVMPopV", []>;983defm "" : LMULWriteRes<"WriteVMFFSV", []>;984defm "" : LMULWriteRes<"WriteVMSFSV", []>;985defm "" : LMULWriteRes<"WriteVIotaV", []>;986defm "" : LMULWriteRes<"WriteVIdxV", []>;987 988// 16. Vector Permutation Instructions989def : WriteRes<WriteVMovSX, []>;990def : WriteRes<WriteVMovXS, []>;991def : WriteRes<WriteVMovSF, []>;992def : WriteRes<WriteVMovFS, []>;993defm "" : LMULWriteRes<"WriteVSlideUpX", []>;994defm "" : LMULWriteRes<"WriteVSlideDownX", []>;995defm "" : LMULWriteRes<"WriteVSlideI", []>;996defm "" : LMULWriteRes<"WriteVISlide1X", []>;997defm "" : LMULWriteRes<"WriteVFSlide1F", []>;998defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;999defm "" : LMULSEWWriteRes<"WriteVRGatherEI16VV", []>;1000defm "" : LMULWriteRes<"WriteVRGatherVX", []>;1001defm "" : LMULWriteRes<"WriteVRGatherVI", []>;1002defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;1003// These are already LMUL aware1004def : WriteRes<WriteVMov1V, []>;1005def : WriteRes<WriteVMov2V, []>;1006def : WriteRes<WriteVMov4V, []>;1007def : WriteRes<WriteVMov8V, []>;1008 1009// 6. Configuration-Setting Instructions1010def : ReadAdvance<ReadVSETVLI, 0>;1011def : ReadAdvance<ReadVSETVL, 0>;1012 1013// 7. Vector Loads and Stores1014def : ReadAdvance<ReadVLDX, 0>;1015def : ReadAdvance<ReadVSTX, 0>;1016defm "" : LMULReadAdvance<"ReadVSTEV", 0>;1017defm "" : LMULReadAdvance<"ReadVSTM", 0>;1018def : ReadAdvance<ReadVLDSX, 0>;1019def : ReadAdvance<ReadVSTSX, 0>;1020defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;1021defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;1022defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;1023defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;1024defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;1025defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;1026defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;1027defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;1028defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;1029defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;1030defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;1031defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;1032defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;1033defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;1034defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;1035defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;1036defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;1037defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;1038defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;1039defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;1040defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;1041defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;1042defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;1043defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;1044// These are already LMUL aware1045def : ReadAdvance<ReadVST1R, 0>;1046def : ReadAdvance<ReadVST2R, 0>;1047def : ReadAdvance<ReadVST4R, 0>;1048def : ReadAdvance<ReadVST8R, 0>;1049 1050// 11. Vector Integer Arithmetic Instructions1051defm "" : LMULReadAdvance<"ReadVIALUV", 0>;1052defm "" : LMULReadAdvance<"ReadVIALUX", 0>;1053defm "" : LMULReadAdvanceW<"ReadVIWALUV", 0>;1054defm "" : LMULReadAdvanceW<"ReadVIWALUX", 0>;1055defm "" : LMULReadAdvance<"ReadVExtV", 0>;1056defm "" : LMULReadAdvance<"ReadVICALUV", 0>;1057defm "" : LMULReadAdvance<"ReadVICALUX", 0>;1058defm "" : LMULReadAdvance<"ReadVShiftV", 0>;1059defm "" : LMULReadAdvance<"ReadVShiftX", 0>;1060defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>;1061defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>;1062defm "" : LMULReadAdvance<"ReadVICmpV", 0>;1063defm "" : LMULReadAdvance<"ReadVICmpX", 0>;1064defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>;1065defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>;1066defm "" : LMULReadAdvance<"ReadVIMulV", 0>;1067defm "" : LMULReadAdvance<"ReadVIMulX", 0>;1068defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>;1069defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>;1070defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>;1071defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>;1072defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;1073defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>;1074defm "" : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;1075defm "" : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;1076defm "" : LMULReadAdvance<"ReadVIMergeV", 0>;1077defm "" : LMULReadAdvance<"ReadVIMergeX", 0>;1078defm "" : LMULReadAdvance<"ReadVIMovV", 0>;1079defm "" : LMULReadAdvance<"ReadVIMovX", 0>;1080 1081// 12. Vector Fixed-Point Arithmetic Instructions1082defm "" : LMULReadAdvance<"ReadVSALUV", 0>;1083defm "" : LMULReadAdvance<"ReadVSALUX", 0>;1084defm "" : LMULReadAdvance<"ReadVAALUV", 0>;1085defm "" : LMULReadAdvance<"ReadVAALUX", 0>;1086defm "" : LMULReadAdvance<"ReadVSMulV", 0>;1087defm "" : LMULReadAdvance<"ReadVSMulX", 0>;1088defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;1089defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;1090defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;1091defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;1092 1093// 13. Vector Floating-Point Instructions1094defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;1095defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;1096defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;1097defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;1098defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;1099defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;1100defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;1101defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;1102defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;1103defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;1104defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;1105defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;1106defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;1107defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;1108defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;1109defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;1110defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;1111defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;1112defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;1113defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;1114defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;1115defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;1116defm "" : LMULReadAdvance<"ReadVFClassV", 0>;1117defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;1118defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;1119defm "" : LMULReadAdvance<"ReadVFMovF", 0>;1120defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;1121defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;1122defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;1123defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;1124defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;1125defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;1126defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;1127defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;1128 1129// 14. Vector Reduction Operations1130def : ReadAdvance<ReadVIRedV, 0>;1131def : ReadAdvance<ReadVIRedV0, 0>;1132def : ReadAdvance<ReadVIWRedV, 0>;1133def : ReadAdvance<ReadVIWRedV0, 0>;1134def : ReadAdvance<ReadVFRedV, 0>;1135def : ReadAdvance<ReadVFRedV0, 0>;1136def : ReadAdvance<ReadVFRedOV, 0>;1137def : ReadAdvance<ReadVFRedOV0, 0>;1138def : ReadAdvance<ReadVFRedMinMaxV, 0>;1139def : ReadAdvance<ReadVFWRedV, 0>;1140def : ReadAdvance<ReadVFWRedV0, 0>;1141def : ReadAdvance<ReadVFWRedOV, 0>;1142def : ReadAdvance<ReadVFWRedOV0, 0>;1143 1144// 15. Vector Mask Instructions1145defm "" : LMULReadAdvance<"ReadVMALUV", 0>;1146defm "" : LMULReadAdvance<"ReadVMPopV", 0>;1147defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;1148defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;1149defm "" : LMULReadAdvance<"ReadVIotaV", 0>;1150 1151// 16. Vector Permutation Instructions1152def : ReadAdvance<ReadVMovXS, 0>;1153def : ReadAdvance<ReadVMovSX_V, 0>;1154def : ReadAdvance<ReadVMovSX_X, 0>;1155def : ReadAdvance<ReadVMovFS, 0>;1156def : ReadAdvance<ReadVMovSF_V, 0>;1157def : ReadAdvance<ReadVMovSF_F, 0>;1158defm "" : LMULReadAdvance<"ReadVISlideV", 0>;1159defm "" : LMULReadAdvance<"ReadVISlideX", 0>;1160defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;1161defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;1162defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;1163defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;1164defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;1165defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;1166defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;1167defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;1168defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;1169defm "" : LMULReadAdvance<"ReadVGatherV", 0>;1170defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;1171// These are already LMUL aware1172def : ReadAdvance<ReadVMov1V, 0>;1173def : ReadAdvance<ReadVMov2V, 0>;1174def : ReadAdvance<ReadVMov4V, 0>;1175def : ReadAdvance<ReadVMov8V, 0>;1176 1177// Others1178def : ReadAdvance<ReadVMask, 0>;1179def : ReadAdvance<ReadVPassthru_WorstCase, 0>;1180foreach mx = SchedMxList in {1181 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;1182 foreach sew = SchedSEWSet<mx>.val in1183 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;1184}1185 1186} // Unsupported1187} // UnsupportedSchedV1188