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1//=== RISCVScheduleZvk.td - RISC-V Scheduling Definitions Zvk -*- tablegen ===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9/// Define scheduler resources associated with def operands.10 11/// Zvbb extension12defm "" : LMULSchedWrites<"WriteVBREVV">;13defm "" : LMULSchedWrites<"WriteVCLZV">;14defm "" : LMULSchedWrites<"WriteVCPOPV">;15defm "" : LMULSchedWrites<"WriteVCTZV">;16defm "" : LMULSchedWrites<"WriteVWSLLV">;17defm "" : LMULSchedWrites<"WriteVWSLLX">;18defm "" : LMULSchedWrites<"WriteVWSLLI">;19 20/// Zvbc extension21defm "" : LMULSchedWrites<"WriteVCLMULV">;22defm "" : LMULSchedWrites<"WriteVCLMULX">;23 24/// Zvkb extension25// VANDN uses WriteVIALU[V|X|I]26defm "" : LMULSchedWrites<"WriteVBREV8V">;27defm "" : LMULSchedWrites<"WriteVREV8V">;28defm "" : LMULSchedWrites<"WriteVRotV">;29defm "" : LMULSchedWrites<"WriteVRotX">;30defm "" : LMULSchedWrites<"WriteVRotI">;31 32/// Zvkg extension33defm "" : LMULSchedWrites<"WriteVGHSHV">;34defm "" : LMULSchedWrites<"WriteVGMULV">;35 36/// Zvknha or Zvknhb extensions37defm "" : LMULSchedWrites<"WriteVSHA2CHV">;38defm "" : LMULSchedWrites<"WriteVSHA2CLV">;39defm "" : LMULSEWSchedWrites<"WriteVSHA2MSV">;40 41/// Zvkned extension42defm "" : LMULSchedWrites<"WriteVAESMVV">;43defm "" : LMULSchedWrites<"WriteVAESKF1V">;44defm "" : LMULSchedWrites<"WriteVAESKF2V">;45defm "" : LMULSchedWrites<"WriteVAESZV">;46 47/// Zvksed extension48defm "" : LMULSchedWrites<"WriteVSM4KV">;49defm "" : LMULSchedWrites<"WriteVSM4RV">;50 51/// Zvksh extension52defm "" : LMULSchedWrites<"WriteVSM3CV">;53defm "" : LMULSchedWrites<"WriteVSM3MEV">;54 55/// Define scheduler resources associated with use operands.56/// Zvbb extension57defm "" : LMULSchedReads<"ReadVBREVV">;58defm "" : LMULSchedReads<"ReadVCLZV">;59defm "" : LMULSchedReads<"ReadVCPOPV">;60defm "" : LMULSchedReads<"ReadVCTZV">;61defm "" : LMULSchedReads<"ReadVWSLLV">;62defm "" : LMULSchedReads<"ReadVWSLLX">;63 64/// Zvbc extension65defm "" : LMULSchedReads<"ReadVCLMULV">;66defm "" : LMULSchedReads<"ReadVCLMULX">;67 68/// Zvkb extension69// VANDN uses ReadVIALU[V|X|I]70defm "" : LMULSchedReads<"ReadVBREV8V">;71defm "" : LMULSchedReads<"ReadVREV8V">;72defm "" : LMULSchedReads<"ReadVRotV">;73defm "" : LMULSchedReads<"ReadVRotX">;74 75/// Zvkg extension76defm "" : LMULSchedReads<"ReadVGHSHV">;77defm "" : LMULSchedReads<"ReadVGMULV">;78 79/// Zvknha or Zvknhb extensions80defm "" : LMULSchedReads<"ReadVSHA2CHV">;81defm "" : LMULSchedReads<"ReadVSHA2CLV">;82defm "" : LMULSEWSchedReads<"ReadVSHA2MSV">;83 84/// Zvkned extension85defm "" : LMULSchedReads<"ReadVAESMVV">;86defm "" : LMULSchedReads<"ReadVAESKF1V">;87defm "" : LMULSchedReads<"ReadVAESKF2V">;88defm "" : LMULSchedReads<"ReadVAESZV">;89 90/// Zvksed extension91defm "" : LMULSchedReads<"ReadVSM4KV">;92defm "" : LMULSchedReads<"ReadVSM4RV">;93 94/// Zvksh extension95defm "" : LMULSchedReads<"ReadVSM3CV">;96defm "" : LMULSchedReads<"ReadVSM3MEV">;97 98multiclass UnsupportedSchedZvbb {99let Unsupported = true in {100defm "" : LMULWriteRes<"WriteVBREVV", []>;101defm "" : LMULWriteRes<"WriteVCLZV", []>;102defm "" : LMULWriteRes<"WriteVCPOPV", []>;103defm "" : LMULWriteRes<"WriteVCTZV", []>;104defm "" : LMULWriteRes<"WriteVWSLLV", []>;105defm "" : LMULWriteRes<"WriteVWSLLX", []>;106defm "" : LMULWriteRes<"WriteVWSLLI", []>;107 108defm "" : LMULReadAdvance<"ReadVBREVV", 0>;109defm "" : LMULReadAdvance<"ReadVCLZV", 0>;110defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;111defm "" : LMULReadAdvance<"ReadVCTZV", 0>;112defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;113defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;114}115}116 117multiclass UnsupportedSchedZvbc {118let Unsupported = true in {119defm "" : LMULWriteRes<"WriteVCLMULV", []>;120defm "" : LMULWriteRes<"WriteVCLMULX", []>;121 122defm "" : LMULReadAdvance<"ReadVCLMULV", 0>; 123defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;124}125}126 127multiclass UnsupportedSchedZvkb {128let Unsupported = true in {129defm "" : LMULWriteRes<"WriteVBREV8V", []>;130defm "" : LMULWriteRes<"WriteVREV8V", []>;131defm "" : LMULWriteRes<"WriteVRotV", []>;132defm "" : LMULWriteRes<"WriteVRotX", []>;133defm "" : LMULWriteRes<"WriteVRotI", []>;134 135defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;136defm "" : LMULReadAdvance<"ReadVREV8V", 0>;137defm "" : LMULReadAdvance<"ReadVRotV", 0>;138defm "" : LMULReadAdvance<"ReadVRotX", 0>;139}140}141 142multiclass UnsupportedSchedZvkg {143let Unsupported = true in {144defm "" : LMULWriteRes<"WriteVGHSHV", []>;145defm "" : LMULWriteRes<"WriteVGMULV", []>;146 147defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;148defm "" : LMULReadAdvance<"ReadVGMULV", 0>;149}150}151 152multiclass UnsupportedSchedZvknhaOrZvknhb {153let Unsupported = true in {154defm "" : LMULWriteRes<"WriteVSHA2CHV", []>;155defm "" : LMULWriteRes<"WriteVSHA2CLV", []>;156defm "" : LMULSEWWriteRes<"WriteVSHA2MSV", []>;157 158defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;159defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;160defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>;161}162}163 164multiclass UnsupportedSchedZvkned {165let Unsupported = true in {166defm "" : LMULWriteRes<"WriteVAESMVV", []>;167defm "" : LMULWriteRes<"WriteVAESKF1V", []>;168defm "" : LMULWriteRes<"WriteVAESKF2V", []>;169defm "" : LMULWriteRes<"WriteVAESZV", []>;170 171defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;172defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;173defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;174defm "" : LMULReadAdvance<"ReadVAESZV", 0>;175}176}177 178multiclass UnsupportedSchedZvksed {179let Unsupported = true in {180defm "" : LMULWriteRes<"WriteVSM4KV", []>;181defm "" : LMULWriteRes<"WriteVSM4RV", []>;182 183defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;184defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;185}186}187 188multiclass UnsupportedSchedZvksh {189let Unsupported = true in {190defm "" : LMULWriteRes<"WriteVSM3CV", []>;191defm "" : LMULWriteRes<"WriteVSM3MEV", []>;192 193defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;194defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;195}196}197 198// Helper class to define all RISC-V Vector Crypto extensions as unsupported199multiclass UnsupportedSchedZvk {200defm "" : UnsupportedSchedZvbb;201defm "" : UnsupportedSchedZvbc;202defm "" : UnsupportedSchedZvkb;203defm "" : UnsupportedSchedZvkg;204defm "" : UnsupportedSchedZvknhaOrZvknhb;205defm "" : UnsupportedSchedZvkned;206defm "" : UnsupportedSchedZvksed;207defm "" : UnsupportedSchedZvksh;208}209