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1//===----------------------------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H10#define LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H11 12#include "llvm/CodeGen/SDNodeInfo.h"13#include "llvm/CodeGen/SelectionDAGTargetInfo.h"14 15#define GET_SDNODE_ENUM16#include "RISCVGenSDNodeInfo.inc"17 18namespace llvm {19 20namespace RISCVISD {21// RISCVISD Node TSFlags22enum : llvm::SDNodeTSFlags {23 HasPassthruOpMask = 1 << 0,24 HasMaskOpMask = 1 << 1,25};26} // namespace RISCVISD27 28class RISCVSelectionDAGInfo : public SelectionDAGGenTargetInfo {29public:30 RISCVSelectionDAGInfo();31 32 ~RISCVSelectionDAGInfo() override;33 34 void verifyTargetNode(const SelectionDAG &DAG,35 const SDNode *N) const override;36 37 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,38 SDValue Chain, SDValue Dst, SDValue Src,39 SDValue Size, Align Alignment,40 bool isVolatile, bool AlwaysInline,41 MachinePointerInfo DstPtrInfo) const override;42 43 bool hasPassthruOp(unsigned Opcode) const {44 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasPassthruOpMask;45 }46 47 bool hasMaskOp(unsigned Opcode) const {48 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasMaskOpMask;49 }50 51 unsigned getMAccOpcode(unsigned MulOpcode) const {52 switch (static_cast<RISCVISD::GenNodeType>(MulOpcode)) {53 default:54 llvm_unreachable("Unexpected opcode");55 case RISCVISD::VWMUL_VL:56 return RISCVISD::VWMACC_VL;57 case RISCVISD::VWMULU_VL:58 return RISCVISD::VWMACCU_VL;59 case RISCVISD::VWMULSU_VL:60 return RISCVISD::VWMACCSU_VL;61 }62 }63};64 65} // namespace llvm66 67#endif // LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H68