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1//===-- RISCVTargetMachine.h - Define TargetMachine for RISC-V --*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file declares the RISC-V specific subclass of TargetMachine.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H14#define LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H15 16#include "MCTargetDesc/RISCVMCTargetDesc.h"17#include "RISCVSubtarget.h"18#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"19#include "llvm/IR/DataLayout.h"20#include <optional>21 22namespace llvm {23class RISCVTargetMachine : public CodeGenTargetMachineImpl {24 std::unique_ptr<TargetLoweringObjectFile> TLOF;25 mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;26 27public:28 RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,29 StringRef FS, const TargetOptions &Options,30 std::optional<Reloc::Model> RM,31 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,32 bool JIT);33 34 const RISCVSubtarget *getSubtargetImpl(const Function &F) const override;35 // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,36 // subtargets are per-function entities based on the target-specific37 // attributes of each function.38 const RISCVSubtarget *getSubtargetImpl() const = delete;39 40 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;41 42 TargetLoweringObjectFile *getObjFileLowering() const override {43 return TLOF.get();44 }45 46 MachineFunctionInfo *47 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,48 const TargetSubtargetInfo *STI) const override;49 50 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;51 52 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override;53 54 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;55 yaml::MachineFunctionInfo *56 convertFuncInfoToYAML(const MachineFunction &MF) const override;57 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,58 PerFunctionMIParsingState &PFS,59 SMDiagnostic &Error,60 SMRange &SourceRange) const override;61 void registerPassBuilderCallbacks(PassBuilder &PB) override;62 ScheduleDAGInstrs *63 createMachineScheduler(MachineSchedContext *C) const override;64 ScheduleDAGInstrs *65 createPostMachineScheduler(MachineSchedContext *C) const override;66};67 68std::unique_ptr<ScheduleDAGMutation>69createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI);70 71} // namespace llvm72 73#endif74