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1To-do2-----3 4* Keep the address of the constant pool in a register instead of forming its5 address all of the time.6* We can fold small constant offsets into the %hi/%lo references to constant7 pool addresses as well.8* When in V9 mode, register allocate %icc[0-3].9* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.10* Emit the 'Branch on Integer Register with Prediction' instructions. It's11 not clear how to write a pattern for this though:12 13float %t1(int %a, int* %p) {14 %C = seteq int %a, 015 br bool %C, label %T, label %F16T:17 store int 123, int* %p18 br label %F19F:20 ret float undef21}22 23codegens to this:24 25t1:26 save -96, %o6, %o6271) subcc %i0, 0, %l0281) bne .LBBt1_2 ! F29 nop30.LBBt1_1: ! T31 or %g0, 123, %l032 st %l0, [%i1]33.LBBt1_2: ! F34 restore %g0, %g0, %g035 retl36 nop37 381) should be replaced with a brz in V9 mode.39 40* Same as above, but emit conditional move on register zero (p192) in V941 mode. Testcase:42 43int %t1(int %a, int %b) {44 %C = seteq int %a, 045 %D = select bool %C, int %a, int %b46 ret int %D47}48 49* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling50 with the Y register, if they are faster.51 52* Codegen bswap(load)/store(bswap) -> load/store ASI53 54* Implement frame pointer elimination, e.g. eliminate save/restore for55 leaf fns.56* Fill delay slots57 58* Use %g0 directly to materialize 0. No instruction is required.59