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1//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12//===----------------------------------------------------------------------===//13// Target-independent interfaces which we are implementing14//===----------------------------------------------------------------------===//15 16include "llvm/Target/Target.td"17include "llvm/TableGen/SearchableTable.td"18 19//===----------------------------------------------------------------------===//20// SPARC Subtarget features.21//22 23def FeatureSoftMulDiv24 : SubtargetFeature<"soft-mul-div", "UseSoftMulDiv", "true",25 "Use software emulation for integer multiply and divide">;26 27def FeatureNoFSMULD28 : SubtargetFeature<"no-fsmuld", "HasNoFSMULD", "true",29 "Disable the fsmuld instruction.">;30def FeatureNoFMULS31 : SubtargetFeature<"no-fmuls", "HasNoFMULS", "true",32 "Disable the fmuls instruction.">;33 34def FeatureV935 : SubtargetFeature<"v9", "IsV9", "true",36 "Enable SPARC-V9 instructions">;37def Feature64Bit : SubtargetFeature<"64bit", "Is64Bit", "true",38 "Enable 64-bit mode", [FeatureV9]>;39 40def FeatureV8Plus41 : SubtargetFeature<"v8plus", "IsV8Plus", "true",42 "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code">;43def FeatureV8Deprecated44 : SubtargetFeature<"deprecated-v8", "UseV8DeprecatedInsts", "true",45 "Enable deprecated V8 instructions in V9 mode">;46def FeatureVIS47 : SubtargetFeature<"vis", "IsVIS", "true",48 "Enable UltraSPARC Visual Instruction Set extensions",49 [FeatureV9]>;50def FeatureVIS251 : SubtargetFeature<"vis2", "IsVIS2", "true",52 "Enable Visual Instruction Set extensions II",53 [FeatureV9]>;54def FeatureVIS355 : SubtargetFeature<"vis3", "IsVIS3", "true",56 "Enable Visual Instruction Set extensions III",57 [FeatureV9]>;58def FeatureUA200559 : SubtargetFeature<"ua2005", "IsUA2005", "true",60 "Enable UltraSPARC Architecture 2005 extensions",61 [FeatureV9, FeatureVIS, FeatureVIS2]>;62def FeatureUA200763 : SubtargetFeature<"ua2007", "IsUA2007", "true",64 "Enable UltraSPARC Architecture 2007 extensions",65 [FeatureV9, FeatureVIS, FeatureVIS2]>;66def FeatureOSA201167 : SubtargetFeature<"osa2011", "IsOSA2011", "true",68 "Enable Oracle SPARC Architecture 2011 extensions",69 [FeatureV9, FeatureVIS, FeatureVIS2, FeatureVIS3]>;70def FeatureCrypto71 : SubtargetFeature<"crypto", "IsCrypto", "true",72 "Enable cryptographic extensions",73 [FeatureOSA2011]>;74def FeatureLeon75 : SubtargetFeature<"leon", "IsLeon", "true",76 "Enable LEON extensions">;77def FeaturePWRPSR78 : SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true",79 "Enable the PWRPSR instruction">;80 81def FeatureHardQuad82 : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",83 "Enable quad-word floating point instructions">;84 85def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",86 "Use the popc (population count) instruction">;87 88def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",89 "Use software emulation for floating point">;90 91//===----------------------------------------------------------------------===//92// SPARC Subtarget tuning features.93//94 95def TuneSlowRDPC : SubtargetFeature<"slow-rdpc", "HasSlowRDPC", "true",96 "rd %pc, %XX is slow", [FeatureV9]>;97 98def TuneNoPredictor : SubtargetFeature<"no-predictor", "HasNoPredictor", "true",99 "Processor has no branch predictor, branches stall execution", []>;100 101//==== Features added predmoninantly for LEON subtarget support102include "LeonFeatures.td"103 104//==== Register allocation tweaks needed by some low-level software105foreach i = 1 ... 7 in106 def FeatureReserveG#i : SubtargetFeature<"reserve-g"#i, "ReserveRegister["#i#" + SP::G0]", "true",107 "Reserve G"#i#", making it unavailable as a GPR">;108foreach i = 0 ... 5 in109 def FeatureReserveO#i : SubtargetFeature<"reserve-o"#i, "ReserveRegister["#i#" + SP::O0]", "true",110 "Reserve O"#i#", making it unavailable as a GPR">;111foreach i = 0 ... 7 in112 def FeatureReserveL#i : SubtargetFeature<"reserve-l"#i, "ReserveRegister["#i#" + SP::L0]", "true",113 "Reserve L"#i#", making it unavailable as a GPR">;114foreach i = 0 ... 5 in115 def FeatureReserveI#i : SubtargetFeature<"reserve-i"#i, "ReserveRegister["#i#" + SP::I0]", "true",116 "Reserve I"#i#", making it unavailable as a GPR">;117 118//===----------------------------------------------------------------------===//119// Register File, Calling Conv, Instruction Descriptions120//===----------------------------------------------------------------------===//121 122include "SparcASITags.td"123include "SparcPrefetchTags.td"124include "SparcRegisterInfo.td"125include "SparcCallingConv.td"126include "SparcSchedule.td"127include "SparcInstrInfo.td"128 129defm : RemapAllTargetPseudoPointerOperands<sparc_ptr_rc>;130 131def SparcInstrInfo : InstrInfo;132 133def SparcAsmParser : AsmParser {134 let ShouldEmitMatchRegisterAltName = true;135 let AllowDuplicateRegisterNames = true;136}137 138def SparcAsmParserVariant : AsmParserVariant {139 let RegisterPrefix = "%";140}141 142//===----------------------------------------------------------------------===//143// SPARC processors supported.144//===----------------------------------------------------------------------===//145 146class Proc<string Name, list<SubtargetFeature> Features,147 list<SubtargetFeature> TuneFeatures = []>148 : Processor<Name, NoItineraries, Features, TuneFeatures>;149 150def : Proc<"generic", []>;151def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>;152def : Proc<"v8", []>;153def : Proc<"supersparc", []>;154def : Proc<"sparclite", []>;155def : Proc<"f934", []>;156def : Proc<"hypersparc", []>;157def : Proc<"sparclite86x", []>;158def : Proc<"sparclet", []>;159def : Proc<"tsc701", []>;160def : Proc<"myriad2", [FeatureLeon, LeonCASA]>;161def : Proc<"myriad2.1", [FeatureLeon, LeonCASA]>;162def : Proc<"myriad2.2", [FeatureLeon, LeonCASA]>;163def : Proc<"myriad2.3", [FeatureLeon, LeonCASA]>;164def : Proc<"ma2100", [FeatureLeon, LeonCASA]>;165def : Proc<"ma2150", [FeatureLeon, LeonCASA]>;166def : Proc<"ma2155", [FeatureLeon, LeonCASA]>;167def : Proc<"ma2450", [FeatureLeon, LeonCASA]>;168def : Proc<"ma2455", [FeatureLeon, LeonCASA]>;169def : Proc<"ma2x5x", [FeatureLeon, LeonCASA]>;170def : Proc<"ma2080", [FeatureLeon, LeonCASA]>;171def : Proc<"ma2085", [FeatureLeon, LeonCASA]>;172def : Proc<"ma2480", [FeatureLeon, LeonCASA]>;173def : Proc<"ma2485", [FeatureLeon, LeonCASA]>;174def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>;175def : Proc<"v9", [FeatureV9]>;176def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS],177 [TuneSlowRDPC]>;178def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,179 FeatureVIS2],180 [TuneSlowRDPC]>;181def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,182 FeatureVIS2, FeatureUA2005],183 [TuneNoPredictor]>;184def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,185 FeatureVIS, FeatureVIS2, FeatureUA2005],186 [TuneNoPredictor]>;187def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,188 FeatureVIS, FeatureVIS2, FeatureVIS3,189 FeatureUA2005, FeatureUA2007],190 [TuneNoPredictor]>;191def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,192 FeatureVIS, FeatureVIS2, FeatureVIS3,193 FeatureUA2005, FeatureUA2007, FeatureOSA2011,194 FeatureCrypto]>;195 196// LEON 2 FT generic197def : Processor<"leon2", LEON2Itineraries,198 [FeatureLeon]>;199 200// LEON 2 FT (AT697E)201// TO DO: Place-holder: Processor specific features will be added *very* soon here.202def : Processor<"at697e", LEON2Itineraries,203 [FeatureLeon, InsertNOPLoad]>;204 205// LEON 2 FT (AT697F)206// TO DO: Place-holder: Processor specific features will be added *very* soon here.207def : Processor<"at697f", LEON2Itineraries,208 [FeatureLeon, InsertNOPLoad]>;209 210 211// LEON 3 FT generic212def : Processor<"leon3", LEON3Itineraries,213 [FeatureLeon, UMACSMACSupport]>;214 215// LEON 3 FT (UT699). Provides features for the UT699 processor216// - covers all the erratum fixes for LEON3, but does not support the CASA instruction.217def : Processor<"ut699", LEON3Itineraries,218 [FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>;219 220// LEON3 FT (GR712RC). Provides features for the GR712RC processor.221// - covers all the erratum fixed for LEON3 and support for the CASA instruction.222def : Processor<"gr712rc", LEON3Itineraries,223 [FeatureLeon, LeonCASA]>;224 225// LEON 4 FT generic226def : Processor<"leon4", LEON4Itineraries,227 [FeatureLeon, UMACSMACSupport, LeonCASA]>;228 229// LEON 4 FT (GR740)230// TO DO: Place-holder: Processor specific features will be added *very* soon here.231def : Processor<"gr740", LEON4Itineraries,232 [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter,233 FeaturePWRPSR]>;234 235//===----------------------------------------------------------------------===//236// Declare the target which we are implementing237//===----------------------------------------------------------------------===//238 239def SparcAsmWriter : AsmWriter {240 string AsmWriterClassName = "InstPrinter";241 int PassSubtarget = 1;242 int Variant = 0;243}244 245def Sparc : Target {246 // Pull in Instruction Info:247 let InstructionSet = SparcInstrInfo;248 let AssemblyParsers = [SparcAsmParser];249 let AssemblyParserVariants = [SparcAsmParserVariant];250 let AssemblyWriters = [SparcAsmWriter];251 let AllowRegisterRenaming = 1;252}253