213 lines · c
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the interfaces that Sparc uses to lower LLVM code into a10// selection DAG.11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H15#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H16 17#include "Sparc.h"18#include "llvm/CodeGen/TargetLowering.h"19 20namespace llvm {21 class SparcSubtarget;22 23 class SparcTargetLowering : public TargetLowering {24 const SparcSubtarget *Subtarget;25 public:26 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);27 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;28 29 bool useSoftFloat() const override;30 31 bool softPromoteHalfType() const override { return true; }32 33 /// computeKnownBitsForTargetNode - Determine which of the bits specified34 /// in Mask are known to be either zero or one and return them in the35 /// KnownZero/KnownOne bitsets.36 void computeKnownBitsForTargetNode(const SDValue Op,37 KnownBits &Known,38 const APInt &DemandedElts,39 const SelectionDAG &DAG,40 unsigned Depth = 0) const override;41 42 MachineBasicBlock *43 EmitInstrWithCustomInserter(MachineInstr &MI,44 MachineBasicBlock *MBB) const override;45 46 ConstraintType getConstraintType(StringRef Constraint) const override;47 ConstraintWeight48 getSingleConstraintMatchWeight(AsmOperandInfo &info,49 const char *constraint) const override;50 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,51 std::vector<SDValue> &Ops,52 SelectionDAG &DAG) const override;53 54 std::pair<unsigned, const TargetRegisterClass *>55 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,56 StringRef Constraint, MVT VT) const override;57 58 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;59 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {60 return MVT::i32;61 }62 63 Register getRegisterByName(const char* RegName, LLT VT,64 const MachineFunction &MF) const override;65 66 /// If a physical register, this returns the register that receives the67 /// exception address on entry to an EH pad.68 Register69 getExceptionPointerRegister(const Constant *PersonalityFn) const override {70 return SP::I0;71 }72 73 /// If a physical register, this returns the register that receives the74 /// exception typeid on entry to a landing pad.75 Register76 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {77 return SP::I1;78 }79 80 /// Override to support customized stack guard loading.81 bool useLoadStackGuardNode(const Module &M) const override;82 83 /// getSetCCResultType - Return the ISD::SETCC ValueType84 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,85 EVT VT) const override;86 87 SDValue88 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,89 const SmallVectorImpl<ISD::InputArg> &Ins,90 const SDLoc &dl, SelectionDAG &DAG,91 SmallVectorImpl<SDValue> &InVals) const override;92 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,93 bool isVarArg,94 const SmallVectorImpl<ISD::InputArg> &Ins,95 const SDLoc &dl, SelectionDAG &DAG,96 SmallVectorImpl<SDValue> &InVals) const;97 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,98 bool isVarArg,99 const SmallVectorImpl<ISD::InputArg> &Ins,100 const SDLoc &dl, SelectionDAG &DAG,101 SmallVectorImpl<SDValue> &InVals) const;102 103 SDValue104 LowerCall(TargetLowering::CallLoweringInfo &CLI,105 SmallVectorImpl<SDValue> &InVals) const override;106 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,107 SmallVectorImpl<SDValue> &InVals) const;108 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,109 SmallVectorImpl<SDValue> &InVals) const;110 111 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,112 bool isVarArg,113 const SmallVectorImpl<ISD::OutputArg> &Outs,114 LLVMContext &Context, const Type *RetTy) const override;115 116 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,117 const SmallVectorImpl<ISD::OutputArg> &Outs,118 const SmallVectorImpl<SDValue> &OutVals,119 const SDLoc &dl, SelectionDAG &DAG) const override;120 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,121 bool IsVarArg,122 const SmallVectorImpl<ISD::OutputArg> &Outs,123 const SmallVectorImpl<SDValue> &OutVals,124 const SDLoc &DL, SelectionDAG &DAG) const;125 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,126 bool IsVarArg,127 const SmallVectorImpl<ISD::OutputArg> &Outs,128 const SmallVectorImpl<SDValue> &OutVals,129 const SDLoc &DL, SelectionDAG &DAG) const;130 131 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;132 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;133 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;134 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;135 136 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;137 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,138 SelectionDAG &DAG) const;139 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;140 141 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,142 const SDLoc &DL, SelectionDAG &DAG) const;143 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,144 const char *LibFuncName,145 unsigned numArgs) const;146 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,147 const SDLoc &DL, SelectionDAG &DAG) const;148 149 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;150 151 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;152 153 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,154 SelectionDAG &DAG) const;155 156 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;157 158 bool IsEligibleForTailCallOptimization(CCState &CCInfo,159 CallLoweringInfo &CLI,160 MachineFunction &MF) const;161 162 bool ShouldShrinkFPConstant(EVT VT) const override {163 // Do not shrink FP constpool if VT == MVT::f128.164 // (ldd, call _Q_fdtoq) is more expensive than two ldds.165 return VT != MVT::f128;166 }167 168 bool isFNegFree(EVT VT) const override;169 170 bool isFPImmLegal(const APFloat &Imm, EVT VT,171 bool ForCodeSize) const override;172 173 bool isCtlzFast() const override;174 175 bool isCheapToSpeculateCtlz(Type *Ty) const override {176 return isCtlzFast();177 }178 179 bool isCheapToSpeculateCttz(Type *Ty) const override;180 181 bool enableAggressiveFMAFusion(EVT VT) const override { return true; };182 183 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,184 EVT VT) const override;185 186 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,187 AtomicOrdering Ord) const override;188 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,189 AtomicOrdering Ord) const override;190 191 bool shouldInsertFencesForAtomic(const Instruction *I) const override {192 // FIXME: We insert fences for each atomics and generate193 // sub-optimal code for PSO/TSO. (Approximately nobody uses any194 // mode but TSO, which makes this even more silly)195 return true;196 }197 198 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;199 200 void ReplaceNodeResults(SDNode *N,201 SmallVectorImpl<SDValue>& Results,202 SelectionDAG &DAG) const override;203 204 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,205 unsigned BROpcode) const;206 207 void AdjustInstrPostInstrSelection(MachineInstr &MI,208 SDNode *Node) const override;209 };210} // end namespace llvm211 212#endif // LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H213