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1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains instruction definitions and patterns needed for 64-bit10// code generation on SPARC v9.11//12// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can13// also be used in 32-bit code running on a SPARC v9 CPU.14//15//===----------------------------------------------------------------------===//16 17let Predicates = [Is64Bit] in {18// The same integer registers are used for i32 and i64 values.19// When registers hold i32 values, the high bits are don't care.20// This give us free trunc and anyext.21def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;22def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;23 24} // Predicates = [Is64Bit]25 26 27//===----------------------------------------------------------------------===//28// 64-bit Shift Instructions.29//===----------------------------------------------------------------------===//30//31// The 32-bit shift instructions are still available. The left shift srl32// instructions shift all 64 bits, but it only accepts a 5-bit shift amount.33//34// The srl instructions only shift the low 32 bits and clear the high 32 bits.35// Finally, sra shifts the low 32 bits and sign-extends to 64 bits.36 37let Predicates = [Is64Bit] in {38 39def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;40def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;41 42def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;43def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;44 45defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, shift_imm6, I64Regs>;46defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, shift_imm6, I64Regs>;47defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>;48 49} // Predicates = [Is64Bit]50 51 52//===----------------------------------------------------------------------===//53// 64-bit Immediates.54//===----------------------------------------------------------------------===//55//56// All 32-bit immediates can be materialized with sethi+or, but 64-bit57// immediates may require more code. There may be a point where it is58// preferable to use a constant pool load instead, depending on the59// microarchitecture.60 61// Single-instruction patterns.62 63// Zero immediate.64def : Pat<(i64 0), (COPY (i64 G0))>,65 Requires<[Is64Bit]>;66 67// The ALU instructions want their simm13 operands as i32 immediates.68// FIXME: This is no longer true, they are now pointer-sized.69def as_i32imm : SDNodeXForm<imm, [{70 return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);71}]>;72def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;73def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;74 75// Double-instruction patterns.76 77// All unsigned i32 immediates can be handled by sethi+or.78def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;79def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,80 Requires<[Is64Bit]>;81 82// All negative i33 immediates can be handled by sethi+xor.83def nimm33 : PatLeaf<(imm), [{84 int64_t Imm = N->getSExtValue();85 return Imm < 0 && isInt<33>(Imm);86}]>;87// Bits 10-31 inverted. Same as assembler's %hix.88def HIX22 : SDNodeXForm<imm, [{89 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);90 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);91}]>;92// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.93def LOX10 : SDNodeXForm<imm, [{94 return CurDAG->getSignedTargetConstant(~(~N->getZExtValue() & 0x3ff),95 SDLoc(N), MVT::i32);96}]>;97def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,98 Requires<[Is64Bit]>;99 100// More possible patterns:101//102// (sllx sethi, n)103// (sllx simm13, n)104//105// 3 instrs:106//107// (xor (sllx sethi), simm13)108// (sllx (xor sethi, simm13))109//110// 4 instrs:111//112// (or sethi, (sllx sethi))113// (xnor sethi, (sllx sethi))114//115// 5 instrs:116//117// (or (sllx sethi), (or sethi, simm13))118// (xnor (sllx sethi), (or sethi, simm13))119// (or (sllx sethi), (sllx sethi))120// (xnor (sllx sethi), (sllx sethi))121//122// Worst case is 6 instrs:123//124// (or (sllx (or sethi, simmm13)), (or sethi, simm13))125 126// Bits 42-63, same as assembler's %hh.127def HH22 : SDNodeXForm<imm, [{128 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);129 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);130}]>;131// Bits 32-41, same as assembler's %hm.132def HM10 : SDNodeXForm<imm, [{133 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);134 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);135}]>;136def : Pat<(i64 imm:$val),137 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),138 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,139 Requires<[Is64Bit]>;140 141 142//===----------------------------------------------------------------------===//143// 64-bit Integer Arithmetic and Logic.144//===----------------------------------------------------------------------===//145 146let Predicates = [Is64Bit] in {147 148def : Pat<(and i64:$lhs, i64:$rhs), (ANDrr $lhs, $rhs)>;149def : Pat<(or i64:$lhs, i64:$rhs), (ORrr $lhs, $rhs)>;150def : Pat<(xor i64:$lhs, i64:$rhs), (XORrr $lhs, $rhs)>;151 152def : Pat<(and i64:$lhs, (i64 simm13:$rhs)), (ANDri $lhs, imm:$rhs)>;153def : Pat<(or i64:$lhs, (i64 simm13:$rhs)), (ORri $lhs, imm:$rhs)>;154def : Pat<(xor i64:$lhs, (i64 simm13:$rhs)), (XORri $lhs, imm:$rhs)>;155 156def : Pat<(and i64:$lhs, (not i64:$rhs)), (ANDNrr $lhs, $rhs)>;157def : Pat<(or i64:$lhs, (not i64:$rhs)), (ORNrr $lhs, $rhs)>;158def : Pat<(not (xor i64:$lhs, i64:$rhs)), (XNORrr $lhs, $rhs)>;159 160def : Pat<(addc i64:$lhs, i64:$rhs), (ADDCCrr $lhs, $rhs)>, Requires<[HasVIS3]>;161def : Pat<(add i64:$lhs, i64:$rhs), (ADDrr $lhs, $rhs)>;162def : Pat<(sub i64:$lhs, i64:$rhs), (SUBrr $lhs, $rhs)>;163 164def : Pat<(addc i64:$lhs, (i64 simm13:$rhs)), (ADDCCri $lhs, imm:$rhs)>, Requires<[HasVIS3]>;165def : Pat<(add i64:$lhs, (i64 simm13:$rhs)), (ADDri $lhs, imm:$rhs)>;166def : Pat<(sub i64:$lhs, (i64 simm13:$rhs)), (SUBri $lhs, imm:$rhs)>;167 168def : Pat<(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym),169 (TLS_ADDrr $rs1, $rs2, $sym)>;170 171def : Pat<(SPcmpicc i64:$lhs, i64:$rhs), (SUBCCrr $lhs, $rhs)>;172def : Pat<(SPcmpicc i64:$lhs, (i64 simm13:$rhs)), (SUBCCri $lhs, imm:$rhs)>;173def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;174 175} // Predicates = [Is64Bit]176 177 178//===----------------------------------------------------------------------===//179// 64-bit Integer Multiply and Divide.180//===----------------------------------------------------------------------===//181 182let Predicates = [Is64Bit] in {183defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>;184 185// Division can trap.186let hasSideEffects = 1 in {187defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>;188defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>;189} // hasSideEffects = 1190} // Predicates = [Is64Bit]191 192 193//===----------------------------------------------------------------------===//194// 64-bit Loads and Stores.195//===----------------------------------------------------------------------===//196//197// All the 32-bit loads and stores are available. The extending loads are sign198// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits199// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned200// Word).201//202// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.203 204let Predicates = [Is64Bit] in {205 206// 64-bit loads.207defm LDX : LoadA<"ldx", 0b001011, 0b011011, load, I64Regs, i64>;208 209let mayLoad = 1, isAsmParserOnly = 1 in {210 def TLS_LDXrr : F3_1<3, 0b001011,211 (outs IntRegs:$rd),212 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),213 "ldx [$addr], $rd, $sym",214 [(set i64:$rd,215 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;216 def GDOP_LDXrr : F3_1<3, 0b001011,217 (outs I64Regs:$rd),218 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym),219 "ldx [$addr], $rd, $sym",220 [(set i64:$rd,221 (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>;222}223 224// Extending loads to i64.225def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;226def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;227def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;228def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;229 230def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;231def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;232def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;233def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;234def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;235def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;236 237def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;238def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;239def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;240def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;241def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;242def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;243 244def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;245def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;246def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;247def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;248 249// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.250defm LDSW : LoadA<"ldsw", 0b001000, 0b011000, sextloadi32, I64Regs, i64>;251 252// 64-bit stores.253defm STX : StoreA<"stx", 0b001110, 0b011110, store, I64Regs, i64>;254 255// Truncating stores from i64 are identical to the i32 stores.256def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;257def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;258def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;259def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;260def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>;261def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>;262 263// store 0, addr -> store %g0, addr264def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>;265def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;266 267} // Predicates = [Is64Bit]268 269 270//===----------------------------------------------------------------------===//271// 64-bit Conditionals.272//===----------------------------------------------------------------------===//273 274//275// Flag-setting instructions like subcc and addcc set both icc and xcc flags.276// The icc flags correspond to the 32-bit result, and the xcc are for the277// full 64-bit result.278//279// We reuse CMPICC SDNodes for compares, but use new BPXCC branch nodes for280// 64-bit compares. See LowerBR_CC.281 282let Predicates = [Is64Bit] in {283 284let Uses = [ICC], cc = 0b10 in285 defm BPX : IPredBranch<"%xcc", [(SPbpxcc bb:$imm19, imm:$cond)]>;286 287// Conditional moves on %xcc.288let Uses = [ICC], Constraints = "$f = $rd" in {289let intcc = 1, cc = 0b10 in {290def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),291 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),292 "mov$cond %xcc, $rs2, $rd",293 [(set i32:$rd,294 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;295def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),296 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),297 "mov$cond %xcc, $simm11, $rd",298 [(set i32:$rd,299 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;300} // cc301 302let intcc = 1, opf_cc = 0b10 in {303def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),304 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),305 "fmovs$cond %xcc, $rs2, $rd",306 [(set f32:$rd,307 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;308def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),309 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),310 "fmovd$cond %xcc, $rs2, $rd",311 [(set f64:$rd,312 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;313let Predicates = [Is64Bit, HasHardQuad] in314def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),315 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),316 "fmovq$cond %xcc, $rs2, $rd",317 [(set f128:$rd,318 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;319} // opf_cc320} // Uses, Constraints321 322// Branch On integer register with Prediction (BPr).323let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in324multiclass BranchOnReg<list<dag> CCPattern> {325 def R : F2_4<0, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),326 "br$rcond $rs1, $imm16", CCPattern>;327 def RA : F2_4<1, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),328 "br$rcond,a $rs1, $imm16", []>;329 def RNT : F2_4<0, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),330 "br$rcond,pn $rs1, $imm16", []>;331 def RANT : F2_4<1, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),332 "br$rcond,a,pn $rs1, $imm16", []>;333}334 335multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {336 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),337 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;338 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),339 (APT I64Regs:$rs1, bprtarget16:$imm16), 0>;340}341 342let Predicates = [Is64Bit] in343 defm BP : BranchOnReg<[(SPbrreg bb:$imm16, imm:$rcond, i64:$rs1)]>;344 345// Move integer register on register condition (MOVr).346let Predicates = [Is64Bit], Constraints = "$f = $rd" in {347 def MOVRrr : F4_4r<0b101111, 0b00000, (outs IntRegs:$rd),348 (ins I64Regs:$rs1, IntRegs:$rs2, IntRegs:$f, RegCCOp:$rcond),349 "movr$rcond $rs1, $rs2, $rd",350 [(set i32:$rd, (SPselectreg i32:$rs2, i32:$f, imm:$rcond, i64:$rs1))]>;351 352 def MOVRri : F4_4i<0b101111, (outs IntRegs:$rd),353 (ins I64Regs:$rs1, i32imm:$simm10, IntRegs:$f, RegCCOp:$rcond),354 "movr$rcond $rs1, $simm10, $rd",355 [(set i32:$rd, (SPselectreg simm10:$simm10, i32:$f, imm:$rcond, i64:$rs1))]>;356}357 358// Move FP register on integer register condition (FMOVr).359let Predicates = [Is64Bit], Constraints = "$f = $rd" in {360 def FMOVRS : F4_4r<0b110101, 0b00101,361 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2, FPRegs:$f, RegCCOp:$rcond),362 "fmovrs$rcond $rs1, $rs2, $rd",363 [(set f32:$rd, (SPselectreg f32:$rs2, f32:$f, imm:$rcond, i64:$rs1))]>;364 def FMOVRD : F4_4r<0b110101, 0b00110,365 (outs DFPRegs:$rd), (ins I64Regs:$rs1, DFPRegs:$rs2, DFPRegs:$f, RegCCOp:$rcond),366 "fmovrd$rcond $rs1, $rs2, $rd",367 [(set f64:$rd, (SPselectreg f64:$rs2, f64:$f, imm:$rcond, i64:$rs1))]>;368 let Predicates = [HasHardQuad] in369 def FMOVRQ : F4_4r<0b110101, 0b00111,370 (outs QFPRegs:$rd), (ins I64Regs:$rs1, QFPRegs:$rs2, QFPRegs:$f, RegCCOp:$rcond),371 "fmovrq$rcond $rs1, $rs2, $rd",372 [(set f128:$rd, (SPselectreg f128:$rs2, f128:$f, imm:$rcond, i64:$rs1))]>;373}374 375//===----------------------------------------------------------------------===//376// 64-bit Floating Point Conversions.377//===----------------------------------------------------------------------===//378 379let Predicates = [Is64Bit] in {380 381def FXTOS : F3_3u<2, 0b110100, 0b010000100,382 (outs FPRegs:$rd), (ins DFPRegs:$rs2),383 "fxtos $rs2, $rd",384 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;385def FXTOD : F3_3u<2, 0b110100, 0b010001000,386 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),387 "fxtod $rs2, $rd",388 [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;389let Predicates = [Is64Bit, HasHardQuad] in390def FXTOQ : F3_3u<2, 0b110100, 0b010001100,391 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),392 "fxtoq $rs2, $rd",393 [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;394 395def FSTOX : F3_3u<2, 0b110100, 0b010000001,396 (outs DFPRegs:$rd), (ins FPRegs:$rs2),397 "fstox $rs2, $rd",398 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;399def FDTOX : F3_3u<2, 0b110100, 0b010000010,400 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),401 "fdtox $rs2, $rd",402 [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>;403let Predicates = [Is64Bit, HasHardQuad] in404def FQTOX : F3_3u<2, 0b110100, 0b010000011,405 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),406 "fqtox $rs2, $rd",407 [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>;408 409} // Predicates = [Is64Bit]410 411def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),412 (MOVXCCrr $t, $f, imm:$cond)>;413def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),414 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>;415 416def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond),417 (MOVICCrr $t, $f, imm:$cond)>;418def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond),419 (MOVICCri (as_i32imm $t), $f, imm:$cond)>;420 421def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond),422 (MOVFCCrr $t, $f, imm:$cond)>;423def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),424 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>;425 426def : Pat<(SPselectreg i64:$t, i64:$f, imm:$rcond, i64:$rs1),427 (MOVRrr $rs1, $t, $f, imm:$rcond)>;428def : Pat<(SPselectreg (i64 simm10:$t), i64:$f, imm:$rcond, i64:$rs1),429 (MOVRri $rs1, (as_i32imm $t), $f, imm:$rcond)>;430 431} // Predicates = [Is64Bit]432 433// ATOMICS.434let Predicates = [Is64Bit, HasV9], Constraints = "$swap = $rd" in {435 def CASXArr: F3_1_asi<3, 0b111110,436 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,437 I64Regs:$swap, ASITag:$asi),438 "casxa [$rs1] $asi, $rs2, $rd",439 []>;440 441 let Uses = [ASR3] in442 def CASXAri: F3_1_cas_asi<3, 0b111110,443 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,444 I64Regs:$swap),445 "casxa [$rs1] %asi, $rs2, $rd",446 []>;447} // Predicates = [Is64Bit], Constraints = ...448 449let Predicates = [Is64Bit] in {450 451// atomic_load_nonext_64 addr -> load addr452def : Pat<(i64 (atomic_load_nonext_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>;453def : Pat<(i64 (atomic_load_nonext_64 ADDRri:$src)), (LDXri ADDRri:$src)>;454 455// atomic_store_64 val, addr -> store val, addr456def : Pat<(atomic_store_64 i64:$val, ADDRrr:$dst), (STXrr ADDRrr:$dst, $val)>;457def : Pat<(atomic_store_64 i64:$val, ADDRri:$dst), (STXri ADDRri:$dst, $val)>;458 459def : Pat<(atomic_cmp_swap_i64 i64:$rs1, i64:$rs2, i64:$swap),460 (CASXArr $rs1, $rs2, $swap, 0x80)>;461 462} // Predicates = [Is64Bit]463 464let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in465 defm TXCC : TRAP<"%xcc">;466 467// Global addresses, constant pool entries468let Predicates = [Is64Bit] in {469 470def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;471def : Pat<(SPlo tglobaladdr:$in), (ORri (i64 G0), tglobaladdr:$in)>;472def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;473def : Pat<(SPlo tconstpool:$in), (ORri (i64 G0), tconstpool:$in)>;474 475// GlobalTLS addresses476def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;477def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i64 G0), tglobaltlsaddr:$in)>;478def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),479 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;480def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),481 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;482 483// Blockaddress484def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;485def : Pat<(SPlo tblockaddress:$in), (ORri (i64 G0), tblockaddress:$in)>;486 487// Add reg, lo. This is used when taking the addr of a global/constpool entry.488def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;489def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;490def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),491 (ADDri $r, tblockaddress:$in)>;492}493