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1//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains instruction aliases for Sparc.10//===----------------------------------------------------------------------===//11 12// Instruction aliases for conditional moves.13 14// mov<cond> <ccreg> rs2, rd15multiclass intcond_mov_alias<string cond, int condVal, string ccreg,16 Instruction movrr, Instruction movri,17 Instruction fmovs, Instruction fmovd> {18 19 // mov<cond> (%icc|%xcc), rs2, rd20 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),21 ", $rs2, $rd"),22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;23 24 // mov<cond> (%icc|%xcc), simm11, rd25 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),26 ", $simm11, $rd"),27 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;28 29 // fmovs<cond> (%icc|%xcc), $rs2, $rd30 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),31 ", $rs2, $rd"),32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;33 34 // fmovd<cond> (%icc|%xcc), $rs2, $rd35 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),36 ", $rs2, $rd"),37 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;38}39 40// mov<cond> <ccreg> rs2, rd41multiclass fpcond_mov_alias<string cond, int condVal,42 Instruction movrr, Instruction movri,43 Instruction fmovs, Instruction fmovd> {44 45 // mov<cond> %fcc[0-3], rs2, rd46 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),47 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;48 49 // mov<cond> %fcc[0-3], simm11, rd50 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),51 (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;52 53 // fmovs<cond> %fcc[0-3], $rs2, $rd54 def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),55 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;56 57 // fmovd<cond> %fcc[0-3], $rs2, $rd58 def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),59 (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;60}61 62// movr<cond> rs1, rs2, rd63multiclass regcond_mov_alias<string rcond, int condVal,64 Instruction movrrr, Instruction movrri,65 Instruction fmovrs, Instruction fmovrd,66 Instruction fmovrq> {67 68 // movr<cond> $rs1, $rs2, $rd69 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $rs2, $rd"),70 (movrrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, condVal)>;71 72 // movr<cond> $rs1, $simm10, $rd73 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $simm10, $rd"),74 (movrri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, condVal)>;75 76 // fmovrs<cond> $rs1, $rs2, $rd77 def : InstAlias<!strconcat(!strconcat("fmovrs", rcond), " $rs1, $rs2, $rd"),78 (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;79 80 // fmovrd<cond> $rs1, $rs2, $rd81 def : InstAlias<!strconcat(!strconcat("fmovrd", rcond), " $rs1, $rs2, $rd"),82 (fmovrd DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, condVal)>;83 84 // fmovrq<cond> $rs1, $rs2, $rd85 let Predicates = [HasHardQuad] in86 def : InstAlias<!strconcat(!strconcat("fmovrq", rcond), " $rs1, $rs2, $rd"),87 (fmovrq QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, condVal)>;88}89 90// Instruction aliases for integer conditional branches and moves.91multiclass int_cond_alias<string cond, int condVal> {92 93 // b<cond> $imm94 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),95 (BCOND brtarget:$imm, condVal)>;96 97 // b<cond>,a $imm98 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),99 (BCONDA brtarget:$imm, condVal)>;100 101 // b<cond> %icc, $imm102 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),103 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;104 105 // b<cond>,pt %icc, $imm106 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),107 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;108 109 // b<cond>,a %icc, $imm110 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),111 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;112 113 // b<cond>,a,pt %icc, $imm114 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),115 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;116 117 // b<cond>,pn %icc, $imm118 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),119 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;120 121 // b<cond>,a,pn %icc, $imm122 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),123 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;124 125 // b<cond> %xcc, $imm126 def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),127 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;128 129 // b<cond>,pt %xcc, $imm130 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),131 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;132 133 // b<cond>,a %xcc, $imm134 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),135 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;136 137 // b<cond>,a,pt %xcc, $imm138 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),139 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;140 141 // b<cond>,pn %xcc, $imm142 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),143 (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;144 145 // b<cond>,a,pn %xcc, $imm146 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),147 (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;148 149 150 defm : intcond_mov_alias<cond, condVal, " %icc",151 MOVICCrr, MOVICCri,152 FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;153 154 defm : intcond_mov_alias<cond, condVal, " %xcc",155 MOVXCCrr, MOVXCCri,156 FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;157 158 // fmovq<cond> (%icc|%xcc), $rs2, $rd159 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),160 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,161 Requires<[HasV9, HasHardQuad]>;162 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),163 (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,164 Requires<[Is64Bit, HasHardQuad]>;165 166 // t<cond> %icc, rs => t<cond> %icc, G0 + rs167 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),168 (TICCrr G0, IntRegs:$rs2, condVal)>,169 Requires<[HasV9]>;170 // t<cond> %icc, rs1 + rs2171 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),172 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,173 Requires<[HasV9]>;174 175 176 // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs177 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),178 (TXCCrr G0, IntRegs:$rs2, condVal)>,179 Requires<[HasV9]>;180 // t<cond> %xcc, rs1 + rs2181 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),182 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,183 Requires<[HasV9]>;184 185 186 // t<cond> rs=> t<cond> %icc, G0 + rs2187 //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),188 // (TICCrr G0, IntRegs:$rs2, condVal)>,189 // Requires<[HasV9]>;190 191 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2192 //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),193 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,194 // Requires<[HasV9]>;195 196 // t<cond> %icc, imm => t<cond> %icc, G0 + imm197 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),198 (TICCri G0, i32imm:$imm, condVal)>,199 Requires<[HasV9]>;200 // t<cond> %icc, rs1 + imm201 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),202 (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,203 Requires<[HasV9]>;204 // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm205 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),206 (TXCCri G0, i32imm:$imm, condVal)>,207 Requires<[HasV9]>;208 // t<cond> %xcc, rs1 + imm209 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),210 (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,211 Requires<[HasV9]>;212 213 // t<cond> imm => t<cond> G0 + imm214 def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),215 (TRAPri G0, i32imm:$imm, condVal)>;216 217 // t<cond> rs1 + imm => t<cond> rs1 + imm218 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),219 (TRAPri IntRegs:$rs1, i32imm:$imm, condVal)>;220 221 // t<cond> rs1 => t<cond> G0 + rs1222 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1"),223 (TRAPrr G0, IntRegs:$rs1, condVal)>;224 225 // t<cond> rs1 + rs2226 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),227 (TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;228}229 230 231// Instruction aliases for floating point conditional branches and moves.232multiclass fp_cond_alias<string cond, int condVal> {233 234 // fb<cond> $imm235 def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),236 (FBCOND brtarget:$imm, condVal), 0>;237 238 // fb<cond>,a $imm239 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),240 (FBCONDA brtarget:$imm, condVal), 0>;241 242 // fb<cond> %fcc0, $imm243 def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),244 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,245 Requires<[HasV9]>;246 247 // fb<cond>,pt %fcc0, $imm248 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),249 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,250 Requires<[HasV9]>;251 252 // fb<cond>,a %fcc0, $imm253 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),254 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,255 Requires<[HasV9]>;256 257 // fb<cond>,a,pt %fcc0, $imm258 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),259 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,260 Requires<[HasV9]>;261 262 // fb<cond>,pn %fcc0, $imm263 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),264 (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,265 Requires<[HasV9]>;266 267 // fb<cond>,a,pn %fcc0, $imm268 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),269 (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,270 Requires<[HasV9]>;271 272 defm : fpcond_mov_alias<cond, condVal,273 V9MOVFCCrr, V9MOVFCCri,274 V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;275 276 // fmovq<cond> %fcc0, $rs2, $rd277 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),278 (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,279 condVal)>,280 Requires<[HasV9, HasHardQuad]>;281}282 283 284// Instruction aliases for co-processor conditional branches.285multiclass cp_cond_alias<string cond, int condVal> {286 287 // cb<cond> $imm288 def : InstAlias<!strconcat(!strconcat("cb", cond), " $imm"),289 (CPBCOND brtarget:$imm, condVal), 0>;290 291 // cb<cond>,a $imm292 def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),293 (CPBCONDA brtarget:$imm, condVal), 0>;294}295 296// Instruction aliases for register conditional branches and moves.297multiclass reg_cond_alias<string rcond, int condVal> {298 // br<rcond> $rs1, $imm299 def : InstAlias<!strconcat(!strconcat("br", rcond), " $rs1, $imm"),300 (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,301 Requires<[Is64Bit]>;302 303 // br<rcond>,pt $rs1, $imm304 def : InstAlias<!strconcat(!strconcat("br", rcond), ",pt $rs1, $imm"),305 (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,306 Requires<[Is64Bit]>;307 308 // br<rcond>,pn $rs1, $imm309 def : InstAlias<!strconcat(!strconcat("br", rcond), ",pn $rs1, $imm"),310 (BPRNT bprtarget16:$imm, condVal, I64Regs:$rs1)>,311 Requires<[Is64Bit]>;312 313 // br<rcond>,a $rs1, $imm314 def : InstAlias<!strconcat(!strconcat("br", rcond), ",a $rs1, $imm"),315 (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,316 Requires<[Is64Bit]>;317 318 // br<rcond>,a,pt $rs1, $imm319 def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pt $rs1, $imm"),320 (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,321 Requires<[Is64Bit]>;322 323 // br<rcond>,a,pn $rs1, $imm324 def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pn $rs1, $imm"),325 (BPRANT bprtarget16:$imm, condVal, I64Regs:$rs1)>,326 Requires<[Is64Bit]>;327 328 defm : regcond_mov_alias<rcond, condVal,329 MOVRrr, MOVRri,330 FMOVRS, FMOVRD, FMOVRQ>,331 Requires<[Is64Bit]>;332}333 334// Instruction aliases for compare-and-branch.335multiclass cwb_cond_alias<string cond, int condVal> {336 def : InstAlias<"cwb" # cond # " $rs1, $rs2, $imm",337 (CWBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,338 Requires<[HasOSA2011]>;339 def : InstAlias<"cwb" # cond # " $rs1, $simm5, $imm",340 (CWBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,341 Requires<[HasOSA2011]>;342}343 344multiclass cxb_cond_alias<string cond, int condVal> {345 def : InstAlias<"cxb" # cond # " $rs1, $rs2, $imm",346 (CXBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,347 Requires<[HasOSA2011]>;348 def : InstAlias<"cxb" # cond # " $rs1, $simm5, $imm",349 (CXBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,350 Requires<[HasOSA2011]>;351}352 353defm : int_cond_alias<"a", 0b1000>;354defm : int_cond_alias<"n", 0b0000>;355defm : int_cond_alias<"ne", 0b1001>;356defm : int_cond_alias<"e", 0b0001>;357defm : int_cond_alias<"g", 0b1010>;358defm : int_cond_alias<"le", 0b0010>;359defm : int_cond_alias<"ge", 0b1011>;360defm : int_cond_alias<"l", 0b0011>;361defm : int_cond_alias<"gu", 0b1100>;362defm : int_cond_alias<"leu", 0b0100>;363defm : int_cond_alias<"cc", 0b1101>;364defm : int_cond_alias<"cs", 0b0101>;365defm : int_cond_alias<"pos", 0b1110>;366defm : int_cond_alias<"neg", 0b0110>;367defm : int_cond_alias<"vc", 0b1111>;368defm : int_cond_alias<"vs", 0b0111>;369let EmitPriority = 0 in370{371 defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual372 defm : int_cond_alias<"gt", 0b1010>; // same as g; gnu asm, not in manual373 defm : int_cond_alias<"lt", 0b0011>; // same as l; gnu asm, not in manual374 defm : int_cond_alias<"nz", 0b1001>; // same as ne375 defm : int_cond_alias<"eq", 0b0001>; // same as e376 defm : int_cond_alias<"z", 0b0001>; // same as e377 defm : int_cond_alias<"geu", 0b1101>; // same as cc378 defm : int_cond_alias<"lu", 0b0101>; // same as cs379}380defm : fp_cond_alias<"a", 0b1000>;381defm : fp_cond_alias<"n", 0b0000>;382defm : fp_cond_alias<"u", 0b0111>;383defm : fp_cond_alias<"g", 0b0110>;384defm : fp_cond_alias<"ug", 0b0101>;385defm : fp_cond_alias<"l", 0b0100>;386defm : fp_cond_alias<"ul", 0b0011>;387defm : fp_cond_alias<"lg", 0b0010>;388defm : fp_cond_alias<"ne", 0b0001>;389defm : fp_cond_alias<"e", 0b1001>;390defm : fp_cond_alias<"ue", 0b1010>;391defm : fp_cond_alias<"ge", 0b1011>;392defm : fp_cond_alias<"uge", 0b1100>;393defm : fp_cond_alias<"le", 0b1101>;394defm : fp_cond_alias<"ule", 0b1110>;395defm : fp_cond_alias<"o", 0b1111>;396let EmitPriority = 0 in397{398 defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual399 defm : fp_cond_alias<"nz", 0b0001>; // same as ne400 defm : fp_cond_alias<"z", 0b1001>; // same as e401}402 403defm : cp_cond_alias<"a", 0b1000>;404defm : cp_cond_alias<"n", 0b0000>;405defm : cp_cond_alias<"3", 0b0111>;406defm : cp_cond_alias<"2", 0b0110>;407defm : cp_cond_alias<"23", 0b0101>;408defm : cp_cond_alias<"1", 0b0100>;409defm : cp_cond_alias<"13", 0b0011>;410defm : cp_cond_alias<"12", 0b0010>;411defm : cp_cond_alias<"123", 0b0001>;412defm : cp_cond_alias<"0", 0b1001>;413defm : cp_cond_alias<"03", 0b1010>;414defm : cp_cond_alias<"02", 0b1011>;415defm : cp_cond_alias<"023", 0b1100>;416defm : cp_cond_alias<"01", 0b1101>;417defm : cp_cond_alias<"013", 0b1110>;418defm : cp_cond_alias<"012", 0b1111>;419let EmitPriority = 0 in defm : cp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual420 421defm : reg_cond_alias<"z", 0b001>;422defm : reg_cond_alias<"e", 0b001>;423defm : reg_cond_alias<"lez", 0b010>;424defm : reg_cond_alias<"lz", 0b011>;425defm : reg_cond_alias<"nz", 0b101>;426defm : reg_cond_alias<"ne", 0b101>;427defm : reg_cond_alias<"gz", 0b110>;428defm : reg_cond_alias<"gez", 0b111>;429 430defm : cwb_cond_alias<"ne", 0b1001>;431defm : cwb_cond_alias<"e", 0b0001>;432defm : cwb_cond_alias<"g", 0b1010>;433defm : cwb_cond_alias<"le", 0b0010>;434defm : cwb_cond_alias<"ge", 0b1011>;435defm : cwb_cond_alias<"l", 0b0011>;436defm : cwb_cond_alias<"gu", 0b1100>;437defm : cwb_cond_alias<"leu", 0b0100>;438defm : cwb_cond_alias<"cc", 0b1101>;439defm : cwb_cond_alias<"cs", 0b0101>;440defm : cwb_cond_alias<"pos", 0b1110>;441defm : cwb_cond_alias<"neg", 0b0110>;442defm : cwb_cond_alias<"vc", 0b1111>;443defm : cwb_cond_alias<"vs", 0b0111>;444let EmitPriority = 0 in {445 defm : cwb_cond_alias<"geu", 0b1101>; // same as cc446 defm : cwb_cond_alias<"lu", 0b0101>; // same as cs447}448 449defm : cxb_cond_alias<"ne", 0b1001>;450defm : cxb_cond_alias<"e", 0b0001>;451defm : cxb_cond_alias<"g", 0b1010>;452defm : cxb_cond_alias<"le", 0b0010>;453defm : cxb_cond_alias<"ge", 0b1011>;454defm : cxb_cond_alias<"l", 0b0011>;455defm : cxb_cond_alias<"gu", 0b1100>;456defm : cxb_cond_alias<"leu", 0b0100>;457defm : cxb_cond_alias<"cc", 0b1101>;458defm : cxb_cond_alias<"cs", 0b0101>;459defm : cxb_cond_alias<"pos", 0b1110>;460defm : cxb_cond_alias<"neg", 0b0110>;461defm : cxb_cond_alias<"vc", 0b1111>;462defm : cxb_cond_alias<"vs", 0b0111>;463let EmitPriority = 0 in {464 defm : cxb_cond_alias<"geu", 0b1101>; // same as cc465 defm : cxb_cond_alias<"lu", 0b0101>; // same as cs466}467 468// Section A.3 Synthetic Instructions469 470// Most are marked as Emit=0, so that they are not used for disassembly. This is471// an aesthetic issue, but the chosen policy is to typically prefer using the472// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,473// call, tst, ret, retl.474 475// Note: jmp/call/ret/retl have special case handling for output in476// SparcInstPrinter.cpp477 478// cmp rs1, reg_or_imm -> subcc rs1, reg_or_imm, %g0479def : InstAlias<"cmp $rs1, $rs2", (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2)>;480def : InstAlias<"cmp $rs1, $imm", (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm)>;481 482// jmp addr -> jmpl addr, %g0483def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;484def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;485 486// call addr -> jmpl addr, %o7487def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;488def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;489 490// tst reg -> orcc %g0, reg, %g0491def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;492 493// ret -> jmpl %i7+8, %g0 (aka RET 8)494def : InstAlias<"ret", (RET 8)>;495 496// retl -> jmpl %o7+8, %g0 (aka RETL 8)497def : InstAlias<"retl", (RETL 8)>;498 499// restore -> restore %g0, %g0, %g0500def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;501 502// save -> restore %g0, %g0, %g0503def : InstAlias<"save", (SAVErr G0, G0, G0)>;504 505// set value, rd506// (turns into a sequence of sethi+or, depending on the value)507// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;508def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;509 510// setsw value, rd511// (turns into a sequence of sethi+or+sra, depending on the value)512def SETSW : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "setsw $val, $rd">, Requires<[HasV9]>;513 514// setx value, tmp, rd515// (turns into a sequence of sethi+or+shift, depending on the value)516def SETX : AsmPseudoInst<(outs I64Regs:$rd),517 (ins i64imm:$val, I64Regs:$tmp),518 "setx $val, $tmp, $rd">,519 Requires<[Is64Bit, HasV9]>;520 521// not rd -> xnor rd, %g0, rd522def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;523 524// not reg, rd -> xnor reg, %g0, rd525def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;526 527// neg rd -> sub %g0, rd, rd528def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;529 530// neg reg, rd -> sub %g0, reg, rd531def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;532 533let Predicates = [HasV9] in {534 // cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd535 def : InstAlias<"cas [$rs1], $rs2, $rd",536 (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80)>;537 538 // casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd539 def : InstAlias<"casl [$rs1], $rs2, $rd",540 (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88)>;541 542 // casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd543 def : InstAlias<"casx [$rs1], $rs2, $rd",544 (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80)>;545 546 // casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd547 def : InstAlias<"casxl [$rs1], $rs2, $rd",548 (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88)>;549}550 551// inc rd -> add rd, 1, rd552def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;553 554// inc simm13, rd -> add rd, simm13, rd555def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;556 557// inccc rd -> addcc rd, 1, rd558def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;559 560// inccc simm13, rd -> addcc rd, simm13, rd561def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;562 563// dec rd -> sub rd, 1, rd564def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;565 566// dec simm13, rd -> sub rd, simm13, rd567def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;568 569// deccc rd -> subcc rd, 1, rd570def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;571 572// deccc simm13, rd -> subcc rd, simm13, rd573def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;574 575// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0576def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;577def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, simm13Op:$simm13), 0>;578 579// bset reg_or_imm, rd -> or rd,reg_or_imm,rd580def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;581def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;582 583// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd584def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;585def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;586 587// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd588def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;589def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;590 591 592// clr rd -> or %g0, %g0, rd593def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;594 595// clr{b,h,} [addr] -> st{b,h,} %g0, [addr]596def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;597def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;598def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;599def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;600def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;601def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;602 603 604// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd605def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;606def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, simm13Op:$simm13)>;607 608// mov specialreg, rd -> rd specialreg, rd609def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;610def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;611def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;612def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;613 614// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg615def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;616def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;617def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;618def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;619def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;620def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;621def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;622def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;623 624// End of Section A.3625 626 627// Nonstandard GNU extensions.628let EmitPriority = 0 in {629 // or imm, reg, rd -> or reg, imm, rd630 def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;631 632 // addc/addx imm, reg, rd -> addc/addx reg, imm, rd633 def : InstAlias<"addx $simm13, $rs1, $rd", (ADDCri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;634}635 636// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg637// (aka: omit the first arg when it's g0. This is not in the manual, but is638// supported by gnu and solaris as)639def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;640def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;641def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;642def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;643def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;644def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;645def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;646def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;647 648def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;649def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, simm13Op:$simm13), 0>;650 651// wrpr %reg, %rd -> wrpr %reg, %g0, %rd652// wrpr imm, %rd -> wrpr %g0, imm, %rd653// Nonstandard GNU extensions.654let Predicates = [HasV9] in {655 def : InstAlias<"wrpr $rs1, $rd", (WRPRrr PRRegs:$rd, IntRegs:$rs1, G0), 0>;656 def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, simm13Op:$simm13), 0>;657}658 659// flush -> flush %g0660def : InstAlias<"flush", (FLUSH), 0>;661 662// unimp -> unimp 0663def : InstAlias<"unimp", (UNIMP 0), 0>;664 665// Not in spec, but we follow Solaris behavior of having `illtrap`666// interchangeable with `unimp` all the time.667def : MnemonicAlias<"illtrap", "unimp">;668 669def : MnemonicAlias<"setuw", "set">, Requires<[HasV9]>;670 671def : MnemonicAlias<"iflush", "flush">;672 673def : MnemonicAlias<"stub", "stb">;674def : MnemonicAlias<"stsb", "stb">;675 676def : MnemonicAlias<"stuba", "stba">;677def : MnemonicAlias<"stsba", "stba">;678 679def : MnemonicAlias<"stuh", "sth">;680def : MnemonicAlias<"stsh", "sth">;681 682def : MnemonicAlias<"stuha", "stha">;683def : MnemonicAlias<"stsha", "stha">;684 685def : MnemonicAlias<"stw", "st">, Requires<[HasV9]>;686def : MnemonicAlias<"stuw", "st">, Requires<[HasV9]>;687def : MnemonicAlias<"stsw", "st">, Requires<[HasV9]>;688 689def : MnemonicAlias<"stwa", "sta">, Requires<[HasV9]>;690def : MnemonicAlias<"stuwa", "sta">, Requires<[HasV9]>;691def : MnemonicAlias<"stswa", "sta">, Requires<[HasV9]>;692 693def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;694def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;695 696def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;697 698def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;699def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;700 701def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;702def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;703 704 705def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;706def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;707def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,708 Requires<[HasHardQuad]>;709 710def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;711def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,712 DFPRegs:$rs2)>;713def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,714 QFPRegs:$rs2)>,715 Requires<[HasHardQuad]>;716 717// signx rd -> sra rd, %g0, rd718def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;719 720// signx reg, rd -> sra reg, %g0, rd721def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;722 723// sir -> sir 0724def : InstAlias<"sir", (SIR 0), 0>;725 726// pause reg_or_imm -> wrasr %g0, reg_or_imm, %asr27727let Predicates = [HasOSA2011] in {728 def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2), 1>;729 def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13), 1>;730} // Predicates = [HasOSA2011]731