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1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,10 InstrItinClass itin = NoItinerary>11 : Instruction {12 field bits<32> Inst;13 14 let Namespace = "SP";15 let Size = 4;16 17 bits<2> op;18 let Inst{31-30} = op; // Top two bits are the 'op' field19 20 dag OutOperandList = outs;21 dag InOperandList = ins;22 let AsmString = asmstr;23 let Pattern = pattern;24 25 let DecoderNamespace = "Sparc";26 27 let Itinerary = itin;28}29 30//===----------------------------------------------------------------------===//31// Format #2 instruction classes in the Sparc32//===----------------------------------------------------------------------===//33 34// Format 2 instructions35class F2<dag outs, dag ins, string asmstr, list<dag> pattern,36 InstrItinClass itin = NoItinerary>37 : InstSP<outs, ins, asmstr, pattern, itin> {38 bits<3> op2;39 bits<22> imm22;40 let op = 0; // op = 041 let Inst{24-22} = op2;42 let Inst{21-0} = imm22;43}44 45// Specific F2 classes: SparcV8 manual, page 4446//47class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,48 InstrItinClass itin = NoItinerary>49 : F2<outs, ins, asmstr, pattern, itin> {50 bits<5> rd;51 52 let op2 = op2Val;53 54 let Inst{29-25} = rd;55}56 57class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,58 list<dag> pattern, InstrItinClass itin = NoItinerary>59 : F2<outs, ins, asmstr, pattern, itin> {60 bits<4> cond;61 let op2 = op2Val;62 63 let Inst{29} = annul;64 let Inst{28-25} = cond;65}66 67class F2_3<bits<3> op2Val, bit annul, bit pred,68 dag outs, dag ins, string asmstr, list<dag> pattern,69 InstrItinClass itin = NoItinerary>70 : InstSP<outs, ins, asmstr, pattern, itin> {71 bits<2> cc;72 bits<4> cond;73 bits<19> imm19;74 75 let op = 0; // op = 076 77 let Inst{29} = annul;78 let Inst{28-25} = cond;79 let Inst{24-22} = op2Val;80 let Inst{21-20} = cc;81 let Inst{19} = pred;82 let Inst{18-0} = imm19;83}84 85class F2_4<bit annul, bit pred, dag outs, dag ins,86 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>87 : InstSP<outs, ins, asmstr, pattern, itin> {88 bits<16> imm16;89 bits<5> rs1;90 bits<3> rcond;91 92 let op = 0; // op = 093 94 let Inst{29} = annul;95 let Inst{28} = 0;96 let Inst{27-25} = rcond;97 let Inst{24-22} = 0b011;98 let Inst{21-20} = imm16{15-14};99 let Inst{19} = pred;100 let Inst{18-14} = rs1;101 let Inst{13-0} = imm16{13-0};102}103 104class F2_5<bit cc, dag outs, dag ins, string asmstr,105 list<dag> pattern = [], InstrItinClass itin = NoItinerary>106 : InstSP<outs, ins, asmstr, pattern, itin> {107 bits<10> imm10;108 bits<5> rs1;109 bits<5> rs2;110 bits<4> cond;111 112 let op = 0; // op = 0113 114 let Inst{29} = cond{3};115 let Inst{28} = 1;116 let Inst{27-25} = cond{2-0};117 let Inst{24-22} = 0b011;118 let Inst{21} = cc;119 let Inst{20-19} = imm10{9-8};120 let Inst{18-14} = rs1;121 let Inst{13} = 0; // i = 0122 let Inst{12-5} = imm10{7-0};123 let Inst{4-0} = rs2;124}125 126class F2_6<bit cc, dag outs, dag ins, string asmstr,127 list<dag> pattern = [], InstrItinClass itin = NoItinerary>128 : InstSP<outs, ins, asmstr, pattern, itin> {129 bits<10> imm10;130 bits<5> rs1;131 bits<5> simm5;132 bits<4> cond;133 134 let op = 0; // op = 0135 136 let Inst{29} = cond{3};137 let Inst{28} = 1;138 let Inst{27-25} = cond{2-0};139 let Inst{24-22} = 0b011;140 let Inst{21} = cc;141 let Inst{20-19} = imm10{9-8};142 let Inst{18-14} = rs1;143 let Inst{13} = 1; // i = 1144 let Inst{12-5} = imm10{7-0};145 let Inst{4-0} = simm5;146}147 148//===----------------------------------------------------------------------===//149// Format #3 instruction classes in the Sparc150//===----------------------------------------------------------------------===//151 152class F3<dag outs, dag ins, string asmstr, list<dag> pattern,153 InstrItinClass itin = NoItinerary>154 : InstSP<outs, ins, asmstr, pattern, itin> {155 bits<5> rd;156 bits<6> op3;157 bits<5> rs1;158 let op{1} = 1; // Op = 2 or 3159 let Inst{29-25} = rd;160 let Inst{24-19} = op3;161 let Inst{18-14} = rs1;162}163 164// Specific F3 classes: SparcV8 manual, page 44165//166class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,167 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>168 : F3<outs, ins, asmstr, pattern, itin> {169 bits<8> asi;170 bits<5> rs2;171 172 let op = opVal;173 let op3 = op3val;174 175 let Inst{13} = 0; // i field = 0176 let Inst{12-5} = asi; // address space identifier177 let Inst{4-0} = rs2;178}179 180// CAS instructions does not use an immediate even when i=1181class F3_1_cas_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,182 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>183 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {184 let asi = 0;185 let Inst{13} = 1; // i field = 1186}187 188class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,189 list<dag> pattern, InstrItinClass itin = IIC_iu_instr>190 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {191 let asi = 0;192}193 194class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,195 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>196 : F3<outs, ins, asmstr, pattern, itin> {197 bits<13> simm13;198 199 let op = opVal;200 let op3 = op3val;201 202 let Inst{13} = 1; // i field = 1203 let Inst{12-0} = simm13;204}205 206// floating-point207class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,208 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>209 : F3<outs, ins, asmstr, pattern, itin> {210 bits<5> rs2;211 212 let op = opVal;213 let op3 = op3val;214 215 let Inst{13-5} = opfval; // fp opcode216 let Inst{4-0} = rs2;217}218 219// floating-point unary operations.220class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,221 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>222 : F3<outs, ins, asmstr, pattern, itin> {223 bits<5> rs2;224 225 let op = opVal;226 let op3 = op3val;227 let rs1 = 0;228 229 let Inst{13-5} = opfval; // fp opcode230 let Inst{4-0} = rs2;231}232 233// floating-point compares.234class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,235 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>236 : F3<outs, ins, asmstr, pattern, itin> {237 bits<5> rs2;238 239 let op = opVal;240 let op3 = op3val;241 242 let Inst{13-5} = opfval; // fp opcode243 let Inst{4-0} = rs2;244}245 246// SIAM instruction247class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,248 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>249 : F3<outs, ins, asmstr, pattern, itin> {250 bits<3> mode;251 252 let op = opVal;253 let op3 = op3val;254 let rd = 0;255 let rs1 = 0;256 let Inst{13-5} = opfval; // fp opcode257 let Inst{4-3} = 0;258 let Inst{2-0} = mode;259}260 261// Shift by register rs2.262class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,263 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>264 : F3<outs, ins, asmstr, pattern, itin> {265 bit x = xVal; // 1 for 64-bit shifts.266 bits<5> rs2;267 268 let op = opVal;269 let op3 = op3val;270 271 let Inst{13} = 0; // i field = 0272 let Inst{12} = x; // extended registers.273 let Inst{4-0} = rs2;274}275 276// Shift by immediate.277class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,278 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>279 : F3<outs, ins, asmstr, pattern, itin> {280 bit x = xVal; // 1 for 64-bit shifts.281 bits<6> shcnt; // shcnt32 / shcnt64.282 283 let op = opVal;284 let op3 = op3val;285 286 let Inst{13} = 1; // i field = 1287 let Inst{12} = x; // extended registers.288 let Inst{5-0} = shcnt;289}290 291// Define rr and ri shift instructions with patterns.292multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,293 ValueType VT, Operand SIT, RegisterClass RC,294 InstrItinClass itin = IIC_iu_instr> {295 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),296 !strconcat(OpcStr, " $rs1, $rs2, $rd"),297 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],298 itin>;299 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, SIT:$shcnt),300 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),301 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))],302 itin>;303}304 305// 4-operand instructions.306class F3_4<bits<6> op3val, bits<4> op5val, dag outs, dag ins,307 string asmstr, list<dag> pattern = [], InstrItinClass itin = NoItinerary>308 : F3<outs, ins, asmstr, pattern, itin> {309 bits<4> op5;310 bits<5> rs3;311 bits<5> rs2;312 313 let op = 2;314 let op3 = op3val;315 let op5 = op5val;316 317 let Inst{13-9} = rs3;318 let Inst{8-5} = op5;319 let Inst{4-0} = rs2;320}321 322class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,323 InstrItinClass itin = NoItinerary>324 : InstSP<outs, ins, asmstr, pattern, itin> {325 bits<5> rd;326 327 let op = 2;328 let Inst{29-25} = rd;329 let Inst{24-19} = op3;330}331 332 333class F4_1<bits<6> op3, dag outs, dag ins,334 string asmstr, list<dag> pattern,335 InstrItinClass itin = NoItinerary>336 : F4<op3, outs, ins, asmstr, pattern, itin> {337 bit intcc;338 bits<2> cc;339 bits<4> cond;340 bits<5> rs2;341 342 let Inst{4-0} = rs2;343 let Inst{12-11} = cc;344 let Inst{13} = 0;345 let Inst{17-14} = cond;346 let Inst{18} = intcc;347}348 349class F4_2<bits<6> op3, dag outs, dag ins,350 string asmstr, list<dag> pattern,351 InstrItinClass itin = NoItinerary>352 : F4<op3, outs, ins, asmstr, pattern, itin> {353 bit intcc;354 bits<2> cc;355 bits<4> cond;356 bits<11> simm11;357 358 let Inst{10-0} = simm11;359 let Inst{12-11} = cc;360 let Inst{13} = 1;361 let Inst{17-14} = cond;362 let Inst{18} = intcc;363}364 365class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,366 string asmstr, list<dag> pattern,367 InstrItinClass itin = NoItinerary>368 : F4<op3, outs, ins, asmstr, pattern, itin> {369 bits<4> cond;370 bit intcc;371 bits<2> opf_cc;372 bits<5> rs2;373 374 let Inst{18} = 0;375 let Inst{17-14} = cond;376 let Inst{13} = intcc;377 let Inst{12-11} = opf_cc;378 let Inst{10-5} = opf_low;379 let Inst{4-0} = rs2;380}381 382class F4_4r<bits<6> op3, bits<5> opf_low, dag outs, dag ins,383 string asmstr, list<dag> pattern,384 InstrItinClass itin = NoItinerary>385 : F4<op3, outs, ins, asmstr, pattern, itin> {386 bits<5> rs1;387 bits<5> rs2;388 bits<3> rcond;389 let Inst{18-14} = rs1;390 let Inst{13} = 0; // IsImm391 let Inst{12-10} = rcond;392 let Inst{9-5} = opf_low;393 let Inst{4-0} = rs2;394}395 396 397class F4_4i<bits<6> op3, dag outs, dag ins,398 string asmstr, list<dag> pattern,399 InstrItinClass itin = NoItinerary>400 : F4<op3, outs, ins, asmstr, pattern, itin> {401 bits<5> rs1;402 bits<10> simm10;403 bits<3> rcond;404 let Inst{18-14} = rs1;405 let Inst{13} = 1; // IsImm406 let Inst{12-10} = rcond;407 let Inst{9-0} = simm10;408}409 410 411class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins,412 string asmstr, list<dag> pattern,413 InstrItinClass itin = NoItinerary>414 : F3<outs, ins, asmstr, pattern, itin> {415 bits<4> cond;416 bits<2> cc;417 418 let op = 0b10;419 let rd{4} = 0;420 let rd{3-0} = cond;421 let op3 = op3Val;422 let Inst{13} = isimm;423 let Inst{12-11} = cc;424 425}426 427class TRAPSPrr<bits<6> op3Val, dag outs, dag ins,428 string asmstr, list<dag> pattern,429 InstrItinClass itin = NoItinerary>430 : TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> {431 bits<5> rs2;432 433 let Inst{10-5} = 0;434 let Inst{4-0} = rs2;435}436 437class TRAPSPri<bits<6> op3Val, dag outs, dag ins,438 string asmstr, list<dag> pattern,439 InstrItinClass itin = NoItinerary>440 : TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> {441 bits<8> imm;442 443 let Inst{10-8} = 0;444 let Inst{7-0} = imm;445}446 447// Pseudo-instructions for alternate assembly syntax (never used by codegen).448// These are aliases that require C++ handling to convert to the target449// instruction, while InstAliases can be handled directly by tblgen.450class AsmPseudoInst<dag outs, dag ins, string asm>451 : InstSP<outs, ins, asm, []> {452 let isPseudo = 1;453}454