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1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Sparc instructions in TableGen format.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Instruction format superclass15//===----------------------------------------------------------------------===//16 17include "SparcInstrFormats.td"18 19//===----------------------------------------------------------------------===//20// Feature predicates.21//===----------------------------------------------------------------------===//22 23// True when generating 32-bit code.24def Is32Bit : Predicate<"!Subtarget->is64Bit()">;25 26// True when generating 64-bit code. This also implies HasV9.27def Is64Bit : Predicate<"Subtarget->is64Bit()">,28 AssemblerPredicate<(all_of FeatureV9)>;29 30def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,31 AssemblerPredicate<(all_of FeatureSoftMulDiv)>;32 33// HasV9 - This predicate is true when the target processor supports V934// instructions. Note that the machine may be running in 32-bit mode.35def HasV9 : Predicate<"Subtarget->isV9()">,36 AssemblerPredicate<(all_of FeatureV9)>;37 38// HasNoV9 - This predicate is true when the target doesn't have V939// instructions. Use of this is just a hack for the isel not having proper40// costs for V8 instructions that are more expensive than their V9 ones.41def HasNoV9 : Predicate<"!Subtarget->isV9()">;42 43// HasVIS - This is true when the target processor has VIS extensions.44def HasVIS : Predicate<"Subtarget->isVIS()">,45 AssemblerPredicate<(all_of FeatureVIS)>;46def HasVIS2 : Predicate<"Subtarget->isVIS2()">,47 AssemblerPredicate<(all_of FeatureVIS2)>;48def HasVIS3 : Predicate<"Subtarget->isVIS3()">,49 AssemblerPredicate<(all_of FeatureVIS3)>;50 51// HasUA2005 - This is true when the target processor has UA 2005 extensions.52def HasUA2005 : Predicate<"Subtarget->isUA2005()">,53 AssemblerPredicate<(all_of FeatureUA2005)>;54 55// HasUA2007 - This is true when the target processor has UA 2007 extensions.56def HasUA2007 : Predicate<"Subtarget->isUA2007()">,57 AssemblerPredicate<(all_of FeatureUA2007)>;58 59// HasOSA2011 - This is true when the target processor has OSA 2011 extensions.60def HasOSA2011 : Predicate<"Subtarget->isOSA2011()">,61 AssemblerPredicate<(all_of FeatureOSA2011)>;62 63// HasCrypto - This is true when the target processor has cryptographic extensions.64def HasCrypto : Predicate<"Subtarget->isCrypto()">,65 AssemblerPredicate<(all_of FeatureCrypto)>;66 67// HasHardQuad - This is true when the target processor supports quad floating68// point instructions.69def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;70 71// HasLeonCASA - This is true when the target processor supports the Leon CASA72// instruction.73def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;74 75// HasCASA - This is true when the target processor supports CASA instruction.76def HasCASA : Predicate<"Subtarget->hasLeonCasa() || Subtarget->isV9()">,77 AssemblerPredicate<(any_of LeonCASA, FeatureV9)>;78 79// HasPWRPSR - This is true when the target processor supports partial80// writes to the PSR register that only affects the ET field.81def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">,82 AssemblerPredicate<(all_of FeaturePWRPSR)>;83 84// HasUMAC_SMAC - This is true when the target processor supports the85// UMAC and SMAC instructions86def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;87 88def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">;89def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">;90def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;91 92// UseDeprecatedInsts - This predicate is true when the target processor is a93// V8, or when it is V9 but the V8 deprecated instructions are efficient enough94// to use when appropriate. In either of these cases, the instruction selector95// will pick deprecated instructions.96def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;97 98//===----------------------------------------------------------------------===//99// HwModes Pattern Stuff100//===----------------------------------------------------------------------===//101 102defvar SPARC32 = DefaultMode;103def SPARC64 : HwMode<[Is64Bit]>;104 105//===----------------------------------------------------------------------===//106// Instruction Pattern Stuff107//===----------------------------------------------------------------------===//108 109def sparc_ptr_rc : RegClassByHwMode<110 [SPARC32, SPARC64],111 [IntRegs, I64Regs]>;112 113// Both cases can use the same decoder method, so avoid the dispatch114// by hwmode by setting an explicit DecoderMethod115def ptr_op : RegisterOperand<sparc_ptr_rc> {116 let DecoderMethod = "DecodeIntRegsRegisterClass";117}118 119// FIXME these should have AsmOperandClass.120def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;121 122def simm5 : PatLeaf<(imm), [{ return isInt<5>(N->getSExtValue()); }]>;123 124def simm10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;125 126def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;127 128def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;129 130def LO10 : SDNodeXForm<imm, [{131 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),132 MVT::i32);133}]>;134 135def HI22 : SDNodeXForm<imm, [{136 // Transformation function: shift the immediate value down into the low bits.137 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),138 MVT::i32);139}]>;140 141// Return the complement of a HI22 immediate value.142def HI22_not : SDNodeXForm<imm, [{143 return CurDAG->getTargetConstant(~(unsigned)N->getZExtValue() >> 10, SDLoc(N),144 MVT::i32);145}]>;146 147def SETHIimm : PatLeaf<(imm), [{148 return isShiftedUInt<22, 10>(N->getZExtValue());149}], HI22>;150 151// The N->hasOneUse() prevents the immediate from being instantiated in both152// normal and complement form.153def SETHIimm_not : PatLeaf<(i32 imm), [{154 return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue());155}], HI22_not>;156 157// Addressing modes.158def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;159def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [], []>;160 161// Constrained operands for the shift operations.162class ShiftAmtImmAsmOperand<int Bits> : AsmOperandClass {163 let Name = "ShiftAmtImm" # Bits;164 let ParserMethod = "parseShiftAmtImm<" # Bits # ">";165}166def shift_imm5 : Operand<i32> {167 let ParserMatchClass = ShiftAmtImmAsmOperand<5>;168}169def shift_imm6 : Operand<i32> {170 let ParserMatchClass = ShiftAmtImmAsmOperand<6>;171}172 173// Address operands174def SparcMEMrrAsmOperand : AsmOperandClass {175 let Name = "MEMrr";176 let ParserMethod = "parseMEMOperand";177}178 179def SparcMEMriAsmOperand : AsmOperandClass {180 let Name = "MEMri";181 let ParserMethod = "parseMEMOperand";182}183 184def simm5Op : Operand<iPTR> {185 let OperandType = "OPERAND_IMMEDIATE";186 let DecoderMethod = "DecodeSIMM5";187 let EncoderMethod = "getSImm5OpValue";188}189 190def simm13Op : Operand<iPTR> {191 let OperandType = "OPERAND_IMMEDIATE";192 let DecoderMethod = "DecodeSIMM13";193 let EncoderMethod = "getSImm13OpValue";194}195 196def MEMrr : Operand<iPTR> {197 let PrintMethod = "printMemOperand";198 let MIOperandInfo = (ops ptr_op, ptr_op);199 let ParserMatchClass = SparcMEMrrAsmOperand;200}201def MEMri : Operand<iPTR> {202 let PrintMethod = "printMemOperand";203 let MIOperandInfo = (ops ptr_op, simm13Op);204 let ParserMatchClass = SparcMEMriAsmOperand;205}206 207// Represents a tail relocation operand for instructions such as add, ld, call.208class SparcTailRelocSymAsmOperand<string Kind> : AsmOperandClass {209 let Name = "TailRelocSym" # Kind;210 let RenderMethod = "addTailRelocSymOperands";211 let PredicateMethod = "isTailRelocSym";212 let ParserMethod = "parseTailRelocSym<TailRelocKind::" # Kind # ">";213}214 215def TailRelocSymGOTLoad : Operand<iPTR> {216 let ParserMatchClass = SparcTailRelocSymAsmOperand<"Load_GOT">;217}218 219def TailRelocSymTLSAdd : Operand<iPTR> {220 let ParserMatchClass = SparcTailRelocSymAsmOperand<"Add_TLS">;221}222 223def TailRelocSymTLSLoad : Operand<iPTR> {224 let ParserMatchClass = SparcTailRelocSymAsmOperand<"Load_TLS">;225}226 227def TailRelocSymTLSCall : Operand<iPTR> {228 let ParserMatchClass = SparcTailRelocSymAsmOperand<"Call_TLS">;229}230 231def SparcMembarTagAsmOperand : AsmOperandClass {232 let Name = "MembarTag";233 let ParserMethod = "parseMembarTag";234}235 236def MembarTag : Operand<i32> {237 let PrintMethod = "printMembarTag";238 let ParserMatchClass = SparcMembarTagAsmOperand;239}240 241def SparcASITagAsmOperand : AsmOperandClass {242 let Name = "ASITag";243 let ParserMethod = "parseASITag";244}245 246def ASITag : Operand<i32> {247 let PrintMethod = "printASITag";248 let ParserMatchClass = SparcASITagAsmOperand;249}250 251def SparcPrefetchTagAsmOperand : AsmOperandClass {252 let Name = "PrefetchTag";253 let ParserMethod = "parsePrefetchTag";254}255 256def PrefetchTag : Operand<i32> {257 let PrintMethod = "printPrefetchTag";258 let ParserMatchClass = SparcPrefetchTagAsmOperand;259}260 261// Branch targets have OtherVT type.262def brtarget : Operand<OtherVT> {263 let EncoderMethod = "getBranchTargetOpValue";264 let DecoderMethod = "DecodeDisp<22>";265 let PrintMethod = "printCTILabel";266 let OperandType = "OPERAND_PCREL";267}268 269def bprtarget : Operand<OtherVT> {270 let EncoderMethod = "getBranchPredTargetOpValue";271 let DecoderMethod = "DecodeDisp<19>";272 let PrintMethod = "printCTILabel";273 let OperandType = "OPERAND_PCREL";274}275 276def bprtarget16 : Operand<OtherVT> {277 let EncoderMethod = "getBranchOnRegTargetOpValue";278 let DecoderMethod = "DecodeDisp<16>";279 let PrintMethod = "printCTILabel";280 let OperandType = "OPERAND_PCREL";281}282 283def cbtarget : Operand<OtherVT> {284 let EncoderMethod = "getCompareAndBranchTargetOpValue";285 let DecoderMethod = "DecodeDisp<10>";286 let PrintMethod = "printCTILabel";287 let OperandType = "OPERAND_PCREL";288}289 290def SparcCallTargetAsmOperand : AsmOperandClass {291 let Name = "CallTarget";292 let ParserMethod = "parseCallTarget";293}294 295def calltarget : Operand<i32> {296 let EncoderMethod = "getCallTargetOpValue";297 let DecoderMethod = "DecodeCall";298 let ParserMatchClass = SparcCallTargetAsmOperand;299 let PrintMethod = "printCTILabel";300 let OperandType = "OPERAND_PCREL";301}302 303// Operand for printing out a condition code.304let PrintMethod = "printCCOperand" in {305 def CCOp : Operand<i32>;306 def RegCCOp : Operand<i32>;307}308 309def SDTSPcmpicc :310SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;311def SDTSPcmpfcc :312SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;313def SDTSPbrcc :314SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;315def SDTSPbrreg :316SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, SDTCisVT<2, i64>]>;317def SDTSPselectcc :318SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;319def SDTSPselectreg :320SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>, SDTCisVT<4, i64>]>;321def SDTSPFTOI :322SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;323def SDTSPITOF :324SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;325def SDTSPFTOX :326SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;327def SDTSPXTOF :328SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;329 330def SDTSPtlsadd :331SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;332def SDTSPtlsld :333SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;334 335def SDTSPloadgdop :336SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;337 338def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;339def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;340def SPcmpfccv9 : SDNode<"SPISD::CMPFCC_V9", SDTSPcmpfcc, [SDNPOutGlue]>;341def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;342def SPbpicc : SDNode<"SPISD::BPICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;343def SPbpxcc : SDNode<"SPISD::BPXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;344def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;345def SPbrfccv9 : SDNode<"SPISD::BRFCC_V9", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;346def SPbrreg : SDNode<"SPISD::BR_REG", SDTSPbrreg, [SDNPHasChain]>;347 348def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;349def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;350 351def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;352def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;353def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;354def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;355 356def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;357def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;358def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;359def SPselectreg : SDNode<"SPISD::SELECT_REG", SDTSPselectreg>;360 361// These are target-independent nodes, but have target-specific formats.362def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,363 SDTCisVT<1, i32> ]>;364def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,365 SDTCisVT<1, i32> ]>;366 367def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,368 [SDNPHasChain, SDNPOutGlue]>;369def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,370 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;371 372def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;373def call : SDNode<"SPISD::CALL", SDT_SPCall,374 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,375 SDNPVariadic]>;376 377def tailcall : SDNode<"SPISD::TAIL_CALL", SDT_SPCall,378 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;379 380def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;381def retglue : SDNode<"SPISD::RET_GLUE", SDT_SPRet,382 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;383 384def global_base_reg : SDNode<"SPISD::GLOBAL_BASE_REG",385 SDTypeProfile<1, 0, [SDTCisVT<0, iPTR>]>>;386 387def flushw : SDNode<"SPISD::FLUSHW", SDTNone,388 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;389 390def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;391def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;392def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,393 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,394 SDNPVariadic]>;395 396def load_gdop : SDNode<"SPISD::LOAD_GDOP", SDTSPloadgdop>;397 398def getPCX : Operand<iPTR> {399 let PrintMethod = "printGetPCX";400}401 402//===----------------------------------------------------------------------===//403// SPARC Flag Conditions404//===----------------------------------------------------------------------===//405 406// Note that these values must be kept in sync with the CCOp::CondCode enum407// values.408class ICC_VAL<int N> : PatLeaf<(i32 N)>;409def ICC_NE : ICC_VAL< 9>; // Not Equal410def ICC_E : ICC_VAL< 1>; // Equal411def ICC_G : ICC_VAL<10>; // Greater412def ICC_LE : ICC_VAL< 2>; // Less or Equal413def ICC_GE : ICC_VAL<11>; // Greater or Equal414def ICC_L : ICC_VAL< 3>; // Less415def ICC_GU : ICC_VAL<12>; // Greater Unsigned416def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned417def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned418def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned419def ICC_POS : ICC_VAL<14>; // Positive420def ICC_NEG : ICC_VAL< 6>; // Negative421def ICC_VC : ICC_VAL<15>; // Overflow Clear422def ICC_VS : ICC_VAL< 7>; // Overflow Set423 424class FCC_VAL<int N> : PatLeaf<(i32 N)>;425def FCC_U : FCC_VAL<23>; // Unordered426def FCC_G : FCC_VAL<22>; // Greater427def FCC_UG : FCC_VAL<21>; // Unordered or Greater428def FCC_L : FCC_VAL<20>; // Less429def FCC_UL : FCC_VAL<19>; // Unordered or Less430def FCC_LG : FCC_VAL<18>; // Less or Greater431def FCC_NE : FCC_VAL<17>; // Not Equal432def FCC_E : FCC_VAL<25>; // Equal433def FCC_UE : FCC_VAL<26>; // Unordered or Equal434def FCC_GE : FCC_VAL<27>; // Greater or Equal435def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal436def FCC_LE : FCC_VAL<29>; // Less or Equal437def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal438def FCC_O : FCC_VAL<31>; // Ordered439 440class CPCC_VAL<int N> : PatLeaf<(i32 N)>;441def CPCC_3 : CPCC_VAL<39>; // 3442def CPCC_2 : CPCC_VAL<38>; // 2443def CPCC_23 : CPCC_VAL<37>; // 2 or 3444def CPCC_1 : CPCC_VAL<36>; // 1445def CPCC_13 : CPCC_VAL<35>; // 1 or 3446def CPCC_12 : CPCC_VAL<34>; // 1 or 2447def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3448def CPCC_0 : CPCC_VAL<41>; // 0449def CPCC_03 : CPCC_VAL<42>; // 0 or 3450def CPCC_02 : CPCC_VAL<43>; // 0 or 2451def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3452def CPCC_01 : CPCC_VAL<45>; // 0 or 1453def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3454def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2455 456class RegCC_VAL<int N> : PatLeaf<(i32 N)>;457def RegCC_Z : RegCC_VAL<49>; // Zero458def RegCC_LEZ : RegCC_VAL<50>; // Lees or equal than zero459def RegCC_LZ : RegCC_VAL<51>; // Less than zero460def RegCC_NZ : RegCC_VAL<53>; // Not zero461def RegCC_GZ : RegCC_VAL<54>; // Greater than zero462def RegCC_GEZ : RegCC_VAL<55>; // Greater or equal to zero463 464//===----------------------------------------------------------------------===//465// Instruction Class Templates466//===----------------------------------------------------------------------===//467 468/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.469multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,470 RegisterClass RC, ValueType Ty, Operand immOp,471 InstrItinClass itin = IIC_iu_instr> {472 def rr : F3_1<2, Op3Val,473 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),474 !strconcat(OpcStr, " $rs1, $rs2, $rd"),475 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],476 itin>;477 def ri : F3_2<2, Op3Val,478 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),479 !strconcat(OpcStr, " $rs1, $simm13, $rd"),480 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],481 itin>;482}483 484/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no485/// pattern.486multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {487 def rr : F3_1<2, Op3Val,488 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),489 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],490 itin>;491 def ri : F3_2<2, Op3Val,492 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),493 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],494 itin>;495}496 497// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.498multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,499 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> {500 def rr : F3_1<3, Op3Val,501 (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr),502 !strconcat(OpcStr, " [$addr], $rd"),503 [(set Ty:$rd, (OpNode ADDRrr:$addr))],504 itin>;505 def ri : F3_2<3, Op3Val,506 (outs RC:$rd), (ins (MEMri $rs1, $simm13):$addr),507 !strconcat(OpcStr, " [$addr], $rd"),508 [(set Ty:$rd, (OpNode ADDRri:$addr))],509 itin>;510}511 512// TODO: Instructions of the LoadASI class are currently asm only; hooking up513// CodeGen's address spaces to use these is a future task.514multiclass LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> {515 def rr : F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),516 !strconcat(OpcStr, "a [$addr] $asi, $rd"),517 []>;518 519 let Predicates = [HasV9], Uses = [ASR3] in520 def ri : F3_2<3, Op3Val, (outs RC:$rd), (ins (MEMri $rs1, $simm13):$addr),521 !strconcat(OpcStr, "a [$addr] %asi, $rd"),522 []>;523}524 525// LoadA multiclass - As above, but also define alternate address space variant526multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,527 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,528 InstrItinClass itin = NoItinerary> :529 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {530 defm A : LoadASI<OpcStr, LoadAOp3Val, RC>;531}532 533// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.534multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,535 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {536 def rr : F3_1<3, Op3Val,537 (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd),538 !strconcat(OpcStr, " $rd, [$addr]"),539 [(OpNode Ty:$rd, ADDRrr:$addr)],540 itin>;541 def ri : F3_2<3, Op3Val,542 (outs), (ins (MEMri $rs1, $simm13):$addr, RC:$rd),543 !strconcat(OpcStr, " $rd, [$addr]"),544 [(OpNode Ty:$rd, ADDRri:$addr)],545 itin>;546}547 548// TODO: Instructions of the StoreASI class are currently asm only; hooking up549// CodeGen's address spaces to use these is a future task.550multiclass StoreASI<string OpcStr, bits<6> Op3Val, RegisterClass RC,551 InstrItinClass itin = IIC_st> {552 def rr : F3_1_asi<3, Op3Val, (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd, ASITag:$asi),553 !strconcat(OpcStr, "a $rd, [$addr] $asi"),554 [],555 itin>;556 557 let Predicates = [HasV9], Uses = [ASR3] in558 def ri : F3_2<3, Op3Val, (outs), (ins (MEMri $rs1, $simm13):$addr, RC:$rd),559 !strconcat(OpcStr, "a $rd, [$addr] %asi"),560 [],561 itin>;562}563 564multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,565 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :566 Store<OpcStr, Op3Val, OpNode, RC, Ty> {567 defm A : StoreASI<OpcStr, StoreAOp3Val, RC>;568}569 570//===----------------------------------------------------------------------===//571// Instructions572//===----------------------------------------------------------------------===//573 574// Pseudo instructions.575class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>576 : InstSP<outs, ins, asmstr, pattern> {577 let isCodeGenOnly = 1;578 let isPseudo = 1;579}580 581// Full memory barrier for V8.582def V8BAR : Pseudo<(outs), (ins), "!V8BAR", []>, Requires<[HasNoV9]>;583 584// GETPCX for PIC585let Defs = [O7] in {586 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;587}588 589let Defs = [O6], Uses = [O6] in {590def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),591 "!ADJCALLSTACKDOWN $amt1, $amt2",592 [(callseq_start timm:$amt1, timm:$amt2)]>;593def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),594 "!ADJCALLSTACKUP $amt1",595 [(callseq_end timm:$amt1, timm:$amt2)]>;596}597 598let hasSideEffects = 1, mayStore = 1 in {599 let rd = 0, rs1 = 0, rs2 = 0 in600 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),601 "flushw",602 [(flushw)]>, Requires<[HasV9]>;603 let rd = 8, rs1 = 0, simm13 = 3 in604 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),605 "ta 3",606 [(flushw)]>;607}608 609// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after610// instruction selection into a branch sequence. This has to handle all611// permutations of selection between i32/f32/f64 on ICC and FCC.612// Expanded after instruction selection.613let Uses = [ICC], usesCustomInserter = 1 in {614 def SELECT_CC_Int_ICC615 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),616 "; SELECT_CC_Int_ICC PSEUDO!",617 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;618 def SELECT_CC_FP_ICC619 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),620 "; SELECT_CC_FP_ICC PSEUDO!",621 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;622 623 def SELECT_CC_DFP_ICC624 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),625 "; SELECT_CC_DFP_ICC PSEUDO!",626 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;627 628 def SELECT_CC_QFP_ICC629 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),630 "; SELECT_CC_QFP_ICC PSEUDO!",631 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;632}633 634let Uses = [ICC], usesCustomInserter = 1 in {635 def SELECT_CC_Int_XCC636 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),637 "; SELECT_CC_Int_XCC PSEUDO!",638 [(set i32:$dst, (SPselectxcc i32:$T, i32:$F, imm:$Cond))]>;639 def SELECT_CC_FP_XCC640 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),641 "; SELECT_CC_FP_XCC PSEUDO!",642 [(set f32:$dst, (SPselectxcc f32:$T, f32:$F, imm:$Cond))]>;643 644 def SELECT_CC_DFP_XCC645 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),646 "; SELECT_CC_DFP_XCC PSEUDO!",647 [(set f64:$dst, (SPselectxcc f64:$T, f64:$F, imm:$Cond))]>;648 649 def SELECT_CC_QFP_XCC650 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),651 "; SELECT_CC_QFP_XCC PSEUDO!",652 [(set f128:$dst, (SPselectxcc f128:$T, f128:$F, imm:$Cond))]>;653}654 655let usesCustomInserter = 1, Uses = [FCC0] in {656 657 def SELECT_CC_Int_FCC658 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),659 "; SELECT_CC_Int_FCC PSEUDO!",660 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;661 662 def SELECT_CC_FP_FCC663 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),664 "; SELECT_CC_FP_FCC PSEUDO!",665 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;666 def SELECT_CC_DFP_FCC667 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),668 "; SELECT_CC_DFP_FCC PSEUDO!",669 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;670 def SELECT_CC_QFP_FCC671 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),672 "; SELECT_CC_QFP_FCC PSEUDO!",673 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;674}675 676// Section B.1 - Load Integer Instructions, p. 90677defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;678defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;679defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;680defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;681defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;682defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;683 684// Section B.2 - Load Floating-point Instructions, p. 92685defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>;686defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>;687 688let DecoderNamespace = "SparcV9", Predicates = [HasV9] in {689 defm LDFA : LoadASI<"ld", 0b110000, FPRegs>;690 defm LDDFA : LoadASI<"ldd", 0b110011, DFPRegs>;691 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,692 Requires<[HasHardQuad]>;693}694 695// Coprocessor instructions were removed in v9.696let DecoderNamespace = "SparcV8", Predicates = [HasNoV9] in {697 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;698 defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;699}700 701let Defs = [CPSR] in {702 let rd = 0 in {703 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins (MEMrr $rs1, $rs2):$addr),704 "ld [$addr], %csr", []>;705 def LDCSRri : F3_2<3, 0b110001, (outs), (ins (MEMri $rs1, $simm13):$addr),706 "ld [$addr], %csr", []>;707 }708}709 710let Defs = [FSR] in {711 let rd = 0 in {712 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),713 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;714 def LDFSRri : F3_2<3, 0b100001, (outs), (ins (MEMri $rs1, $simm13):$addr),715 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;716 }717 let rd = 1 in {718 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),719 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;720 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins (MEMri $rs1, $simm13):$addr),721 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;722 }723}724 725let mayLoad = 1, isAsmParserOnly = 1 in {726 def GDOP_LDrr : F3_1<3, 0b000000,727 (outs IntRegs:$rd),728 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym),729 "ld [$addr], $rd, $sym",730 [(set i32:$rd,731 (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>;732}733 734// Section B.4 - Store Integer Instructions, p. 95735defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;736defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;737defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;738defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>;739 740// Section B.5 - Store Floating-point Instructions, p. 97741defm STF : Store<"st", 0b100100, store, FPRegs, f32>;742defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>;743 744let DecoderNamespace = "SparcV9", Predicates = [HasV9] in {745 defm STFA : StoreASI<"st", 0b110100, FPRegs>;746 defm STDFA : StoreASI<"std", 0b110111, DFPRegs>;747 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,748 Requires<[HasHardQuad]>;749}750 751// Coprocessor instructions were removed in v9.752let DecoderNamespace = "SparcV8", Predicates = [HasNoV9] in {753 defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>;754 defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;755}756 757let rd = 0 in {758 let mayStore = 1, Uses = [CPSR] in {759 def STCSRrr : F3_1<3, 0b110101, (outs), (ins (MEMrr $rs1, $rs2):$addr),760 "st %csr, [$addr]", [], IIC_st>;761 def STCSRri : F3_2<3, 0b110101, (outs), (ins (MEMri $rs1, $simm13):$addr),762 "st %csr, [$addr]", [], IIC_st>;763 }764 let mayStore = 1, Uses = [CPQ] in {765 def STDCQrr : F3_1<3, 0b110110, (outs), (ins (MEMrr $rs1, $rs2):$addr),766 "std %cq, [$addr]", [], IIC_std>;767 def STDCQri : F3_2<3, 0b110110, (outs), (ins (MEMri $rs1, $simm13):$addr),768 "std %cq, [$addr]", [], IIC_std>;769 }770}771 772let rd = 0 in {773 let mayStore = 1, Uses = [FSR] in {774 def STFSRrr : F3_1<3, 0b100101, (outs), (ins (MEMrr $rs1, $rs2):$addr),775 "st %fsr, [$addr]", [], IIC_st>;776 def STFSRri : F3_2<3, 0b100101, (outs), (ins (MEMri $rs1, $simm13):$addr),777 "st %fsr, [$addr]", [], IIC_st>;778 }779 let mayStore = 1, Defs = [FQ] in {780 def STDFQrr : F3_1<3, 0b100110, (outs), (ins (MEMrr $rs1, $rs2):$addr),781 "std %fq, [$addr]", [], IIC_std>;782 def STDFQri : F3_2<3, 0b100110, (outs), (ins (MEMri $rs1, $simm13):$addr),783 "std %fq, [$addr]", [], IIC_std>;784 }785}786let rd = 1, mayStore = 1, Uses = [FSR] in {787 def STXFSRrr : F3_1<3, 0b100101, (outs), (ins (MEMrr $rs1, $rs2):$addr),788 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;789 def STXFSRri : F3_2<3, 0b100101, (outs), (ins (MEMri $rs1, $simm13):$addr),790 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;791}792 793// B.7. Atomic Load-Store Unsigned Byte Instructions794// (Atomic test-and-set)795// TODO look into the possibility to use this to implment `atomic_flag`.796// If it's possible, then LDSTUB is the preferred way to do it.797def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),798 "ldstub [$addr], $rd", []>;799def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),800 "ldstub [$addr], $rd", []>;801def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),802 (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),803 "ldstuba [$addr] $asi, $rd", []>;804let Predicates = [HasV9], Uses = [ASR3] in805def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),806 (ins (MEMri $rs1, $simm13):$addr),807 "ldstuba [$addr] %asi, $rd", []>;808 809// Section B.8 - SWAP Register with Memory Instruction810// (Atomic swap)811let Constraints = "$val = $rd" in {812 def SWAPrr : F3_1<3, 0b001111,813 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, IntRegs:$val),814 "swap [$addr], $rd",815 [(set i32:$rd, (atomic_swap_i32 ADDRrr:$addr, i32:$val))]>;816 def SWAPri : F3_2<3, 0b001111,817 (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr, IntRegs:$val),818 "swap [$addr], $rd",819 [(set i32:$rd, (atomic_swap_i32 ADDRri:$addr, i32:$val))]>;820 def SWAPArr : F3_1_asi<3, 0b011111,821 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, IntRegs:$val),822 "swapa [$addr] $asi, $rd",823 [/*FIXME: pattern?*/]>;824let Predicates = [HasV9], Uses = [ASR3] in825 def SWAPAri : F3_2<3, 0b011111,826 (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr, IntRegs:$val),827 "swapa [$addr] %asi, $rd",828 [/*FIXME: pattern?*/]>;829}830 831 832// Section B.9 - SETHI Instruction, p. 104833def SETHIi: F2_1<0b100,834 (outs IntRegs:$rd), (ins i32imm:$imm22),835 "sethi $imm22, $rd",836 [(set i32:$rd, SETHIimm:$imm22)],837 IIC_iu_instr>;838 839// Section B.10 - NOP Instruction, p. 105840// (It's a special case of SETHI)841let rd = 0, imm22 = 0 in842 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;843 844// Section B.11 - Logical Instructions, p. 106845defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;846 847def ANDNrr : F3_1<2, 0b000101,848 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),849 "andn $rs1, $rs2, $rd",850 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;851def ANDNri : F3_2<2, 0b000101,852 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),853 "andn $rs1, $simm13, $rd", []>;854 855defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;856 857def ORNrr : F3_1<2, 0b000110,858 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),859 "orn $rs1, $rs2, $rd",860 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;861def ORNri : F3_2<2, 0b000110,862 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),863 "orn $rs1, $simm13, $rd", []>;864defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;865 866def XNORrr : F3_1<2, 0b000111,867 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),868 "xnor $rs1, $rs2, $rd",869 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;870def XNORri : F3_2<2, 0b000111,871 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),872 "xnor $rs1, $simm13, $rd", []>;873 874def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2),875 (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;876 877def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2),878 (ORNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;879 880let Defs = [ICC] in {881 defm ANDCC : F3_12np<"andcc", 0b010001>;882 defm ANDNCC : F3_12np<"andncc", 0b010101>;883 defm ORCC : F3_12np<"orcc", 0b010010>;884 defm ORNCC : F3_12np<"orncc", 0b010110>;885 defm XORCC : F3_12np<"xorcc", 0b010011>;886 defm XNORCC : F3_12np<"xnorcc", 0b010111>;887}888 889// Section B.12 - Shift Instructions, p. 107890defm SLL : F3_S<"sll", 0b100101, 0, shl, i32, shift_imm5, IntRegs>;891defm SRL : F3_S<"srl", 0b100110, 0, srl, i32, shift_imm5, IntRegs>;892defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>;893 894// Section B.13 - Add Instructions, p. 108895defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;896 897let Defs = [ICC] in898 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;899 900let Uses = [ICC] in901 defm ADDC : F3_12np<"addx", 0b001000>;902 903let Uses = [ICC], Defs = [ICC] in904 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;905 906// Section B.15 - Subtract Instructions, p. 110907defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;908let Uses = [ICC], Defs = [ICC] in909 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;910 911let Defs = [ICC], hasPostISelHook = true, isCompare = 1 in912 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;913 914let Uses = [ICC] in915 defm SUBC : F3_12np <"subx", 0b001100>;916 917def : Pat<(SPcmpicc i32:$lhs, i32:$rhs), (SUBCCrr $lhs, $rhs)>;918def : Pat<(SPcmpicc i32:$lhs, (i32 simm13:$rhs)), (SUBCCri $lhs, imm:$rhs)>;919 920// Section B.18 - Multiply Instructions, p. 113921let Defs = [Y] in {922 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>;923 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;924}925 926let Defs = [Y, ICC] in {927 defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>;928 defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>;929}930 931let Defs = [Y, ICC], Uses = [Y, ICC] in {932 defm MULSCC : F3_12np<"mulscc", 0b100100>;933}934 935// Section B.19 - Divide Instructions, p. 115936let Uses = [Y], Defs = [Y] in {937 defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>;938 defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>;939}940 941let Uses = [Y], Defs = [Y, ICC] in {942 defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>;943 defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>;944}945 946// Section B.20 - SAVE and RESTORE, p. 117947defm SAVE : F3_12np<"save" , 0b111100>;948defm RESTORE : F3_12np<"restore", 0b111101>;949 950// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119951// Section A.7 - Branch on Integer Condition Codes with Prediction (SPARC v9)952 953let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {954// unconditional branch class.955class BranchAlways<dag ins, string asmstr, list<dag> pattern>956 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;957 958// Same as BranchAlways but uses the new v9 encoding959class BranchPredictAlways<dag ins, string asmstr, list<dag> pattern>960 : F2_3<0b001, 0, 1, (outs), ins, asmstr, pattern>;961}962 963let cond = 8 in964 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;965 966let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {967 968// conditional branch class:969class BranchSP<dag ins, string asmstr, list<dag> pattern>970 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;971 972// conditional branch with annul class:973class BranchSPA<dag ins, string asmstr, list<dag> pattern>974 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;975 976// Conditional branch class on %icc|%xcc with predication:977multiclass IPredBranch<string regstr, list<dag> CCPattern> {978 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),979 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),980 CCPattern,981 IIC_iu_instr>;982 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),983 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),984 [],985 IIC_iu_instr>;986 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),987 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),988 [],989 IIC_iu_instr>;990 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),991 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),992 [],993 IIC_iu_instr>;994}995 996} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1997 998 999// Indirect branch instructions.1000let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,1001 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {1002 def BINDrr : F3_1<2, 0b111000,1003 (outs), (ins (MEMrr $rs1, $rs2):$addr),1004 "jmp $addr",1005 [(brind ADDRrr:$addr)]>;1006 def BINDri : F3_2<2, 0b111000,1007 (outs), (ins (MEMri $rs1, $simm13):$addr),1008 "jmp $addr",1009 [(brind ADDRri:$addr)]>;1010}1011 1012let Uses = [ICC] in {1013 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),1014 "b$cond $imm22",1015 [(SPbricc bb:$imm22, imm:$cond)]>;1016 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),1017 "b$cond,a $imm22", []>;1018 1019 let Predicates = [HasV9], cc = 0b00 in1020 defm BPI : IPredBranch<"%icc", [(SPbpicc bb:$imm19, imm:$cond)]>;1021}1022 1023// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 1211024 1025let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {1026 1027// floating-point conditional branch class:1028class FPBranchSP<dag ins, string asmstr, list<dag> pattern>1029 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;1030 1031// floating-point conditional branch with annul class:1032class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>1033 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;1034 1035// Conditional branch class on %fcc0-%fcc3 with predication:1036multiclass FPredBranch {1037 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,1038 FCCRegs:$cc),1039 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;1040 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,1041 FCCRegs:$cc),1042 "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>;1043 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,1044 FCCRegs:$cc),1045 "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>;1046 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,1047 FCCRegs:$cc),1048 "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>;1049}1050} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 11051 1052let Uses = [FCC0] in {1053 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),1054 "fb$cond $imm22",1055 [(SPbrfcc bb:$imm22, imm:$cond)]>;1056 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),1057 "fb$cond,a $imm22", []>;1058}1059 1060// Variants of FBCOND that uses V9 opcode1061let Predicates = [HasV9], Uses = [FCC0], cc = 0,1062 isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {1063 def FBCOND_V9 : F2_3<0b101, 0, 1, (outs),1064 (ins bprtarget:$imm19, CCOp:$cond),1065 "fb$cond %fcc0, $imm19",1066 [(SPbrfccv9 bb:$imm19, imm:$cond)], IIC_fpu_normal_instr>;1067 def FBCONDA_V9 : F2_3<0b101, 1, 1, (outs),1068 (ins bprtarget:$imm19, CCOp:$cond),1069 "fb$cond,a %fcc0, $imm19",1070 [(SPbrfccv9 bb:$imm19, imm:$cond)], IIC_fpu_normal_instr>;1071}1072 1073let Predicates = [HasV9] in1074 defm BPF : FPredBranch;1075 1076// Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 1231077let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {1078 1079// co-processor conditional branch class:1080class CPBranchSP<dag ins, string asmstr, list<dag> pattern>1081 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>;1082 1083// co-processor conditional branch with annul class:1084class CPBranchSPA<dag ins, string asmstr, list<dag> pattern>1085 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>;1086 1087} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 11088 1089def CPBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),1090 "cb$cond $imm22",1091 [(SPbrfcc bb:$imm22, imm:$cond)]>;1092def CPBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),1093 "cb$cond,a $imm22", []>;1094 1095// Section B.24 - Call and Link Instruction, p. 1251096// This is the only Format 1 instruction1097let Uses = [O6],1098 hasDelaySlot = 1, isCall = 1 in {1099 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),1100 "call $disp",1101 [],1102 IIC_jmp_or_call> {1103 bits<30> disp;1104 let op = 1;1105 let Inst{29-0} = disp;1106 }1107 1108 // call with trailing imm argument.1109 // The imm argument is discarded.1110 let isAsmParserOnly = 1 in {1111 def CALLi : InstSP<(outs), (ins calltarget:$disp, i32imm:$imm),1112 "call $disp, $imm", []> {1113 bits<30> disp;1114 let op = 1;1115 let Inst{29-0} = disp;1116 }1117 }1118 1119 // indirect calls: special cases of JMPL.1120 let isCodeGenOnly = 1, rd = 15 in {1121 def CALLrr : F3_1<2, 0b111000,1122 (outs), (ins (MEMrr $rs1, $rs2):$addr, variable_ops),1123 "call $addr",1124 [(call ADDRrr:$addr)],1125 IIC_jmp_or_call>;1126 def CALLri : F3_2<2, 0b111000,1127 (outs), (ins (MEMri $rs1, $simm13):$addr, variable_ops),1128 "call $addr",1129 [(call ADDRri:$addr)],1130 IIC_jmp_or_call>;1131 }1132 1133 let isAsmParserOnly = 1, rd = 15 in {1134 def CALLrri : F3_1<2, 0b111000,1135 (outs), (ins (MEMrr $rs1, $rs2):$addr, i32imm:$imm),1136 "call $addr, $imm", []>;1137 def CALLrii : F3_2<2, 0b111000,1138 (outs), (ins (MEMri $rs1, $simm13):$addr, i32imm:$imm),1139 "call $addr, $imm", []>;1140 }1141}1142 1143// Section B.25 - Jump and Link Instruction1144 1145// JMPL Instruction.1146let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {1147 def JMPLrr: F3_1<2, 0b111000,1148 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),1149 "jmpl $addr, $rd",1150 [],1151 IIC_jmp_or_call>;1152 def JMPLri: F3_2<2, 0b111000,1153 (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),1154 "jmpl $addr, $rd",1155 [],1156 IIC_jmp_or_call>;1157}1158 1159// Section A.3 - Synthetic Instructions, p. 851160// special cases of JMPL:1161let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,1162 isCodeGenOnly = 1 in {1163 let rd = 0, rs1 = 15 in1164 def RETL: F3_2<2, 0b111000,1165 (outs), (ins i32imm:$simm13),1166 "jmp %o7+$simm13",1167 [(retglue simm13:$simm13)],1168 IIC_jmp_or_call>;1169 1170 let rd = 0, rs1 = 31 in1171 def RET: F3_2<2, 0b111000,1172 (outs), (ins i32imm:$simm13),1173 "jmp %i7+$simm13",1174 [],1175 IIC_jmp_or_call>;1176}1177 1178// Section B.26 - Return from Trap Instruction1179let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,1180 isBarrier = 1, rd = 0 in {1181 def RETTrr : F3_1<2, 0b111001,1182 (outs), (ins (MEMrr $rs1, $rs2):$addr),1183 "rett $addr",1184 [],1185 IIC_jmp_or_call>;1186 def RETTri : F3_2<2, 0b111001,1187 (outs), (ins (MEMri $rs1, $simm13):$addr),1188 "rett $addr",1189 [],1190 IIC_jmp_or_call>;1191}1192 1193 1194// Section B.27 - Trap on Integer Condition Codes Instruction1195// conditional branch class:1196let DecoderNamespace = "SparcV8", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in1197{1198 def TRAPrr : TRAPSPrr<0b111010,1199 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),1200 "t$cond $rs1 + $rs2",1201 []>;1202 def TRAPri : TRAPSPri<0b111010,1203 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),1204 "t$cond $rs1 + $imm",1205 []>;1206}1207 1208multiclass TRAP<string regStr> {1209 def rr : TRAPSPrr<0b111010,1210 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),1211 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),1212 []>;1213 def ri : TRAPSPri<0b111010,1214 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),1215 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"),1216 []>;1217}1218 1219let DecoderNamespace = "SparcV9", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in1220 defm TICC : TRAP<"%icc">;1221 1222 1223let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in1224 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;1225 1226let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in1227 def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>;1228 1229// Section B.28 - Read State Register Instructions1230let rs2 = 0 in1231 def RDASR : F3_1<2, 0b101000,1232 (outs IntRegs:$rd), (ins ASRRegs:$rs1),1233 "rd $rs1, $rd", []>;1234 1235// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.1236let Predicates = [HasNoV9] in {1237 let rs2 = 0, rs1 = 0, Uses=[PSR] in1238 def RDPSR : F3_1<2, 0b101001,1239 (outs IntRegs:$rd), (ins),1240 "rd %psr, $rd", []>;1241 1242 let rs2 = 0, rs1 = 0, Uses=[WIM] in1243 def RDWIM : F3_1<2, 0b101010,1244 (outs IntRegs:$rd), (ins),1245 "rd %wim, $rd", []>;1246 1247 let rs2 = 0, rs1 = 0, Uses=[TBR] in1248 def RDTBR : F3_1<2, 0b101011,1249 (outs IntRegs:$rd), (ins),1250 "rd %tbr, $rd", []>;1251}1252 1253// Section B.29 - Write State Register Instructions1254def WRASRrr : F3_1<2, 0b110000,1255 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),1256 "wr $rs1, $rs2, $rd", []>;1257def WRASRri : F3_2<2, 0b110000,1258 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),1259 "wr $rs1, $simm13, $rd", []>;1260 1261// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.1262let Predicates = [HasNoV9] in {1263 let Defs = [PSR], rd=0 in {1264 def WRPSRrr : F3_1<2, 0b110001,1265 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),1266 "wr $rs1, $rs2, %psr", []>;1267 def WRPSRri : F3_2<2, 0b110001,1268 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),1269 "wr $rs1, $simm13, %psr", []>;1270 }1271 1272 let Defs = [WIM], rd=0 in {1273 def WRWIMrr : F3_1<2, 0b110010,1274 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),1275 "wr $rs1, $rs2, %wim", []>;1276 def WRWIMri : F3_2<2, 0b110010,1277 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),1278 "wr $rs1, $simm13, %wim", []>;1279 }1280 1281 let Defs = [TBR], rd=0 in {1282 def WRTBRrr : F3_1<2, 0b110011,1283 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),1284 "wr $rs1, $rs2, %tbr", []>;1285 def WRTBRri : F3_2<2, 0b110011,1286 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),1287 "wr $rs1, $simm13, %tbr", []>;1288 }1289}1290 1291// Section B.30 - STBAR Instruction1292let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in1293 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;1294 1295 1296// Section B.31 - Unimplemented Instruction1297let rd = 0 in1298 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),1299 "unimp $imm22", []>;1300 1301// Section B.32 - Flush Instruction Memory1302let rd = 0 in {1303 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins (MEMrr $rs1, $rs2):$addr),1304 "flush $addr", []>;1305 def FLUSHri : F3_2<2, 0b111011, (outs), (ins (MEMri $rs1, $simm13):$addr),1306 "flush $addr", []>;1307 1308 // The no-arg FLUSH is only here for the benefit of the InstAlias1309 // "flush", which cannot seem to use FLUSHrr, due to the inability1310 // to construct a MEMrr with fixed G0 registers.1311 let rs1 = 0, rs2 = 0 in1312 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;1313}1314 1315// Section B.33 - Floating-point Operate (FPop) Instructions1316 1317// Convert Integer to Floating-point Instructions, p. 1411318def FITOS : F3_3u<2, 0b110100, 0b011000100,1319 (outs FPRegs:$rd), (ins FPRegs:$rs2),1320 "fitos $rs2, $rd",1321 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],1322 IIC_fpu_fast_instr>;1323def FITOD : F3_3u<2, 0b110100, 0b011001000,1324 (outs DFPRegs:$rd), (ins FPRegs:$rs2),1325 "fitod $rs2, $rd",1326 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))],1327 IIC_fpu_fast_instr>;1328def FITOQ : F3_3u<2, 0b110100, 0b011001100,1329 (outs QFPRegs:$rd), (ins FPRegs:$rs2),1330 "fitoq $rs2, $rd",1331 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,1332 Requires<[HasHardQuad]>;1333 1334// Convert Floating-point to Integer Instructions, p. 1421335def FSTOI : F3_3u<2, 0b110100, 0b011010001,1336 (outs FPRegs:$rd), (ins FPRegs:$rs2),1337 "fstoi $rs2, $rd",1338 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))],1339 IIC_fpu_fast_instr>;1340def FDTOI : F3_3u<2, 0b110100, 0b011010010,1341 (outs FPRegs:$rd), (ins DFPRegs:$rs2),1342 "fdtoi $rs2, $rd",1343 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))],1344 IIC_fpu_fast_instr>;1345def FQTOI : F3_3u<2, 0b110100, 0b011010011,1346 (outs FPRegs:$rd), (ins QFPRegs:$rs2),1347 "fqtoi $rs2, $rd",1348 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,1349 Requires<[HasHardQuad]>;1350 1351// Convert between Floating-point Formats Instructions, p. 1431352def FSTOD : F3_3u<2, 0b110100, 0b011001001,1353 (outs DFPRegs:$rd), (ins FPRegs:$rs2),1354 "fstod $rs2, $rd",1355 [(set f64:$rd, (fpextend f32:$rs2))],1356 IIC_fpu_stod>;1357def FSTOQ : F3_3u<2, 0b110100, 0b011001101,1358 (outs QFPRegs:$rd), (ins FPRegs:$rs2),1359 "fstoq $rs2, $rd",1360 [(set f128:$rd, (fpextend f32:$rs2))]>,1361 Requires<[HasHardQuad]>;1362def FDTOS : F3_3u<2, 0b110100, 0b011000110,1363 (outs FPRegs:$rd), (ins DFPRegs:$rs2),1364 "fdtos $rs2, $rd",1365 [(set f32:$rd, (fpround f64:$rs2))],1366 IIC_fpu_fast_instr>;1367def FDTOQ : F3_3u<2, 0b110100, 0b011001110,1368 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),1369 "fdtoq $rs2, $rd",1370 [(set f128:$rd, (fpextend f64:$rs2))]>,1371 Requires<[HasHardQuad]>;1372def FQTOS : F3_3u<2, 0b110100, 0b011000111,1373 (outs FPRegs:$rd), (ins QFPRegs:$rs2),1374 "fqtos $rs2, $rd",1375 [(set f32:$rd, (fpround f128:$rs2))]>,1376 Requires<[HasHardQuad]>;1377def FQTOD : F3_3u<2, 0b110100, 0b011001011,1378 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),1379 "fqtod $rs2, $rd",1380 [(set f64:$rd, (fpround f128:$rs2))]>,1381 Requires<[HasHardQuad]>;1382 1383// Floating-point Move Instructions, p. 1441384def FMOVS : F3_3u<2, 0b110100, 0b000000001,1385 (outs FPRegs:$rd), (ins FPRegs:$rs2),1386 "fmovs $rs2, $rd", []>;1387def FNEGS : F3_3u<2, 0b110100, 0b000000101,1388 (outs FPRegs:$rd), (ins FPRegs:$rs2),1389 "fnegs $rs2, $rd",1390 [(set f32:$rd, (fneg f32:$rs2))],1391 IIC_fpu_negs>;1392def FABSS : F3_3u<2, 0b110100, 0b000001001,1393 (outs FPRegs:$rd), (ins FPRegs:$rs2),1394 "fabss $rs2, $rd",1395 [(set f32:$rd, (fabs f32:$rs2))],1396 IIC_fpu_abs>;1397 1398 1399// Floating-point Square Root Instructions, p.1451400// FSQRTS generates an erratum on LEON processors, so by disabling this instruction1401// this will be promoted to use FSQRTD with doubles instead.1402let Predicates = [HasNoFdivSqrtFix] in1403def FSQRTS : F3_3u<2, 0b110100, 0b000101001,1404 (outs FPRegs:$rd), (ins FPRegs:$rs2),1405 "fsqrts $rs2, $rd",1406 [(set f32:$rd, (fsqrt f32:$rs2))],1407 IIC_fpu_sqrts>;1408def FSQRTD : F3_3u<2, 0b110100, 0b000101010,1409 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),1410 "fsqrtd $rs2, $rd",1411 [(set f64:$rd, (fsqrt f64:$rs2))],1412 IIC_fpu_sqrtd>;1413def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,1414 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),1415 "fsqrtq $rs2, $rd",1416 [(set f128:$rd, (fsqrt f128:$rs2))]>,1417 Requires<[HasHardQuad]>;1418 1419 1420 1421// Floating-point Add and Subtract Instructions, p. 1461422def FADDS : F3_3<2, 0b110100, 0b001000001,1423 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),1424 "fadds $rs1, $rs2, $rd",1425 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))],1426 IIC_fpu_fast_instr>;1427def FADDD : F3_3<2, 0b110100, 0b001000010,1428 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),1429 "faddd $rs1, $rs2, $rd",1430 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))],1431 IIC_fpu_fast_instr>;1432def FADDQ : F3_3<2, 0b110100, 0b001000011,1433 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),1434 "faddq $rs1, $rs2, $rd",1435 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,1436 Requires<[HasHardQuad]>;1437 1438def FSUBS : F3_3<2, 0b110100, 0b001000101,1439 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),1440 "fsubs $rs1, $rs2, $rd",1441 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))],1442 IIC_fpu_fast_instr>;1443def FSUBD : F3_3<2, 0b110100, 0b001000110,1444 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),1445 "fsubd $rs1, $rs2, $rd",1446 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))],1447 IIC_fpu_fast_instr>;1448def FSUBQ : F3_3<2, 0b110100, 0b001000111,1449 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),1450 "fsubq $rs1, $rs2, $rd",1451 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,1452 Requires<[HasHardQuad]>;1453 1454 1455// Floating-point Multiply and Divide Instructions, p. 1471456def FMULS : F3_3<2, 0b110100, 0b001001001,1457 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),1458 "fmuls $rs1, $rs2, $rd",1459 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],1460 IIC_fpu_muls>,1461 Requires<[HasFMULS]>;1462def FMULD : F3_3<2, 0b110100, 0b001001010,1463 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),1464 "fmuld $rs1, $rs2, $rd",1465 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))],1466 IIC_fpu_muld>;1467def FMULQ : F3_3<2, 0b110100, 0b001001011,1468 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),1469 "fmulq $rs1, $rs2, $rd",1470 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,1471 Requires<[HasHardQuad]>;1472 1473def FSMULD : F3_3<2, 0b110100, 0b001101001,1474 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),1475 "fsmuld $rs1, $rs2, $rd",1476 [(set f64:$rd, (fmul (fpextend f32:$rs1),1477 (fpextend f32:$rs2)))],1478 IIC_fpu_muld>,1479 Requires<[HasFSMULD]>;1480def FDMULQ : F3_3<2, 0b110100, 0b001101110,1481 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),1482 "fdmulq $rs1, $rs2, $rd",1483 [(set f128:$rd, (fmul (fpextend f64:$rs1),1484 (fpextend f64:$rs2)))]>,1485 Requires<[HasHardQuad]>;1486 1487// FDIVS generates an erratum on LEON processors, so by disabling this instruction1488// this will be promoted to use FDIVD with doubles instead.1489def FDIVS : F3_3<2, 0b110100, 0b001001101,1490 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),1491 "fdivs $rs1, $rs2, $rd",1492 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],1493 IIC_fpu_divs>;1494def FDIVD : F3_3<2, 0b110100, 0b001001110,1495 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),1496 "fdivd $rs1, $rs2, $rd",1497 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],1498 IIC_fpu_divd>;1499def FDIVQ : F3_3<2, 0b110100, 0b001001111,1500 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),1501 "fdivq $rs1, $rs2, $rd",1502 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,1503 Requires<[HasHardQuad]>;1504 1505// Floating-point Compare Instructions, p. 1481506// Note: the 2nd template arg is different for these guys.1507// Note 2: the result of a FCMP is not available until the 2nd cycle1508// after the instr is retired, but there is no interlock in Sparc V8.1509// This behavior is modeled with a forced noop after the instruction in1510// DelaySlotFiller.1511 1512let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {1513 def FCMPS : F3_3c<2, 0b110101, 0b001010001,1514 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),1515 "fcmps $rs1, $rs2",1516 [(SPcmpfcc f32:$rs1, f32:$rs2)],1517 IIC_fpu_fast_instr>;1518 def FCMPD : F3_3c<2, 0b110101, 0b001010010,1519 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),1520 "fcmpd $rs1, $rs2",1521 [(SPcmpfcc f64:$rs1, f64:$rs2)],1522 IIC_fpu_fast_instr>;1523 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,1524 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),1525 "fcmpq $rs1, $rs2",1526 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,1527 Requires<[HasHardQuad]>;1528}1529 1530// A.13 Floating-Point Compare (SPARC v9)1531// Note that these always write to %fcc0 instead of having its destination1532// allocated automatically.1533// This avoids complications with the scheduler sometimes wanting to spill1534// the contents of an FCC, since SPARC v9 doesn't have facilities to spill1535// an individual FCC.1536 1537let Predicates = [HasV9], Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {1538 def FCMPS_V9 : F3_3c<2, 0b110101, 0b001010001,1539 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),1540 "fcmps %fcc0, $rs1, $rs2",1541 [(SPcmpfccv9 f32:$rs1, f32:$rs2)],1542 IIC_fpu_fast_instr>;1543 def FCMPD_V9 : F3_3c<2, 0b110101, 0b001010010,1544 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),1545 "fcmpd %fcc0, $rs1, $rs2",1546 [(SPcmpfccv9 f64:$rs1, f64:$rs2)],1547 IIC_fpu_fast_instr>;1548 def FCMPQ_V9 : F3_3c<2, 0b110101, 0b001010011,1549 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),1550 "fcmpq %fcc0, $rs1, $rs2",1551 [(SPcmpfccv9 f128:$rs1, f128:$rs2)]>,1552 Requires<[HasHardQuad]>;1553}1554 1555//===----------------------------------------------------------------------===//1556// Instructions for Thread Local Storage(TLS).1557//===----------------------------------------------------------------------===//1558let isAsmParserOnly = 1 in {1559def TLS_ADDrr : F3_1<2, 0b000000,1560 (outs IntRegs:$rd),1561 (ins IntRegs:$rs1, IntRegs:$rs2, TailRelocSymTLSAdd:$sym),1562 "add $rs1, $rs2, $rd, $sym",1563 [(set i32:$rd,1564 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;1565 1566let mayLoad = 1 in {1567 def TLS_LDrr : F3_1<3, 0b000000,1568 (outs IntRegs:$rd),1569 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),1570 "ld [$addr], $rd, $sym",1571 [(set i32:$rd,1572 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;1573}1574 1575let Uses = [O6], isCall = 1, hasDelaySlot = 1 in1576 def TLS_CALL : InstSP<(outs),1577 (ins calltarget:$disp, TailRelocSymTLSCall:$sym,1578 variable_ops),1579 "call $disp, $sym",1580 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)],1581 IIC_jmp_or_call> {1582 bits<30> disp;1583 let op = 1;1584 let Inst{29-0} = disp;1585}1586}1587 1588//===----------------------------------------------------------------------===//1589// Instructions for tail calls.1590//===----------------------------------------------------------------------===//1591let isCodeGenOnly = 1, isReturn = 1, hasDelaySlot = 1,1592 isTerminator = 1, isBarrier = 1 in {1593 def TAIL_CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),1594 "call $disp",1595 [(tailcall tglobaladdr:$disp)]> {1596 bits<30> disp;1597 let op = 1;1598 let Inst{29-0} = disp;1599 }1600}1601 1602def : Pat<(tailcall (iPTR texternalsym:$dst)),1603 (TAIL_CALL texternalsym:$dst)>;1604 1605let isCodeGenOnly = 1, isReturn = 1, hasDelaySlot = 1, isTerminator = 1,1606 isBarrier = 1, rd = 0 in {1607 def TAIL_CALLri : F3_2<2, 0b111000,1608 (outs), (ins (MEMri $rs1, $simm13):$addr, variable_ops),1609 "jmp $addr",1610 [(tailcall ADDRri:$addr)]>;1611}1612 1613//===----------------------------------------------------------------------===//1614// V9 Instructions1615//===----------------------------------------------------------------------===//1616 1617// V9 Conditional Moves.1618let Predicates = [HasV9], Constraints = "$f = $rd" in {1619 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.1620 let Uses = [ICC], intcc = 1, cc = 0b00 in {1621 def MOVICCrr1622 : F4_1<0b101100, (outs IntRegs:$rd),1623 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),1624 "mov$cond %icc, $rs2, $rd",1625 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;1626 1627 def MOVICCri1628 : F4_2<0b101100, (outs IntRegs:$rd),1629 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),1630 "mov$cond %icc, $simm11, $rd",1631 [(set i32:$rd,1632 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;1633 }1634 1635 let Uses = [FCC0], intcc = 0, cc = 0b00 in {1636 def MOVFCCrr1637 : F4_1<0b101100, (outs IntRegs:$rd),1638 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),1639 "mov$cond %fcc0, $rs2, $rd",1640 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;1641 def MOVFCCri1642 : F4_2<0b101100, (outs IntRegs:$rd),1643 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),1644 "mov$cond %fcc0, $simm11, $rd",1645 [(set i32:$rd,1646 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;1647 }1648 1649 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {1650 def FMOVS_ICC1651 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),1652 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),1653 "fmovs$cond %icc, $rs2, $rd",1654 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;1655 def FMOVD_ICC1656 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),1657 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),1658 "fmovd$cond %icc, $rs2, $rd",1659 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;1660 let Predicates = [HasV9, HasHardQuad] in1661 def FMOVQ_ICC1662 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),1663 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),1664 "fmovq$cond %icc, $rs2, $rd",1665 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;1666 }1667 1668 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {1669 def FMOVS_FCC1670 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),1671 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),1672 "fmovs$cond %fcc0, $rs2, $rd",1673 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;1674 def FMOVD_FCC1675 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),1676 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),1677 "fmovd$cond %fcc0, $rs2, $rd",1678 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;1679 let Predicates = [HasV9, HasHardQuad] in1680 def FMOVQ_FCC1681 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),1682 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),1683 "fmovq$cond %fcc0, $rs2, $rd",1684 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;1685 }1686 1687}1688 1689// Floating-Point Move Instructions, p. 164 of the V9 manual.1690let Predicates = [HasV9] in {1691 def FMOVD : F3_3u<2, 0b110100, 0b000000010,1692 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),1693 "fmovd $rs2, $rd", []>;1694 let Predicates = [HasV9, HasHardQuad] in1695 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,1696 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),1697 "fmovq $rs2, $rd", []>;1698 def FNEGD : F3_3u<2, 0b110100, 0b000000110,1699 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),1700 "fnegd $rs2, $rd",1701 [(set f64:$rd, (fneg f64:$rs2))]>;1702 let Predicates = [HasV9, HasHardQuad] in1703 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,1704 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),1705 "fnegq $rs2, $rd",1706 [(set f128:$rd, (fneg f128:$rs2))]>;1707 def FABSD : F3_3u<2, 0b110100, 0b000001010,1708 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),1709 "fabsd $rs2, $rd",1710 [(set f64:$rd, (fabs f64:$rs2))]>;1711 let Predicates = [HasV9, HasHardQuad] in1712 def FABSQ : F3_3u<2, 0b110100, 0b000001011,1713 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),1714 "fabsq $rs2, $rd",1715 [(set f128:$rd, (fabs f128:$rs2))]>;1716}1717 1718// Floating-point compare instruction with %fcc0-%fcc3.1719def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,1720 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),1721 "fcmps $rd, $rs1, $rs2", []>;1722def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,1723 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),1724 "fcmpd $rd, $rs1, $rs2", []>;1725def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,1726 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),1727 "fcmpq $rd, $rs1, $rs2", []>,1728 Requires<[HasHardQuad]>;1729 1730let hasSideEffects = 1 in {1731 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,1732 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),1733 "fcmpes $rd, $rs1, $rs2", []>;1734 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,1735 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),1736 "fcmped $rd, $rs1, $rs2", []>;1737 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,1738 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),1739 "fcmpeq $rd, $rs1, $rs2", []>,1740 Requires<[HasHardQuad]>;1741}1742 1743// Floating point conditional move instrucitons with %fcc0-%fcc3.1744let Predicates = [HasV9] in {1745 let Constraints = "$f = $rd", intcc = 0 in {1746 def V9MOVFCCrr1747 : F4_1<0b101100, (outs IntRegs:$rd),1748 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),1749 "mov$cond $cc, $rs2, $rd", []>;1750 def V9MOVFCCri1751 : F4_2<0b101100, (outs IntRegs:$rd),1752 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),1753 "mov$cond $cc, $simm11, $rd", []>;1754 def V9FMOVS_FCC1755 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),1756 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),1757 "fmovs$cond $opf_cc, $rs2, $rd", []>;1758 def V9FMOVD_FCC1759 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),1760 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),1761 "fmovd$cond $opf_cc, $rs2, $rd", []>;1762 let Predicates = [HasV9, HasHardQuad] in1763 def V9FMOVQ_FCC1764 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),1765 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),1766 "fmovq$cond $opf_cc, $rs2, $rd", []>;1767 } // Constraints = "$f = $rd", ...1768} // let Predicates = [hasV9]1769 1770 1771// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear1772// the top 32-bits before using it. To do this clearing, we use a SRLri X,0.1773let rs1 = 0 in1774 def POPCrr : F3_1<2, 0b101110,1775 (outs IntRegs:$rd), (ins IntRegs:$rs2),1776 "popc $rs2, $rd", []>, Requires<[HasV9]>;1777def : Pat<(i32 (ctpop i32:$src)),1778 (POPCrr (SRLri $src, 0))>;1779 1780let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in1781 def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13),1782 "membar $simm13", []>;1783 1784let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in1785 def SIR: F3_2<2, 0b110000, (outs),1786 (ins simm13Op:$simm13),1787 "sir $simm13", []>;1788 1789// CASA supported on all V9, some LEON3 and all LEON4 processors.1790let Predicates = [HasCASA], Constraints = "$swap = $rd" in1791 def CASArr: F3_1_asi<3, 0b111100,1792 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,1793 IntRegs:$swap, ASITag:$asi),1794 "casa [$rs1] $asi, $rs2, $rd", []>;1795 1796// On the other hand, CASA that takes its ASI from a register1797// is only supported on V9 processors.1798let Predicates = [HasV9], Uses = [ASR3], Constraints = "$swap = $rd" in1799 def CASAri: F3_1_cas_asi<3, 0b111100,1800 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,1801 IntRegs:$swap),1802 "casa [$rs1] %asi, $rs2, $rd", []>;1803 1804// TODO: Add DAG sequence to lower these instructions. Currently, only provided1805// as inline assembler-supported instructions.1806let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {1807 def SMACrr : F3_1<2, 0b111111,1808 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),1809 "smac $rs1, $rs2, $rd",1810 [], IIC_smac_umac>;1811 1812 def SMACri : F3_2<2, 0b111111,1813 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),1814 "smac $rs1, $simm13, $rd",1815 [], IIC_smac_umac>;1816 1817 def UMACrr : F3_1<2, 0b111110,1818 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),1819 "umac $rs1, $rs2, $rd",1820 [], IIC_smac_umac>;1821 1822 def UMACri : F3_2<2, 0b111110,1823 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),1824 "umac $rs1, $simm13, $rd",1825 [], IIC_smac_umac>;1826}1827 1828// The partial write WRPSR instruction has a non-zero destination1829// register value to separate it from the standard instruction.1830let Predicates = [HasPWRPSR], Defs = [PSR], rd=1 in {1831 def PWRPSRrr : F3_1<2, 0b110001,1832 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),1833 "pwr $rs1, $rs2, %psr", []>;1834 def PWRPSRri : F3_2<2, 0b110001,1835 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),1836 "pwr $rs1, $simm13, %psr", []>;1837}1838 1839let Defs = [ICC] in {1840defm TADDCC : F3_12np<"taddcc", 0b100000>;1841defm TSUBCC : F3_12np<"tsubcc", 0b100001>;1842 1843let hasSideEffects = 1 in {1844 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;1845 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;1846}1847}1848 1849// Section A.11 - DONE and RETRY1850// Section A.47 - SAVED and RESTORED1851let Predicates = [HasV9], rs1 = 0, rs2 = 0 in {1852 let rd = 0 in1853 def DONE : F3_1<2, 0b111110, (outs), (ins), "done", []>;1854 1855 let rd = 1 in1856 def RETRY : F3_1<2, 0b111110, (outs), (ins), "retry", []>;1857 1858 let rd = 0 in1859 def SAVED : F3_1<2, 0b110001, (outs), (ins), "saved", []>;1860 1861 let rd = 1 in1862 def RESTORED : F3_1<2, 0b110001, (outs), (ins), "restored", []>;1863}1864 1865// Section A.42 - Prefetch Data1866let Predicates = [HasV9] in {1867 def PREFETCHr : F3_1<3, 0b101101,1868 (outs), (ins (MEMrr $rs1, $rs2):$addr, PrefetchTag:$rd),1869 "prefetch [$addr], $rd", []>;1870 def PREFETCHi : F3_2<3, 0b101101,1871 (outs), (ins (MEMri $rs1, $simm13):$addr, PrefetchTag:$rd),1872 "prefetch [$addr], $rd", []>;1873 def PREFETCHAr : F3_1_asi<3, 0b111101, (outs),1874 (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, PrefetchTag:$rd),1875 "prefetcha [$addr] $asi, $rd", []>;1876 let Uses = [ASR3] in1877 def PREFETCHAi : F3_2<3, 0b111101, (outs),1878 (ins (MEMri $rs1, $simm13):$addr, PrefetchTag:$rd),1879 "prefetcha [$addr] %asi, $rd", []>;1880}1881 1882 1883 1884// Section A.43 - Read Privileged Register Instructions1885let Predicates = [HasV9] in {1886let rs2 = 0 in1887 def RDPR : F3_1<2, 0b101010,1888 (outs IntRegs:$rd), (ins PRRegs:$rs1),1889 "rdpr $rs1, $rd", []>;1890 1891// Special case %fq as the register is also used in V81892// (albeit with different instructions and encoding).1893// This allows us to reuse the register definition and1894// the "%fq" designation while giving it a different encoding.1895let Uses = [FQ], rs1 = 15, rs2 = 0 in1896 def RDFQ : F3_1<2, 0b101010,1897 (outs IntRegs:$rd), (ins),1898 "rdpr %fq, $rd", []>;1899}1900 1901// Section A.62 - Write Privileged Register Instructions1902let Predicates = [HasV9] in {1903 def WRPRrr : F3_1<2, 0b110010,1904 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),1905 "wrpr $rs1, $rs2, $rd", []>;1906 def WRPRri : F3_2<2, 0b110010,1907 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),1908 "wrpr $rs1, $simm13, $rd", []>;1909}1910 1911//===----------------------------------------------------------------------===//1912// Non-Instruction Patterns1913//===----------------------------------------------------------------------===//1914 1915// Zero immediate.1916def : Pat<(i32 0), (COPY (i32 G0))>;1917// Small immediates.1918def : Pat<(i32 simm13:$val),1919 (ORri (i32 G0), imm:$val)>;1920// Arbitrary immediates.1921def : Pat<(i32 imm:$val),1922 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;1923 1924// Frame index.1925def to_tframeindex : SDNodeXForm<frameindex, [{1926 return CurDAG->getTargetFrameIndex(N->getIndex(), N->getValueType(0));1927}]>;1928def : Pat<(i32 (frameindex:$ptr)), (ADDri (i32 (to_tframeindex $ptr)), (i32 0))>;1929def : Pat<(i64 (frameindex:$ptr)), (ADDri (i64 (to_tframeindex $ptr)), (i64 0))>;1930 1931// Global addresses, constant pool entries1932let Predicates = [Is32Bit] in {1933 1934def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;1935def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;1936def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;1937def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;1938 1939// GlobalTLS addresses1940def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;1941def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;1942def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),1943 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;1944def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),1945 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;1946 1947// Blockaddress1948def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;1949def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;1950 1951// Add reg, lo. This is used when taking the addr of a global/constpool entry.1952def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;1953def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;1954def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),1955 (ADDri $r, tblockaddress:$in)>;1956}1957 1958// Calls:1959def : Pat<(call tglobaladdr:$dst),1960 (CALL tglobaladdr:$dst)>;1961def : Pat<(call texternalsym:$dst),1962 (CALL texternalsym:$dst)>;1963 1964// Map integer extload's to zextloads.1965def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;1966def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;1967def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;1968def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;1969def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;1970def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;1971 1972// zextload bool -> zextload byte1973def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;1974def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;1975 1976// store 0, addr -> store %g0, addr1977def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;1978def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;1979 1980// All load-type operations in V8 comes with implicit acquire semantics.1981let Predicates = [HasNoV9] in {1982 // Acquire -> nop1983 def : Pat<(atomic_fence (i32 4), timm), (NOP)>;1984 // Release / AcqRel -> stbar1985 def : Pat<(atomic_fence (i32 5), timm), (STBAR)>;1986 // AcqRel and stronger -> stbar; ldstub [%sp-1], %g01987 def : Pat<(atomic_fence timm, timm), (V8BAR)>;1988}1989 1990// We have to handle both 32 and 64-bit cases.1991let Predicates = [HasV9] in {1992 // Acquire -> membar #LoadLoad | #LoadStore1993 def : Pat<(atomic_fence (i32 4), timm), (MEMBARi 0x5)>;1994 def : Pat<(atomic_fence (i64 4), timm), (MEMBARi 0x5)>;1995 // Release -> membar #LoadStore | #StoreStore1996 def : Pat<(atomic_fence (i32 5), timm), (MEMBARi 0xc)>;1997 def : Pat<(atomic_fence (i64 5), timm), (MEMBARi 0xc)>;1998 // AcqRel -> membar #LoadLoad | #LoadStore | #StoreStore1999 def : Pat<(atomic_fence (i32 6), timm), (MEMBARi 0xd)>;2000 def : Pat<(atomic_fence (i64 6), timm), (MEMBARi 0xd)>;2001 // SeqCst -> membar #StoreLoad | #LoadLoad | #LoadStore | #StoreStore2002 def : Pat<(atomic_fence timm, timm), (MEMBARi 0xf)>;2003}2004 2005// atomic_load addr -> load addr2006def : Pat<(i32 (atomic_load_azext_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;2007def : Pat<(i32 (atomic_load_azext_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;2008def : Pat<(i32 (atomic_load_azext_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;2009def : Pat<(i32 (atomic_load_azext_16 ADDRri:$src)), (LDUHri ADDRri:$src)>;2010def : Pat<(i32 (atomic_load_nonext_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>;2011def : Pat<(i32 (atomic_load_nonext_32 ADDRri:$src)), (LDri ADDRri:$src)>;2012 2013// atomic_store val, addr -> store val, addr2014def : Pat<(atomic_store_8 i32:$val, ADDRrr:$dst), (STBrr ADDRrr:$dst, $val)>;2015def : Pat<(atomic_store_8 i32:$val, ADDRri:$dst), (STBri ADDRri:$dst, $val)>;2016def : Pat<(atomic_store_16 i32:$val, ADDRrr:$dst), (STHrr ADDRrr:$dst, $val)>;2017def : Pat<(atomic_store_16 i32:$val, ADDRri:$dst), (STHri ADDRri:$dst, $val)>;2018def : Pat<(atomic_store_32 i32:$val, ADDRrr:$dst), (STrr ADDRrr:$dst, $val)>;2019def : Pat<(atomic_store_32 i32:$val, ADDRri:$dst), (STri ADDRri:$dst, $val)>;2020 2021let Predicates = [HasV9] in2022def : Pat<(atomic_cmp_swap_i32 iPTR:$rs1, i32:$rs2, i32:$swap),2023 (CASArr $rs1, $rs2, $swap, 0x80)>;2024 2025// Same pattern as CASArr above, but with a different ASI.2026let Predicates = [HasLeonCASA] in2027def : Pat<(atomic_cmp_swap_i32 iPTR:$rs1, i32:$rs2, i32:$swap),2028 (CASArr $rs1, $rs2, $swap, 0x0A)>;2029 2030// A register pair with zero upper half.2031// The upper part is done with ORrr instead of `COPY G0`2032// or a normal register copy, since `COPY G0`s in that place2033// will be converted into `COPY G0_G1` later on, which is not2034// what we want in this case.2035def : Pat<(build_vector (i32 0), (i32 IntRegs:$a2)),2036 (INSERT_SUBREG (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),2037 (ORrr (i32 G0), (i32 G0)), sub_even),2038 (i32 IntRegs:$a2), sub_odd)>;2039 2040// extract_vector2041def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),2042 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;2043def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),2044 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;2045 2046// build_vector2047def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),2048 (INSERT_SUBREG2049 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),2050 (i32 IntRegs:$a2), sub_odd)>;2051 2052 2053include "SparcInstr64Bit.td"2054include "SparcInstrVIS.td"2055include "SparcInstrUAOSA.td"2056include "SparcInstrCrypto.td"2057include "SparcInstrAliases.td"2058