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1//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains instruction formats, definitions and patterns needed for10// UA 2005, UA 2007, and OSA 2011 instructions on SPARC.11//===----------------------------------------------------------------------===//12 13class UA2005RegWin<string asmstr, bits<5> fcn>14 : F3_1<2, 0b110001, (outs), (ins), asmstr, []> {15 let rd = fcn;16 let rs1 = 0;17 let rs2 = 0;18}19 20// Convenience template for 4-operand instructions21class FourOp<string OpcStr, bits<6> op3val, bits<4> op5val,22 RegisterClass RC>23 : F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),24 !strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;25 26/// F2_56 multiclass - Define a F2_5/F2_6 pattern in one shot.27multiclass F2_56<string OpcStr, bits<1> cc> {28 def rr : F2_5<cc, (outs),29 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, IntRegs:$rs2),30 !strconcat(OpcStr, "$cond $rs1, $rs2, $imm10")>;31 def ri : F2_6<cc, (outs),32 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, simm5Op:$simm5),33 !strconcat(OpcStr, "$cond $rs1, $simm5, $imm10")>;34}35 36// UltraSPARC Architecture 2005 Instructions37let Predicates = [HasUA2005] in {38let hasSideEffects = 1 in {39def ALLCLEAN : UA2005RegWin<"allclean", 0b00010>;40def INVALW : UA2005RegWin<"invalw", 0b00101>;41def NORMALW : UA2005RegWin<"normalw", 0b00100>;42def OTHERW : UA2005RegWin<"otherw", 0b00011>;43}44} // Predicates = [HasUA2005]45 46// UltraSPARC Architecture 2007 Instructions47let Predicates = [HasUA2007] in {48def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;49def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;50def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;51def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;52 53def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;54def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;55def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;56def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;57} // Predicates = [HasUA2007]58 59// Oracle SPARC Architecture 2011 Instructions60let Predicates = [HasOSA2011] in {61let isBranch = 1, isTerminator = 1, hasDelaySlot = 0 in {62defm CWBCOND : F2_56<"cwb", 0>;63defm CXBCOND : F2_56<"cxb", 1>;64}65 66def FPMADDX : FourOp<"fpmaddx", 0b110111, 0b0000, DFPRegs>;67def FPMADDXHI : FourOp<"fpmaddxhi", 0b110111, 0b0100, DFPRegs>;68} // Predicates = [HasOSA2011]69 70// UA2007 instruction patterns.71let Predicates = [HasUA2007] in {72def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, f32:$add)), (FMADDS $rs1, $rs2, $add)>;73def : Pat<(f64 (any_fma f64:$rs1, f64:$rs2, f64:$add)), (FMADDD $rs1, $rs2, $add)>;74def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, (fneg f32:$sub))), (FMSUBS $rs1, $rs2, $sub)>;75def : Pat<(f64 (any_fma f64:$rs1, f64:$rs2, (fneg f64:$sub))), (FMSUBD $rs1, $rs2, $sub)>;76def : Pat<(f32 (fneg (any_fma f32:$rs1, f32:$rs2, f32:$add))), (FNMADDS $rs1, $rs2, $add)>;77def : Pat<(f64 (fneg (any_fma f64:$rs1, f64:$rs2, f64:$add))), (FNMADDD $rs1, $rs2, $add)>;78def : Pat<(f32 (fneg (any_fma f32:$rs1, f32:$rs2, (fneg f32:$sub)))), (FNMSUBS $rs1, $rs2, $sub)>;79def : Pat<(f64 (fneg (any_fma f64:$rs1, f64:$rs2, (fneg f64:$sub)))), (FNMSUBD $rs1, $rs2, $sub)>;80} // Predicates = [HasUA2007]81