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1//===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Declarations that describe the Sparc register file11//===----------------------------------------------------------------------===//12 13class SparcReg<bits<16> Enc, string n> : Register<n> {14 let HWEncoding = Enc;15 let Namespace = "SP";16}17 18class SparcCtrlReg<bits<16> Enc, string n,19 list<string> altNames = []>: Register<n, altNames> {20 let HWEncoding = Enc;21 let Namespace = "SP";22}23 24let Namespace = "SP" in {25def sub_even : SubRegIndex<32>;26def sub_odd : SubRegIndex<32, 32>;27def sub_even64 : SubRegIndex<64>;28def sub_odd64 : SubRegIndex<64, 64>;29}30 31let Namespace = "SP",32 FallbackRegAltNameIndex = NoRegAltName in {33 def RegNamesStateReg : RegAltNameIndex;34}35 36// Registers are identified with 5-bit ID numbers.37// Ri - 32-bit integer registers38class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;39 40// Rdi - pairs of 32-bit integer registers41class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {42 let SubRegs = subregs;43 let SubRegIndices = [sub_even, sub_odd];44 let CoveredBySubRegs = 1;45}46// Rf - 32-bit floating-point registers47class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;48 49// Rd - Slots in the FP register file for 64-bit floating-point values.50class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {51 let SubRegs = subregs;52 let SubRegIndices = [sub_even, sub_odd];53 let CoveredBySubRegs = 1;54}55 56// Rq - Slots in the FP register file for 128-bit floating-point values.57class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {58 let SubRegs = subregs;59 let SubRegIndices = [sub_even64, sub_odd64];60 let CoveredBySubRegs = 1;61}62 63// Control Registers64def ICC : SparcCtrlReg<0, "icc">; // This represents icc and xcc in 64-bit code.65foreach I = 0-3 in66 def FCC#I : SparcCtrlReg<I, "fcc"#I>;67 68def FSR : SparcCtrlReg<0, "fsr">; // Floating-point state register.69def FQ : SparcCtrlReg<0, "fq">; // Floating-point deferred-trap queue.70def CPSR : SparcCtrlReg<0, "csr">; // Co-processor state register.71def CPQ : SparcCtrlReg<0, "cq">; // Co-processor queue.72 73// Y register74def Y : SparcCtrlReg<0, "y">, DwarfRegNum<[64]>;75// Ancillary state registers (implementation defined)76def ASR1 : SparcCtrlReg<1, "asr1">;77let RegAltNameIndices = [RegNamesStateReg] in {78// FIXME: Currently this results in the assembler accepting79// the alternate names (%ccr, %asi, etc.) when targeting V8.80// Make sure that the alternate names are available for V9 only:81// %asr2-asr6 : valid on both V8 and V9.82// %ccr, %asi, etc.: valid on V9, returns "no such register" error on V8.83def ASR2 : SparcCtrlReg<2, "asr2", ["ccr"]>;84def ASR3 : SparcCtrlReg<3, "asr3", ["asi"]>;85def ASR4 : SparcCtrlReg<4, "asr4", ["tick"]>;86def ASR5 : SparcCtrlReg<5, "asr5", ["pc"]>;87def ASR6 : SparcCtrlReg<6, "asr6", ["fprs"]>;88}89def ASR7 : SparcCtrlReg< 7, "asr7">;90def ASR8 : SparcCtrlReg< 8, "asr8">;91def ASR9 : SparcCtrlReg< 9, "asr9">;92def ASR10 : SparcCtrlReg<10, "asr10">;93def ASR11 : SparcCtrlReg<11, "asr11">;94def ASR12 : SparcCtrlReg<12, "asr12">;95def ASR13 : SparcCtrlReg<13, "asr13">;96def ASR14 : SparcCtrlReg<14, "asr14">;97def ASR15 : SparcCtrlReg<15, "asr15">;98def ASR16 : SparcCtrlReg<16, "asr16">;99def ASR17 : SparcCtrlReg<17, "asr17">;100def ASR18 : SparcCtrlReg<18, "asr18">;101def ASR19 : SparcCtrlReg<19, "asr19">;102def ASR20 : SparcCtrlReg<20, "asr20">;103def ASR21 : SparcCtrlReg<21, "asr21">;104def ASR22 : SparcCtrlReg<22, "asr22">;105def ASR23 : SparcCtrlReg<23, "asr23">;106def ASR24 : SparcCtrlReg<24, "asr24">;107def ASR25 : SparcCtrlReg<25, "asr25">;108def ASR26 : SparcCtrlReg<26, "asr26">;109def ASR27 : SparcCtrlReg<27, "asr27">;110def ASR28 : SparcCtrlReg<28, "asr28">;111def ASR29 : SparcCtrlReg<29, "asr29">;112def ASR30 : SparcCtrlReg<30, "asr30">;113def ASR31 : SparcCtrlReg<31, "asr31">;114 115// Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.116def PSR : SparcCtrlReg<0, "psr">;117def WIM : SparcCtrlReg<0, "wim">;118def TBR : SparcCtrlReg<0, "tbr">;119 120// Privileged V9 state registers121def TPC : SparcCtrlReg< 0, "tpc">;122def TNPC : SparcCtrlReg< 1, "tnpc">;123def TSTATE : SparcCtrlReg< 2, "tstate">;124def TT : SparcCtrlReg< 3, "tt">;125def TICK : SparcCtrlReg< 4, "tick">;126def TBA : SparcCtrlReg< 5, "tba">;127def PSTATE : SparcCtrlReg< 6, "pstate">;128def TL : SparcCtrlReg< 7, "tl">;129def PIL : SparcCtrlReg< 8, "pil">;130def CWP : SparcCtrlReg< 9, "cwp">;131def CANSAVE : SparcCtrlReg<10, "cansave">;132def CANRESTORE : SparcCtrlReg<11, "canrestore">;133def CLEANWIN : SparcCtrlReg<12, "cleanwin">;134def OTHERWIN : SparcCtrlReg<13, "otherwin">;135def WSTATE : SparcCtrlReg<14, "wstate">;136def GL : SparcCtrlReg<16, "gl">;137def VER : SparcCtrlReg<31, "ver">;138 139// Integer registers140def G0 : Ri< 0, "g0">, DwarfRegNum<[0]> {141 let isConstant = true;142}143def G1 : Ri< 1, "g1">, DwarfRegNum<[1]>;144def G2 : Ri< 2, "g2">, DwarfRegNum<[2]>;145def G3 : Ri< 3, "g3">, DwarfRegNum<[3]>;146def G4 : Ri< 4, "g4">, DwarfRegNum<[4]>;147def G5 : Ri< 5, "g5">, DwarfRegNum<[5]>;148def G6 : Ri< 6, "g6">, DwarfRegNum<[6]>;149def G7 : Ri< 7, "g7">, DwarfRegNum<[7]>;150def O0 : Ri< 8, "o0">, DwarfRegNum<[8]>;151def O1 : Ri< 9, "o1">, DwarfRegNum<[9]>;152def O2 : Ri<10, "o2">, DwarfRegNum<[10]>;153def O3 : Ri<11, "o3">, DwarfRegNum<[11]>;154def O4 : Ri<12, "o4">, DwarfRegNum<[12]>;155def O5 : Ri<13, "o5">, DwarfRegNum<[13]>;156def O6 : Ri<14, "sp">, DwarfRegNum<[14]>;157def O7 : Ri<15, "o7">, DwarfRegNum<[15]>;158def L0 : Ri<16, "l0">, DwarfRegNum<[16]>;159def L1 : Ri<17, "l1">, DwarfRegNum<[17]>;160def L2 : Ri<18, "l2">, DwarfRegNum<[18]>;161def L3 : Ri<19, "l3">, DwarfRegNum<[19]>;162def L4 : Ri<20, "l4">, DwarfRegNum<[20]>;163def L5 : Ri<21, "l5">, DwarfRegNum<[21]>;164def L6 : Ri<22, "l6">, DwarfRegNum<[22]>;165def L7 : Ri<23, "l7">, DwarfRegNum<[23]>;166def I0 : Ri<24, "i0">, DwarfRegNum<[24]>;167def I1 : Ri<25, "i1">, DwarfRegNum<[25]>;168def I2 : Ri<26, "i2">, DwarfRegNum<[26]>;169def I3 : Ri<27, "i3">, DwarfRegNum<[27]>;170def I4 : Ri<28, "i4">, DwarfRegNum<[28]>;171def I5 : Ri<29, "i5">, DwarfRegNum<[29]>;172def I6 : Ri<30, "fp">, DwarfRegNum<[30]>;173def I7 : Ri<31, "i7">, DwarfRegNum<[31]>;174 175// Floating-point registers176def F0 : Rf< 0, "f0">, DwarfRegNum<[32]>;177def F1 : Rf< 1, "f1">, DwarfRegNum<[33]>;178def F2 : Rf< 2, "f2">, DwarfRegNum<[34]>;179def F3 : Rf< 3, "f3">, DwarfRegNum<[35]>;180def F4 : Rf< 4, "f4">, DwarfRegNum<[36]>;181def F5 : Rf< 5, "f5">, DwarfRegNum<[37]>;182def F6 : Rf< 6, "f6">, DwarfRegNum<[38]>;183def F7 : Rf< 7, "f7">, DwarfRegNum<[39]>;184def F8 : Rf< 8, "f8">, DwarfRegNum<[40]>;185def F9 : Rf< 9, "f9">, DwarfRegNum<[41]>;186def F10 : Rf<10, "f10">, DwarfRegNum<[42]>;187def F11 : Rf<11, "f11">, DwarfRegNum<[43]>;188def F12 : Rf<12, "f12">, DwarfRegNum<[44]>;189def F13 : Rf<13, "f13">, DwarfRegNum<[45]>;190def F14 : Rf<14, "f14">, DwarfRegNum<[46]>;191def F15 : Rf<15, "f15">, DwarfRegNum<[47]>;192def F16 : Rf<16, "f16">, DwarfRegNum<[48]>;193def F17 : Rf<17, "f17">, DwarfRegNum<[49]>;194def F18 : Rf<18, "f18">, DwarfRegNum<[50]>;195def F19 : Rf<19, "f19">, DwarfRegNum<[51]>;196def F20 : Rf<20, "f20">, DwarfRegNum<[52]>;197def F21 : Rf<21, "f21">, DwarfRegNum<[53]>;198def F22 : Rf<22, "f22">, DwarfRegNum<[54]>;199def F23 : Rf<23, "f23">, DwarfRegNum<[55]>;200def F24 : Rf<24, "f24">, DwarfRegNum<[56]>;201def F25 : Rf<25, "f25">, DwarfRegNum<[57]>;202def F26 : Rf<26, "f26">, DwarfRegNum<[58]>;203def F27 : Rf<27, "f27">, DwarfRegNum<[59]>;204def F28 : Rf<28, "f28">, DwarfRegNum<[60]>;205def F29 : Rf<29, "f29">, DwarfRegNum<[61]>;206def F30 : Rf<30, "f30">, DwarfRegNum<[62]>;207def F31 : Rf<31, "f31">, DwarfRegNum<[63]>;208 209// Aliases of the F* registers used to hold 64-bit fp values (doubles)210def D0 : Rd< 0, "f0", [F0, F1]>, DwarfRegNum<[72]>;211def D1 : Rd< 2, "f2", [F2, F3]>, DwarfRegNum<[73]>;212def D2 : Rd< 4, "f4", [F4, F5]>, DwarfRegNum<[74]>;213def D3 : Rd< 6, "f6", [F6, F7]>, DwarfRegNum<[75]>;214def D4 : Rd< 8, "f8", [F8, F9]>, DwarfRegNum<[76]>;215def D5 : Rd<10, "f10", [F10, F11]>, DwarfRegNum<[77]>;216def D6 : Rd<12, "f12", [F12, F13]>, DwarfRegNum<[78]>;217def D7 : Rd<14, "f14", [F14, F15]>, DwarfRegNum<[79]>;218def D8 : Rd<16, "f16", [F16, F17]>, DwarfRegNum<[80]>;219def D9 : Rd<18, "f18", [F18, F19]>, DwarfRegNum<[81]>;220def D10 : Rd<20, "f20", [F20, F21]>, DwarfRegNum<[82]>;221def D11 : Rd<22, "f22", [F22, F23]>, DwarfRegNum<[83]>;222def D12 : Rd<24, "f24", [F24, F25]>, DwarfRegNum<[84]>;223def D13 : Rd<26, "f26", [F26, F27]>, DwarfRegNum<[85]>;224def D14 : Rd<28, "f28", [F28, F29]>, DwarfRegNum<[86]>;225def D15 : Rd<30, "f30", [F30, F31]>, DwarfRegNum<[87]>;226 227// Co-processor registers228def C0 : Ri< 0, "c0">;229def C1 : Ri< 1, "c1">;230def C2 : Ri< 2, "c2">;231def C3 : Ri< 3, "c3">;232def C4 : Ri< 4, "c4">;233def C5 : Ri< 5, "c5">;234def C6 : Ri< 6, "c6">;235def C7 : Ri< 7, "c7">;236def C8 : Ri< 8, "c8">;237def C9 : Ri< 9, "c9">;238def C10 : Ri<10, "c10">;239def C11 : Ri<11, "c11">;240def C12 : Ri<12, "c12">;241def C13 : Ri<13, "c13">;242def C14 : Ri<14, "c14">;243def C15 : Ri<15, "c15">;244def C16 : Ri<16, "c16">;245def C17 : Ri<17, "c17">;246def C18 : Ri<18, "c18">;247def C19 : Ri<19, "c19">;248def C20 : Ri<20, "c20">;249def C21 : Ri<21, "c21">;250def C22 : Ri<22, "c22">;251def C23 : Ri<23, "c23">;252def C24 : Ri<24, "c24">;253def C25 : Ri<25, "c25">;254def C26 : Ri<26, "c26">;255def C27 : Ri<27, "c27">;256def C28 : Ri<28, "c28">;257def C29 : Ri<29, "c29">;258def C30 : Ri<30, "c30">;259def C31 : Ri<31, "c31">;260 261// Unaliased double precision floating point registers.262// FIXME: Define DwarfRegNum for these registers.263def D16 : SparcReg< 1, "f32">;264def D17 : SparcReg< 3, "f34">;265def D18 : SparcReg< 5, "f36">;266def D19 : SparcReg< 7, "f38">;267def D20 : SparcReg< 9, "f40">;268def D21 : SparcReg<11, "f42">;269def D22 : SparcReg<13, "f44">;270def D23 : SparcReg<15, "f46">;271def D24 : SparcReg<17, "f48">;272def D25 : SparcReg<19, "f50">;273def D26 : SparcReg<21, "f52">;274def D27 : SparcReg<23, "f54">;275def D28 : SparcReg<25, "f56">;276def D29 : SparcReg<27, "f58">;277def D30 : SparcReg<29, "f60">;278def D31 : SparcReg<31, "f62">;279 280// Aliases of the F* registers used to hold 128-bit for values (long doubles).281def Q0 : Rq< 0, "f0", [D0, D1]>;282def Q1 : Rq< 4, "f4", [D2, D3]>;283def Q2 : Rq< 8, "f8", [D4, D5]>;284def Q3 : Rq<12, "f12", [D6, D7]>;285def Q4 : Rq<16, "f16", [D8, D9]>;286def Q5 : Rq<20, "f20", [D10, D11]>;287def Q6 : Rq<24, "f24", [D12, D13]>;288def Q7 : Rq<28, "f28", [D14, D15]>;289def Q8 : Rq< 1, "f32", [D16, D17]>;290def Q9 : Rq< 5, "f36", [D18, D19]>;291def Q10 : Rq< 9, "f40", [D20, D21]>;292def Q11 : Rq<13, "f44", [D22, D23]>;293def Q12 : Rq<17, "f48", [D24, D25]>;294def Q13 : Rq<21, "f52", [D26, D27]>;295def Q14 : Rq<25, "f56", [D28, D29]>;296def Q15 : Rq<29, "f60", [D30, D31]>;297 298// Aliases of the integer registers used for LDD/STD double-word operations299def G0_G1 : Rdi< 0, "g0", [G0, G1]>;300def G2_G3 : Rdi< 2, "g2", [G2, G3]>;301def G4_G5 : Rdi< 4, "g4", [G4, G5]>;302def G6_G7 : Rdi< 6, "g6", [G6, G7]>;303def O0_O1 : Rdi< 8, "o0", [O0, O1]>;304def O2_O3 : Rdi<10, "o2", [O2, O3]>;305def O4_O5 : Rdi<12, "o4", [O4, O5]>;306def O6_O7 : Rdi<14, "o6", [O6, O7]>;307def L0_L1 : Rdi<16, "l0", [L0, L1]>;308def L2_L3 : Rdi<18, "l2", [L2, L3]>;309def L4_L5 : Rdi<20, "l4", [L4, L5]>;310def L6_L7 : Rdi<22, "l6", [L6, L7]>;311def I0_I1 : Rdi<24, "i0", [I0, I1]>;312def I2_I3 : Rdi<26, "i2", [I2, I3]>;313def I4_I5 : Rdi<28, "i4", [I4, I5]>;314def I6_I7 : Rdi<30, "i6", [I6, I7]>;315 316// Aliases of the co-processor registers used for LDD/STD double-word operations317def C0_C1 : Rdi< 0, "c0", [C0, C1]>;318def C2_C3 : Rdi< 2, "c2", [C2, C3]>;319def C4_C5 : Rdi< 4, "c4", [C4, C5]>;320def C6_C7 : Rdi< 6, "c6", [C6, C7]>;321def C8_C9 : Rdi< 8, "c8", [C8, C9]>;322def C10_C11 : Rdi<10, "c10", [C10, C11]>;323def C12_C13 : Rdi<12, "c12", [C12, C13]>;324def C14_C15 : Rdi<14, "c14", [C14, C15]>;325def C16_C17 : Rdi<16, "c16", [C16, C17]>;326def C18_C19 : Rdi<18, "c18", [C18, C19]>;327def C20_C21 : Rdi<20, "c20", [C20, C21]>;328def C22_C23 : Rdi<22, "c22", [C22, C23]>;329def C24_C25 : Rdi<24, "c24", [C24, C25]>;330def C26_C27 : Rdi<26, "c26", [C26, C27]>;331def C28_C29 : Rdi<28, "c28", [C28, C29]>;332def C30_C31 : Rdi<30, "c30", [C30, C31]>;333 334// Register classes.335//336// FIXME: the register order should be defined in terms of the preferred337// allocation order...338//339// This register class should not be used to hold i64 values, use the I64Regs340// register class for that. The i64 type is included here to allow i64 patterns341// using the integer instructions.342def IntRegs : RegisterClass<"SP", [i32, i64], 32,343 (add (sequence "I%u", 0, 7),344 (sequence "G%u", 0, 7),345 (sequence "L%u", 0, 7),346 (sequence "O%u", 0, 7))>;347 348// Should be in the same order as IntRegs.349def IntPair : RegisterClass<"SP", [v2i32], 64,350 (add I0_I1, I2_I3, I4_I5, I6_I7,351 G0_G1, G2_G3, G4_G5, G6_G7,352 L0_L1, L2_L3, L4_L5, L6_L7,353 O0_O1, O2_O3, O4_O5, O6_O7)>;354 355// Register class for 64-bit mode, with a 64-bit spill slot size.356// These are the same as the 32-bit registers, so TableGen will consider this357// to be a sub-class of IntRegs. That works out because requiring a 64-bit358// spill slot is a stricter constraint than only requiring a 32-bit spill slot.359def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;360 361// Floating point register classes.362def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;363def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;364def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;365 366// The Low?FPRegs classes are used only for inline-asm constraints.367def LowDFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;368def LowQFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 7)>;369 370// Floating point control register classes.371def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;372 373// GPR argument registers.374def GPROutgoingArg : RegisterClass<"SP", [i32, i64], 32, (sequence "O%u", 0, 5)>;375def GPRIncomingArg : RegisterClass<"SP", [i32, i64], 32, (sequence "I%u", 0, 5)>;376 377let isAllocatable = 0 in {378 // Ancillary state registers379 // FIXME: TICK is special-cased here as it can be accessed380 // from the ASR (as ASR4) or the privileged register set.381 // For now this is required for the parser to work.382 def ASRRegs : RegisterClass<"SP", [i32], 32,383 (add Y, TICK, (sequence "ASR%u", 1, 31))>;384 385 // This register class should not be used to hold i64 values.386 def CoprocRegs : RegisterClass<"SP", [i32], 32,387 (add (sequence "C%u", 0, 31))>;388 389 // Should be in the same order as CoprocRegs.390 def CoprocPair : RegisterClass<"SP", [v2i32], 64,391 (add C0_C1, C2_C3, C4_C5, C6_C7,392 C8_C9, C10_C11, C12_C13, C14_C15,393 C16_C17, C18_C19, C20_C21, C22_C23,394 C24_C25, C26_C27, C28_C29, C30_C31)>;395}396 397// Privileged Registers398def PRRegs : RegisterClass<"SP", [i64], 64,399 (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,400 CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE, GL, VER)>;401