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1//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H10#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H11 12#include "llvm/Support/DataTypes.h"13 14#include <memory>15 16namespace llvm {17 18class MCAsmBackend;19class MCCodeEmitter;20class MCContext;21class MCInstrInfo;22class MCObjectTargetWriter;23class MCRegisterInfo;24class MCSubtargetInfo;25class MCTargetOptions;26class Target;27 28namespace SystemZMC {29// How many bytes are in the ABI-defined, caller-allocated part of30// a stack frame.31const int64_t ELFCallFrameSize = 160;32 33// The offset of the DWARF CFA from the incoming stack pointer.34const int64_t ELFCFAOffsetFromInitialSP = ELFCallFrameSize;35 36// Maps of asm register numbers to LLVM register numbers, with 0 indicating37// an invalid register. In principle we could use 32-bit and 64-bit register38// classes directly, provided that we relegated the GPR allocation order39// in SystemZRegisterInfo.td to an AltOrder and left the default order40// as %r0-%r15. It seems better to provide the same interface for41// all classes though.42extern const unsigned GR32Regs[16];43extern const unsigned GRH32Regs[16];44extern const unsigned GR64Regs[16];45extern const unsigned GR128Regs[16];46extern const unsigned FP16Regs[16];47extern const unsigned FP32Regs[16];48extern const unsigned FP64Regs[16];49extern const unsigned FP128Regs[16];50extern const unsigned VR16Regs[32];51extern const unsigned VR32Regs[32];52extern const unsigned VR64Regs[32];53extern const unsigned VR128Regs[32];54extern const unsigned AR32Regs[16];55extern const unsigned CR64Regs[16];56 57// Return the 0-based number of the first architectural register that58// contains the given LLVM register. E.g. R1D -> 1.59unsigned getFirstReg(unsigned Reg);60 61// Return the given register as a GR64.62inline unsigned getRegAsGR64(unsigned Reg) {63 return GR64Regs[getFirstReg(Reg)];64}65 66// Return the given register as a low GR32.67inline unsigned getRegAsGR32(unsigned Reg) {68 return GR32Regs[getFirstReg(Reg)];69}70 71// Return the given register as a high GR32.72inline unsigned getRegAsGRH32(unsigned Reg) {73 return GRH32Regs[getFirstReg(Reg)];74}75 76// Return the given register as a VR128.77inline unsigned getRegAsVR128(unsigned Reg) {78 return VR128Regs[getFirstReg(Reg)];79}80} // end namespace SystemZMC81 82MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,83 MCContext &Ctx);84 85MCAsmBackend *createSystemZMCAsmBackend(const Target &T,86 const MCSubtargetInfo &STI,87 const MCRegisterInfo &MRI,88 const MCTargetOptions &Options);89 90std::unique_ptr<MCObjectTargetWriter>91createSystemZELFObjectWriter(uint8_t OSABI);92std::unique_ptr<MCObjectTargetWriter> createSystemZGOFFObjectWriter();93} // end namespace llvm94 95// Defines symbolic names for SystemZ registers.96// This defines a mapping from register name to register number.97#define GET_REGINFO_ENUM98#include "SystemZGenRegisterInfo.inc"99 100// Defines symbolic names for the SystemZ instructions.101#define GET_INSTRINFO_ENUM102#define GET_INSTRINFO_MC_HELPER_DECLS103#include "SystemZGenInstrInfo.inc"104 105#define GET_SUBTARGETINFO_ENUM106#include "SystemZGenSubtargetInfo.inc"107 108#endif109