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1//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the interfaces that SystemZ uses to lower LLVM code into a10// selection DAG.11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H15#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H16 17#include "SystemZ.h"18#include "SystemZInstrInfo.h"19#include "llvm/CodeGen/MachineBasicBlock.h"20#include "llvm/CodeGen/SelectionDAG.h"21#include "llvm/CodeGen/TargetLowering.h"22#include <optional>23 24namespace llvm {25 26namespace SystemZICMP {27// Describes whether an integer comparison needs to be signed or unsigned,28// or whether either type is OK.29enum {30 Any,31 UnsignedOnly,32 SignedOnly33};34} // end namespace SystemZICMP35 36class SystemZSubtarget;37 38class SystemZTargetLowering : public TargetLowering {39public:40 explicit SystemZTargetLowering(const TargetMachine &TM,41 const SystemZSubtarget &STI);42 43 bool useSoftFloat() const override;44 45 // Override TargetLowering.46 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {47 return MVT::i32;48 }49 unsigned getVectorIdxWidth(const DataLayout &DL) const override {50 // Only the lower 12 bits of an element index are used, so we don't51 // want to clobber the upper 32 bits of a GPR unnecessarily.52 return 32;53 }54 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)55 const override {56 // Widen subvectors to the full width rather than promoting integer57 // elements. This is better because:58 //59 // (a) it means that we can handle the ABI for passing and returning60 // sub-128 vectors without having to handle them as legal types.61 //62 // (b) we don't have instructions to extend on load and truncate on store,63 // so promoting the integers is less efficient.64 //65 // (c) there are no multiplication instructions for the widest integer66 // type (v2i64).67 if (VT.getScalarSizeInBits() % 8 == 0)68 return TypeWidenVector;69 return TargetLoweringBase::getPreferredVectorAction(VT);70 }71 unsigned72 getNumRegisters(LLVMContext &Context, EVT VT,73 std::optional<MVT> RegisterVT) const override {74 // i128 inline assembly operand.75 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)76 return 1;77 return TargetLowering::getNumRegisters(Context, VT);78 }79 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,80 EVT VT) const override {81 // 128-bit single-element vector types are passed like other vectors,82 // not like their element type.83 if (VT.isVector() && VT.getSizeInBits() == 128 &&84 VT.getVectorNumElements() == 1)85 return MVT::v16i8;86 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);87 }88 bool isCheapToSpeculateCtlz(Type *) const override { return true; }89 bool isCheapToSpeculateCttz(Type *) const override { return true; }90 bool preferZeroCompareBranch() const override { return true; }91 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {92 ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));93 return Mask && Mask->getValue().isIntN(16);94 }95 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {96 return VT.isScalarInteger();97 }98 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,99 EVT) const override;100 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,101 EVT VT) const override;102 bool isFPImmLegal(const APFloat &Imm, EVT VT,103 bool ForCodeSize) const override;104 bool ShouldShrinkFPConstant(EVT VT) const override {105 // Do not shrink 64-bit FP constpool entries since LDEB is slower than106 // LD, and having the full constant in memory enables reg/mem opcodes.107 return VT != MVT::f64;108 }109 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,110 MachineBasicBlock *MBB) const;111 112 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,113 MachineBasicBlock *MBB) const;114 115 bool hasInlineStackProbe(const MachineFunction &MF) const override;116 AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override;117 AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override;118 AtomicExpansionKind119 shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override;120 bool isLegalICmpImmediate(int64_t Imm) const override;121 bool isLegalAddImmediate(int64_t Imm) const override;122 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,123 unsigned AS,124 Instruction *I = nullptr) const override;125 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,126 MachineMemOperand::Flags Flags,127 unsigned *Fast) const override;128 bool129 findOptimalMemOpLowering(LLVMContext &Context, std::vector<EVT> &MemOps,130 unsigned Limit, const MemOp &Op, unsigned DstAS,131 unsigned SrcAS,132 const AttributeList &FuncAttributes) const override;133 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,134 const AttributeList &FuncAttributes) const override;135 bool isTruncateFree(Type *, Type *) const override;136 bool isTruncateFree(EVT, EVT) const override;137 138 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,139 bool MathUsed) const override {140 // Form add and sub with overflow intrinsics regardless of any extra141 // users of the math result.142 return VT == MVT::i32 || VT == MVT::i64 || VT == MVT::i128;143 }144 145 bool shouldConsiderGEPOffsetSplit() const override { return true; }146 147 bool preferSelectsOverBooleanArithmetic(EVT VT) const override {148 return true;149 }150 151 // This function currently returns cost for srl/ipm/cc sequence for merging.152 CondMergingParams153 getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,154 const Value *Rhs) const override;155 156 // Handle Lowering flag assembly outputs.157 SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,158 const SDLoc &DL,159 const AsmOperandInfo &Constraint,160 SelectionDAG &DAG) const override;161 162 std::pair<unsigned, const TargetRegisterClass *>163 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,164 StringRef Constraint, MVT VT) const override;165 TargetLowering::ConstraintType166 getConstraintType(StringRef Constraint) const override;167 TargetLowering::ConstraintWeight168 getSingleConstraintMatchWeight(AsmOperandInfo &info,169 const char *constraint) const override;170 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,171 std::vector<SDValue> &Ops,172 SelectionDAG &DAG) const override;173 174 InlineAsm::ConstraintCode175 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {176 if (ConstraintCode.size() == 1) {177 switch(ConstraintCode[0]) {178 default:179 break;180 case 'o':181 return InlineAsm::ConstraintCode::o;182 case 'Q':183 return InlineAsm::ConstraintCode::Q;184 case 'R':185 return InlineAsm::ConstraintCode::R;186 case 'S':187 return InlineAsm::ConstraintCode::S;188 case 'T':189 return InlineAsm::ConstraintCode::T;190 }191 } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {192 switch (ConstraintCode[1]) {193 default:194 break;195 case 'Q':196 return InlineAsm::ConstraintCode::ZQ;197 case 'R':198 return InlineAsm::ConstraintCode::ZR;199 case 'S':200 return InlineAsm::ConstraintCode::ZS;201 case 'T':202 return InlineAsm::ConstraintCode::ZT;203 }204 }205 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);206 }207 208 Register getRegisterByName(const char *RegName, LLT VT,209 const MachineFunction &MF) const override;210 211 /// If a physical register, this returns the register that receives the212 /// exception address on entry to an EH pad.213 Register214 getExceptionPointerRegister(const Constant *PersonalityFn) const override;215 216 /// If a physical register, this returns the register that receives the217 /// exception typeid on entry to a landing pad.218 Register219 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;220 221 /// Override to support customized stack guard loading.222 bool useLoadStackGuardNode(const Module &M) const override { return true; }223 void insertSSPDeclarations(Module &M) const override {224 }225 226 MachineBasicBlock *227 EmitInstrWithCustomInserter(MachineInstr &MI,228 MachineBasicBlock *BB) const override;229 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;230 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,231 SelectionDAG &DAG) const override;232 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,233 SelectionDAG &DAG) const override;234 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;235 bool allowTruncateForTailCall(Type *, Type *) const override;236 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;237 bool splitValueIntoRegisterParts(238 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,239 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)240 const override;241 SDValue joinRegisterPartsIntoValue(242 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,243 unsigned NumParts, MVT PartVT, EVT ValueVT,244 std::optional<CallingConv::ID> CC) const override;245 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,246 bool isVarArg,247 const SmallVectorImpl<ISD::InputArg> &Ins,248 const SDLoc &DL, SelectionDAG &DAG,249 SmallVectorImpl<SDValue> &InVals) const override;250 SDValue LowerCall(CallLoweringInfo &CLI,251 SmallVectorImpl<SDValue> &InVals) const override;252 253 std::pair<SDValue, SDValue>254 makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName,255 EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv,256 bool IsSigned, SDLoc DL, bool DoesNotReturn,257 bool IsReturnValueUsed) const;258 259 SDValue useLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, MVT VT, SDValue Arg,260 SDLoc DL, SDValue Chain, bool IsStrict) const;261 262 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,263 bool isVarArg,264 const SmallVectorImpl<ISD::OutputArg> &Outs,265 LLVMContext &Context,266 const Type *RetTy) const override;267 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,268 const SmallVectorImpl<ISD::OutputArg> &Outs,269 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,270 SelectionDAG &DAG) const override;271 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;272 273 /// Determine which of the bits specified in Mask are known to be either274 /// zero or one and return them in the KnownZero/KnownOne bitsets.275 void computeKnownBitsForTargetNode(const SDValue Op,276 KnownBits &Known,277 const APInt &DemandedElts,278 const SelectionDAG &DAG,279 unsigned Depth = 0) const override;280 281 /// Determine the number of bits in the operation that are sign bits.282 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,283 const APInt &DemandedElts,284 const SelectionDAG &DAG,285 unsigned Depth) const override;286 287 bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(288 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,289 bool PoisonOnly, unsigned Depth) const override;290 291 ISD::NodeType getExtendForAtomicOps() const override {292 return ISD::ANY_EXTEND;293 }294 ISD::NodeType getExtendForAtomicCmpSwapArg() const override {295 return ISD::ZERO_EXTEND;296 }297 298 bool supportSwiftError() const override {299 return true;300 }301 302 unsigned getStackProbeSize(const MachineFunction &MF) const;303 bool hasAndNot(SDValue Y) const override;304 305private:306 const SystemZSubtarget &Subtarget;307 308 // Implement LowerOperation for individual opcodes.309 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,310 const SDLoc &DL, EVT VT,311 SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;312 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,313 EVT VT, ISD::CondCode CC,314 SDValue CmpOp0, SDValue CmpOp1,315 SDValue Chain = SDValue(),316 bool IsSignaling = false) const;317 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;318 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,319 bool IsSignaling) const;320 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;321 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;322 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,323 SelectionDAG &DAG) const;324 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,325 SelectionDAG &DAG, unsigned Opcode,326 SDValue GOTOffset) const;327 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;328 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,329 SelectionDAG &DAG) const;330 SDValue lowerBlockAddress(BlockAddressSDNode *Node,331 SelectionDAG &DAG) const;332 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;333 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;334 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;335 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;336 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;337 SDValue lowerVASTART_ELF(SDValue Op, SelectionDAG &DAG) const;338 SDValue lowerVASTART_XPLINK(SDValue Op, SelectionDAG &DAG) const;339 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;340 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;341 SDValue lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, SelectionDAG &DAG) const;342 SDValue lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, SelectionDAG &DAG) const;343 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;344 SDValue lowerMULH(SDValue Op, SelectionDAG &DAG, unsigned Opcode) const;345 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;346 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;347 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;348 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;349 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;350 SDValue lowerUADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;351 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;352 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;353 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;354 SDValue lowerVECREDUCE_ADD(SDValue Op, SelectionDAG &DAG) const;355 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;356 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;357 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;358 SDValue lowerATOMIC_LDST_I128(SDValue Op, SelectionDAG &DAG) const;359 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,360 unsigned Opcode) const;361 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;362 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;363 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;364 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;365 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;366 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;367 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;368 bool isVectorElementLoad(SDValue Op) const;369 SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,370 SmallVectorImpl<SDValue> &Elems) const;371 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;372 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;373 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;374 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;375 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;376 SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;377 SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;378 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;379 SDValue lowerFSHL(SDValue Op, SelectionDAG &DAG) const;380 SDValue lowerFSHR(SDValue Op, SelectionDAG &DAG) const;381 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;382 SDValue lower_FP_TO_INT(SDValue Op, SelectionDAG &DAG) const;383 SDValue lower_INT_TO_FP(SDValue Op, SelectionDAG &DAG) const;384 SDValue lowerLoadF16(SDValue Op, SelectionDAG &DAG) const;385 SDValue lowerStoreF16(SDValue Op, SelectionDAG &DAG) const;386 387 SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;388 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;389 SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;390 391 bool canTreatAsByteVector(EVT VT) const;392 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,393 unsigned Index, DAGCombinerInfo &DCI,394 bool Force) const;395 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,396 DAGCombinerInfo &DCI) const;397 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;398 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;399 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;400 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;401 bool canLoadStoreByteSwapped(EVT VT) const;402 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;403 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;404 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;405 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;406 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;407 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;408 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;409 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;410 SDValue combineFCOPYSIGN(SDNode *N, DAGCombinerInfo &DCI) const;411 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;412 SDValue combineSETCC(SDNode *N, DAGCombinerInfo &DCI) const;413 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;414 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;415 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;416 SDValue combineShiftToMulAddHigh(SDNode *N, DAGCombinerInfo &DCI) const;417 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;418 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;419 SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;420 421 SDValue unwrapAddress(SDValue N) const override;422 423 // If the last instruction before MBBI in MBB was some form of COMPARE,424 // try to replace it with a COMPARE AND BRANCH just before MBBI.425 // CCMask and Target are the BRC-like operands for the branch.426 // Return true if the change was made.427 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,428 MachineBasicBlock::iterator MBBI,429 unsigned CCMask,430 MachineBasicBlock *Target) const;431 432 // Implement EmitInstrWithCustomInserter for individual operation types.433 MachineBasicBlock *emitAdjCallStack(MachineInstr &MI,434 MachineBasicBlock *BB) const;435 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;436 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,437 unsigned StoreOpcode, unsigned STOCOpcode,438 bool Invert) const;439 MachineBasicBlock *emitICmp128Hi(MachineInstr &MI, MachineBasicBlock *BB,440 bool Unsigned) const;441 MachineBasicBlock *emitPair128(MachineInstr &MI,442 MachineBasicBlock *MBB) const;443 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,444 bool ClearEven) const;445 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,446 MachineBasicBlock *BB,447 unsigned BinOpcode,448 bool Invert = false) const;449 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,450 MachineBasicBlock *MBB,451 unsigned CompareOpcode,452 unsigned KeepOldMask) const;453 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,454 MachineBasicBlock *BB) const;455 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,456 unsigned Opcode,457 bool IsMemset = false) const;458 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,459 unsigned Opcode) const;460 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,461 MachineBasicBlock *MBB,462 unsigned Opcode, bool NoFloat) const;463 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,464 MachineBasicBlock *MBB,465 unsigned Opcode) const;466 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,467 MachineBasicBlock *MBB) const;468 469 SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;470 471 MachineMemOperand::Flags472 getTargetMMOFlags(const Instruction &I) const override;473 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;474 475private:476 bool isInternal(const Function *Fn) const;477 mutable std::map<const Function *, bool> IsInternalCache;478 void verifyNarrowIntegerArgs_Call(const SmallVectorImpl<ISD::OutputArg> &Outs,479 const Function *F, SDValue Callee) const;480 void verifyNarrowIntegerArgs_Ret(const SmallVectorImpl<ISD::OutputArg> &Outs,481 const Function *F) const;482 bool483 verifyNarrowIntegerArgs(const SmallVectorImpl<ISD::OutputArg> &Outs) const;484 485public:486};487 488struct SystemZVectorConstantInfo {489private:490 APInt IntBits; // The 128 bits as an integer.491 APInt SplatBits; // Smallest splat value.492 APInt SplatUndef; // Bits correspoding to undef operands of the BVN.493 unsigned SplatBitSize = 0;494 bool isFP128 = false;495public:496 unsigned Opcode = 0;497 SmallVector<unsigned, 2> OpVals;498 MVT VecVT;499 SystemZVectorConstantInfo(APInt IntImm);500 SystemZVectorConstantInfo(APFloat FPImm)501 : SystemZVectorConstantInfo(FPImm.bitcastToAPInt()) {502 isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());503 }504 SystemZVectorConstantInfo(BuildVectorSDNode *BVN);505 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);506};507 508} // end namespace llvm509 510#endif511