247 lines · plain
1//==- SystemZInstrDFP.td - Floating-point SystemZ instructions -*- tblgen-*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// The instructions in this file implement SystemZ decimal floating-point10// arithmetic. These instructions are inot currently used for code generation,11// are provided for use with the assembler and disassembler only. If LLVM12// ever supports decimal floating-point types (_Decimal64 etc.), they can13// also be used for code generation for those types.14//15//===----------------------------------------------------------------------===//16 17//===----------------------------------------------------------------------===//18// Move instructions19//===----------------------------------------------------------------------===//20 21// Load and test.22let Uses = [FPC], Defs = [CC] in {23 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;24 def LTXTR : UnaryRRE<"ltxtr", 0xB3DE, null_frag, FP128, FP128>;25}26 27 28//===----------------------------------------------------------------------===//29// Conversion instructions30//===----------------------------------------------------------------------===//31 32// Convert floating-point values to narrower representations. The destination33// of LDXTR is a 128-bit value, but only the first register of the pair is used.34let Uses = [FPC] in {35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;36 def LDXTR : TernaryRRFe<"ldxtr", 0xB3DD, FP128, FP128>;37}38 39// Extend floating-point values to wider representations.40let Uses = [FPC] in {41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;42 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;43}44 45// Convert a signed integer value to a floating-point one.46let Uses = [FPC] in {47 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;48 def CXGTR : UnaryRRE<"cxgtr", 0xB3F9, null_frag, FP128, GR64>;49 let Predicates = [FeatureFPExtension] in {50 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;51 def CXGTRA : TernaryRRFe<"cxgtra", 0xB3F9, FP128, GR64>;52 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;53 def CXFTR : TernaryRRFe<"cxftr", 0xB959, FP128, GR32>;54 }55}56 57// Convert an unsigned integer value to a floating-point one.58let Uses = [FPC], Predicates = [FeatureFPExtension] in {59 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;60 def CXLGTR : TernaryRRFe<"cxlgtr", 0xB95A, FP128, GR64>;61 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;62 def CXLFTR : TernaryRRFe<"cxlftr", 0xB95B, FP128, GR32>;63}64 65// Convert a floating-point value to a signed integer value.66let Uses = [FPC], Defs = [CC] in {67 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;68 def CGXTR : BinaryRRFe<"cgxtr", 0xB3E9, GR64, FP128>;69 let Predicates = [FeatureFPExtension] in {70 def CGDTRA : TernaryRRFe<"cgdtra", 0xB3E1, GR64, FP64>;71 def CGXTRA : TernaryRRFe<"cgxtra", 0xB3E9, GR64, FP128>;72 def CFDTR : TernaryRRFe<"cfdtr", 0xB941, GR32, FP64>;73 def CFXTR : TernaryRRFe<"cfxtr", 0xB949, GR32, FP128>;74 }75}76 77// Convert a floating-point value to an unsigned integer value.78let Uses = [FPC], Defs = [CC] in {79 let Predicates = [FeatureFPExtension] in {80 def CLGDTR : TernaryRRFe<"clgdtr", 0xB942, GR64, FP64>;81 def CLGXTR : TernaryRRFe<"clgxtr", 0xB94A, GR64, FP128>;82 def CLFDTR : TernaryRRFe<"clfdtr", 0xB943, GR32, FP64>;83 def CLFXTR : TernaryRRFe<"clfxtr", 0xB94B, GR32, FP128>;84 }85}86 87// Convert a packed value to a floating-point one.88def CDSTR : UnaryRRE<"cdstr", 0xB3F3, null_frag, FP64, GR64>;89def CXSTR : UnaryRRE<"cxstr", 0xB3FB, null_frag, FP128, GR128>;90def CDUTR : UnaryRRE<"cdutr", 0xB3F2, null_frag, FP64, GR64>;91def CXUTR : UnaryRRE<"cxutr", 0xB3FA, null_frag, FP128, GR128>;92 93// Convert a floating-point value to a packed value.94def CSDTR : BinaryRRFd<"csdtr", 0xB3E3, GR64, FP64>;95def CSXTR : BinaryRRFd<"csxtr", 0xB3EB, GR128, FP128>;96def CUDTR : UnaryRRE<"cudtr", 0xB3E2, null_frag, GR64, FP64>;97def CUXTR : UnaryRRE<"cuxtr", 0xB3EA, null_frag, GR128, FP128>;98 99// Convert from/to memory values in the zoned format.100let Predicates = [FeatureDFPZonedConversion] in {101 def CDZT : BinaryRSL<"cdzt", 0xEDAA, FP64>;102 def CXZT : BinaryRSL<"cxzt", 0xEDAB, FP128>;103 def CZDT : StoreBinaryRSL<"czdt", 0xEDA8, FP64>;104 def CZXT : StoreBinaryRSL<"czxt", 0xEDA9, FP128>;105}106 107// Convert from/to memory values in the packed format.108let Predicates = [FeatureDFPPackedConversion] in {109 def CDPT : BinaryRSL<"cdpt", 0xEDAE, FP64>;110 def CXPT : BinaryRSL<"cxpt", 0xEDAF, FP128>;111 def CPDT : StoreBinaryRSL<"cpdt", 0xEDAC, FP64>;112 def CPXT : StoreBinaryRSL<"cpxt", 0xEDAD, FP128>;113}114 115// Perform floating-point operation.116let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in117 def PFPO : SideEffectInherentE<"pfpo", 0x010A>;118 119 120//===----------------------------------------------------------------------===//121// Unary arithmetic122//===----------------------------------------------------------------------===//123 124// Round to an integer, with the second operand (M3) specifying the rounding125// mode. M4 can be set to 4 to suppress detection of inexact conditions.126let Uses = [FPC] in {127 def FIDTR : TernaryRRFe<"fidtr", 0xB3D7, FP64, FP64>;128 def FIXTR : TernaryRRFe<"fixtr", 0xB3DF, FP128, FP128>;129}130 131// Extract biased exponent.132def EEDTR : UnaryRRE<"eedtr", 0xB3E5, null_frag, GR64, FP64>;133def EEXTR : UnaryRRE<"eextr", 0xB3ED, null_frag, GR64, FP128>;134 135// Extract significance.136def ESDTR : UnaryRRE<"esdtr", 0xB3E7, null_frag, GR64, FP64>;137def ESXTR : UnaryRRE<"esxtr", 0xB3EF, null_frag, GR64, FP128>;138 139 140//===----------------------------------------------------------------------===//141// Binary arithmetic142//===----------------------------------------------------------------------===//143 144// Addition.145let Uses = [FPC], Defs = [CC] in {146 let isCommutable = 1 in {147 def ADTR : BinaryRRFa<"adtr", 0xB3D2, null_frag, FP64, FP64, FP64>;148 def AXTR : BinaryRRFa<"axtr", 0xB3DA, null_frag, FP128, FP128, FP128>;149 }150 let Predicates = [FeatureFPExtension] in {151 def ADTRA : TernaryRRFa<"adtra", 0xB3D2, FP64, FP64, FP64>;152 def AXTRA : TernaryRRFa<"axtra", 0xB3DA, FP128, FP128, FP128>;153 }154}155 156// Subtraction.157let Uses = [FPC], Defs = [CC] in {158 def SDTR : BinaryRRFa<"sdtr", 0xB3D3, null_frag, FP64, FP64, FP64>;159 def SXTR : BinaryRRFa<"sxtr", 0xB3DB, null_frag, FP128, FP128, FP128>;160 let Predicates = [FeatureFPExtension] in {161 def SDTRA : TernaryRRFa<"sdtra", 0xB3D3, FP64, FP64, FP64>;162 def SXTRA : TernaryRRFa<"sxtra", 0xB3DB, FP128, FP128, FP128>;163 }164}165 166// Multiplication.167let Uses = [FPC] in {168 let isCommutable = 1 in {169 def MDTR : BinaryRRFa<"mdtr", 0xB3D0, null_frag, FP64, FP64, FP64>;170 def MXTR : BinaryRRFa<"mxtr", 0xB3D8, null_frag, FP128, FP128, FP128>;171 }172 let Predicates = [FeatureFPExtension] in {173 def MDTRA : TernaryRRFa<"mdtra", 0xB3D0, FP64, FP64, FP64>;174 def MXTRA : TernaryRRFa<"mxtra", 0xB3D8, FP128, FP128, FP128>;175 }176}177 178// Division.179let Uses = [FPC] in {180 def DDTR : BinaryRRFa<"ddtr", 0xB3D1, null_frag, FP64, FP64, FP64>;181 def DXTR : BinaryRRFa<"dxtr", 0xB3D9, null_frag, FP128, FP128, FP128>;182 let Predicates = [FeatureFPExtension] in {183 def DDTRA : TernaryRRFa<"ddtra", 0xB3D1, FP64, FP64, FP64>;184 def DXTRA : TernaryRRFa<"dxtra", 0xB3D9, FP128, FP128, FP128>;185 }186}187 188// Quantize.189let Uses = [FPC] in {190 def QADTR : TernaryRRFb<"qadtr", 0xB3F5, FP64, FP64, FP64>;191 def QAXTR : TernaryRRFb<"qaxtr", 0xB3FD, FP128, FP128, FP128>;192}193 194// Reround.195let Uses = [FPC] in {196 def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, GR32, FP64>;197 def RRXTR : TernaryRRFb<"rrxtr", 0xB3FF, FP128, GR32, FP128>;198}199 200// Shift significand left/right.201def SLDT : BinaryRXF<"sldt", 0xED40, null_frag, FP64, FP64, null_frag, 0>;202def SLXT : BinaryRXF<"slxt", 0xED48, null_frag, FP128, FP128, null_frag, 0>;203def SRDT : BinaryRXF<"srdt", 0xED41, null_frag, FP64, FP64, null_frag, 0>;204def SRXT : BinaryRXF<"srxt", 0xED49, null_frag, FP128, FP128, null_frag, 0>;205 206// Insert biased exponent.207def IEDTR : BinaryRRFb<"iedtr", 0xB3F6, null_frag, FP64, GR64, FP64>;208def IEXTR : BinaryRRFb<"iextr", 0xB3FE, null_frag, FP128, GR64, FP128>;209 210 211//===----------------------------------------------------------------------===//212// Comparisons213//===----------------------------------------------------------------------===//214 215// Compare.216let Uses = [FPC], Defs = [CC] in {217 def CDTR : CompareRRE<"cdtr", 0xB3E4, null_frag, FP64, FP64>;218 def CXTR : CompareRRE<"cxtr", 0xB3EC, null_frag, FP128, FP128>;219}220 221// Compare and signal.222let Uses = [FPC], Defs = [CC] in {223 def KDTR : CompareRRE<"kdtr", 0xB3E0, null_frag, FP64, FP64>;224 def KXTR : CompareRRE<"kxtr", 0xB3E8, null_frag, FP128, FP128>;225}226 227// Compare biased exponent.228let Defs = [CC] in {229 def CEDTR : CompareRRE<"cedtr", 0xB3F4, null_frag, FP64, FP64>;230 def CEXTR : CompareRRE<"cextr", 0xB3FC, null_frag, FP128, FP128>;231}232 233// Test Data Class.234let Defs = [CC] in {235 def TDCET : TestRXE<"tdcet", 0xED50, null_frag, FP32>;236 def TDCDT : TestRXE<"tdcdt", 0xED54, null_frag, FP64>;237 def TDCXT : TestRXE<"tdcxt", 0xED58, null_frag, FP128>;238}239 240// Test Data Group.241let Defs = [CC] in {242 def TDGET : TestRXE<"tdget", 0xED51, null_frag, FP32>;243 def TDGDT : TestRXE<"tdgdt", 0xED55, null_frag, FP64>;244 def TDGXT : TestRXE<"tdgxt", 0xED59, null_frag, FP128>;245}246 247