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1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9// TODO: Most floating-point instructions (except for simple moves and the10// like) can raise exceptions -- should they have hasSideEffects=1 ?11 12//===----------------------------------------------------------------------===//13// Select instructions14//===----------------------------------------------------------------------===//15 16// C's ?: operator for floating-point operands.17let Predicates = [FeatureVector] in {18 def SelectVR32 : SelectWrapper<f32, VR32>;19 def SelectVR64 : SelectWrapper<f64, VR64>;20}21def SelectF32 : SelectWrapper<f32, FP32>;22def SelectF64 : SelectWrapper<f64, FP64>;23let Predicates = [FeatureNoVectorEnhancements1] in24 def SelectF128 : SelectWrapper<f128, FP128>;25let Predicates = [FeatureVectorEnhancements1] in26 def SelectVR128 : SelectWrapper<f128, VR128>;27 28defm CondStoreF32 : CondStores<FP32, simple_store,29 simple_load, bdxaddr20only>;30defm CondStoreF64 : CondStores<FP64, simple_store,31 simple_load, bdxaddr20only>;32 33//===----------------------------------------------------------------------===//34// Move instructions35//===----------------------------------------------------------------------===//36 37// Load zero.38let isAsCheapAsAMove = 1, isMoveImm = 1 in {39 let isCodeGenOnly = 1 in40 def LZER_16 : InherentRRE<"lzer", 0xB374, FP16, fpimm0>;41 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>;42 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>;43 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>;44}45 46// Moves between two floating-point registers.47let isMoveReg = 1 in {48 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;49 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;50 def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;51 // For z13 we prefer LDR over LER to avoid partial register dependencies.52 let isCodeGenOnly = 1 in {53 def LER16 : UnaryRR<"ler", 0x38, null_frag, FP16, FP16>;54 def LDR16 : UnaryRR<"ldr", 0x28, null_frag, FP16, FP16>;55 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;56 }57}58 59 60// Moves between two floating-point registers that also set the condition61// codes. Note that these instructions will turn SNaNs into QNaNs and should62// not be used for comparison if the result will be used afterwards.63let Uses = [FPC], mayRaiseFPException = 1,64 Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {65 def LTEBR : UnaryRRE<"ltebr", 0xB302, null_frag, FP32, FP32>;66 def LTDBR : UnaryRRE<"ltdbr", 0xB312, null_frag, FP64, FP64>;67 def LTXBR : UnaryRRE<"ltxbr", 0xB342, null_frag, FP128, FP128>;68}69 70// Use a load-and-test for compare against zero (via a pseudo to simplify71// instruction selection).72let Uses = [FPC], mayRaiseFPException = 1,73 Defs = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {74 def LTEBRCompare_Pseudo : Pseudo<(outs), (ins FP32:$R1), []>;75 def LTDBRCompare_Pseudo : Pseudo<(outs), (ins FP64:$R1), []>;76 def LTXBRCompare_Pseudo : Pseudo<(outs), (ins FP128:$R1), []>;77}78defm : CompareZeroFP<LTEBRCompare_Pseudo, FP32>;79defm : CompareZeroFP<LTDBRCompare_Pseudo, FP64>;80let Predicates = [FeatureNoVectorEnhancements1] in81 defm : CompareZeroFP<LTXBRCompare_Pseudo, FP128>;82 83// Moves between 64-bit integer and floating-point registers.84def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;85def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;86 87// fcopysign with an FP16 result.88let isCodeGenOnly = 1 in {89 def CPSDRhh : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP16, FP16, FP16>;90 def CPSDRhs : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP16, FP16, FP32>;91 def CPSDRhd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP16, FP16, FP64>;92}93 94// The sign of an FP128 is in the high register.95let Predicates = [FeatureNoVectorEnhancements1] in96 def : Pat<(fcopysign FP16:$src1, (f128 FP128:$src2)),97 (CPSDRhd FP16:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;98let Predicates = [FeatureVectorEnhancements1] in99 def : Pat<(fcopysign FP16:$src1, (f128 VR128:$src2)),100 (CPSDRhd FP16:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;101 102 103// fcopysign with an FP32 result.104let isCodeGenOnly = 1 in {105 def CPSDRsh : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP16>;106 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>;107 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>;108}109 110// The sign of an FP128 is in the high register.111let Predicates = [FeatureNoVectorEnhancements1] in112 def : Pat<(fcopysign FP32:$src1, (f128 FP128:$src2)),113 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;114let Predicates = [FeatureVectorEnhancements1] in115 def : Pat<(fcopysign FP32:$src1, (f128 VR128:$src2)),116 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;117 118// fcopysign with an FP64 result.119let isCodeGenOnly = 1 in {120 def CPSDRdh : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP16>;121 def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>;122}123def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>;124 125// The sign of an FP128 is in the high register.126let Predicates = [FeatureNoVectorEnhancements1] in127 def : Pat<(fcopysign FP64:$src1, (f128 FP128:$src2)),128 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;129let Predicates = [FeatureVectorEnhancements1] in130 def : Pat<(fcopysign FP64:$src1, (f128 VR128:$src2)),131 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;132 133// fcopysign with an FP128 result. Use "upper" as the high half and leave134// the low half as-is.135class CopySign128<RegisterOperand cls, dag upper>136 : Pat<(fcopysign FP128:$src1, cls:$src2),137 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;138 139let Predicates = [FeatureNoVectorEnhancements1] in {140 def : CopySign128<FP16, (CPSDRdh (EXTRACT_SUBREG FP128:$src1, subreg_h64),141 FP16:$src2)>;142 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),143 FP32:$src2)>;144 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),145 FP64:$src2)>;146 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),147 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;148}149 150// The length is given as one less for MVCImm.151defm LoadStoreF32 : MVCLoadStore<load, f32, MVCImm, 3>;152defm LoadStoreF64 : MVCLoadStore<load, f64, MVCImm, 7>;153defm LoadStoreF128 : MVCLoadStore<load, f128, MVCImm, 15>;154 155//===----------------------------------------------------------------------===//156// Load instructions157//===----------------------------------------------------------------------===//158 159let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {160 let isCodeGenOnly = 1 in161 // Reload f16 from 4-byte spill slot.162 defm LE16 : UnaryRXPair<"le", 0x78, 0xED64, z_load, FP16, 4>;163 defm LE : UnaryRXPair<"le", 0x78, 0xED64, z_load, FP32, 4>;164 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, z_load, FP64, 8>;165 166 // For z13 we prefer LDE over LE to avoid partial register dependencies.167 let isCodeGenOnly = 1 in168 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;169 170 // These instructions are split after register allocation, so we don't171 // want a custom inserter.172 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {173 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),174 [(set FP128:$dst, (load bdxaddr20only128:$src))]>;175 }176}177 178//===----------------------------------------------------------------------===//179// Store instructions180//===----------------------------------------------------------------------===//181 182let SimpleBDXStore = 1, mayStore = 1 in {183 let isCodeGenOnly = 1 in184 // Spill f16 to 4-byte spill slot.185 defm STE16 : StoreRXPair<"ste", 0x70, 0xED66, store, FP16, 4>;186 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;187 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;188 189 // These instructions are split after register allocation, so we don't190 // want a custom inserter.191 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {192 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),193 [(store FP128:$src, bdxaddr20only128:$dst)]>;194 }195}196 197//===----------------------------------------------------------------------===//198// Conversion instructions199//===----------------------------------------------------------------------===//200 201// Convert floating-point values to narrower representations, rounding202// according to the current mode. The destination of LEXBR and LDXBR203// is a 128-bit value, but only the first register of the pair is used.204let Uses = [FPC], mayRaiseFPException = 1 in {205 def LEDBR : UnaryRRE<"ledbr", 0xB344, any_fpround, FP32, FP64>;206 def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>;207 def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>;208 209 def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>,210 Requires<[FeatureFPExtension]>;211 def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>,212 Requires<[FeatureFPExtension]>;213 def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>,214 Requires<[FeatureFPExtension]>;215}216 217let Predicates = [FeatureNoVectorEnhancements1] in {218 def : Pat<(f32 (any_fpround FP128:$src)),219 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_h32)>;220 def : Pat<(f64 (any_fpround FP128:$src)),221 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;222}223 224// Extend register floating-point values to wider representations.225let Uses = [FPC], mayRaiseFPException = 1 in {226 def LDEBR : UnaryRRE<"ldebr", 0xB304, any_fpextend, FP64, FP32>;227 def LXEBR : UnaryRRE<"lxebr", 0xB306, null_frag, FP128, FP32>;228 def LXDBR : UnaryRRE<"lxdbr", 0xB305, null_frag, FP128, FP64>;229}230let Predicates = [FeatureNoVectorEnhancements1] in {231 def : Pat<(f128 (any_fpextend (f32 FP32:$src))), (LXEBR FP32:$src)>;232 def : Pat<(f128 (any_fpextend (f64 FP64:$src))), (LXDBR FP64:$src)>;233}234 235// Extend memory floating-point values to wider representations.236let Uses = [FPC], mayRaiseFPException = 1 in {237 def LDEB : UnaryRXE<"ldeb", 0xED04, z_any_extloadf32, FP64, 4>;238 def LXEB : UnaryRXE<"lxeb", 0xED06, null_frag, FP128, 4>;239 def LXDB : UnaryRXE<"lxdb", 0xED05, null_frag, FP128, 8>;240}241let Predicates = [FeatureNoVectorEnhancements1] in {242 def : Pat<(f128 (z_any_extloadf32 bdxaddr12only:$src)),243 (LXEB bdxaddr12only:$src)>;244 def : Pat<(f128 (z_any_extloadf64 bdxaddr12only:$src)),245 (LXDB bdxaddr12only:$src)>;246}247 248// Convert a signed integer register value to a floating-point one.249let Uses = [FPC], mayRaiseFPException = 1 in {250 def CEFBR : UnaryRRE<"cefbr", 0xB394, any_sint_to_fp, FP32, GR32>;251 def CDFBR : UnaryRRE<"cdfbr", 0xB395, any_sint_to_fp, FP64, GR32>;252 def CXFBR : UnaryRRE<"cxfbr", 0xB396, any_sint_to_fp, FP128, GR32>;253 254 def CEGBR : UnaryRRE<"cegbr", 0xB3A4, any_sint_to_fp, FP32, GR64>;255 def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, any_sint_to_fp, FP64, GR64>;256 def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, any_sint_to_fp, FP128, GR64>;257}258 259// The FP extension feature provides versions of the above that allow260// specifying rounding mode and inexact-exception suppression flags.261let Uses = [FPC], mayRaiseFPException = 1, Predicates = [FeatureFPExtension] in {262 def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>;263 def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>;264 def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>;265 266 def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>;267 def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>;268 def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>;269}270 271// Convert an unsigned integer register value to a floating-point one.272let Predicates = [FeatureFPExtension] in {273 let Uses = [FPC], mayRaiseFPException = 1 in {274 def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>;275 def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>;276 def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>;277 278 def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>;279 def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>;280 def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>;281 }282 283 def : Pat<(f32 (any_uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;284 def : Pat<(f64 (any_uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;285 def : Pat<(f128 (any_uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;286 287 def : Pat<(f32 (any_uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;288 def : Pat<(f64 (any_uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;289 def : Pat<(f128 (any_uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;290}291 292// Convert a floating-point register value to a signed integer value,293// with the second operand (modifier M3) specifying the rounding mode.294let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {295 def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>;296 def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>;297 def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>;298 299 def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>;300 def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>;301 def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>;302}303 304// fp_to_sint always rounds towards zero, which is modifier value 5.305def : Pat<(i32 (any_fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;306def : Pat<(i32 (any_fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;307def : Pat<(i32 (any_fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;308 309def : Pat<(i64 (any_fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;310def : Pat<(i64 (any_fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;311def : Pat<(i64 (any_fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;312 313// The FP extension feature provides versions of the above that allow314// also specifying the inexact-exception suppression flag.315let Uses = [FPC], mayRaiseFPException = 1,316 Predicates = [FeatureFPExtension], Defs = [CC] in {317 def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>;318 def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>;319 def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>;320 321 def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>;322 def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>;323 def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>;324}325 326// Convert a floating-point register value to an unsigned integer value.327let Predicates = [FeatureFPExtension] in {328 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {329 def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>;330 def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>;331 def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>;332 333 def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>;334 def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>;335 def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>;336 }337 338 def : Pat<(i32 (any_fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>;339 def : Pat<(i32 (any_fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>;340 def : Pat<(i32 (any_fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;341 342 def : Pat<(i64 (any_fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>;343 def : Pat<(i64 (any_fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>;344 def : Pat<(i64 (any_fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;345}346 347 348//===----------------------------------------------------------------------===//349// Unary arithmetic350//===----------------------------------------------------------------------===//351 352// We prefer generic instructions during isel, because they do not353// clobber CC and therefore give the scheduler more freedom. In cases354// the CC is actually useful, the SystemZElimCompare pass will try to355// convert generic instructions into opcodes that also set CC. Note356// that lcdf / lpdf / lndf only affect the sign bit, and can therefore357// be used with fp32 as well. This could be done for fp128, in which358// case the operands would have to be tied.359 360// Negation (Load Complement).361let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {362 def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>;363 def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>;364 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>;365}366// Generic form, which does not set CC.367def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>;368let isCodeGenOnly = 1 in {369 def LCDFR_16 : UnaryRRE<"lcdfr", 0xB373, fneg, FP16, FP16>;370 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>;371}372 373// Absolute value (Load Positive).374let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {375 def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>;376 def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>;377 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>;378}379// Generic form, which does not set CC.380def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>;381let isCodeGenOnly = 1 in {382 def LPDFR_16 : UnaryRRE<"lpdfr", 0xB370, fabs, FP16, FP16>;383 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>;384}385 386// Negative absolute value (Load Negative).387let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {388 def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>;389 def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>;390 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>;391}392// Generic form, which does not set CC.393def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>;394let isCodeGenOnly = 1 in {395 def LNDFR_16 : UnaryRRE<"lndfr", 0xB371, fnabs, FP16, FP16>;396 def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>;397}398 399// Square root.400let Uses = [FPC], mayRaiseFPException = 1 in {401 def SQEBR : UnaryRRE<"sqebr", 0xB314, any_fsqrt, FP32, FP32>;402 def SQDBR : UnaryRRE<"sqdbr", 0xB315, any_fsqrt, FP64, FP64>;403 def SQXBR : UnaryRRE<"sqxbr", 0xB316, any_fsqrt, FP128, FP128>;404 405 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<any_fsqrt>, FP32, 4>;406 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<any_fsqrt>, FP64, 8>;407}408 409// Round to an integer, with the second operand (modifier M3) specifying410// the rounding mode. These forms always check for inexact conditions.411let Uses = [FPC], mayRaiseFPException = 1 in {412 def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>;413 def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>;414 def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>;415}416 417// frint rounds according to the current mode (modifier 0) and detects418// inexact conditions.419def : Pat<(any_frint FP32:$src), (FIEBR 0, FP32:$src)>;420def : Pat<(any_frint FP64:$src), (FIDBR 0, FP64:$src)>;421def : Pat<(any_frint FP128:$src), (FIXBR 0, FP128:$src)>;422 423let Predicates = [FeatureFPExtension] in {424 // Extended forms of the FIxBR instructions. M4 can be set to 4425 // to suppress detection of inexact conditions.426 let Uses = [FPC], mayRaiseFPException = 1 in {427 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>;428 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>;429 def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>;430 }431 432 // fnearbyint is like frint but does not detect inexact conditions.433 def : Pat<(any_fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>;434 def : Pat<(any_fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>;435 def : Pat<(any_fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;436 437 // floor is no longer allowed to raise an inexact condition,438 // so restrict it to the cases where the condition can be suppressed.439 // Mode 7 is round towards -inf.440 def : Pat<(any_ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>;441 def : Pat<(any_ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>;442 def : Pat<(any_ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;443 444 // Same idea for ceil, where mode 6 is round towards +inf.445 def : Pat<(any_fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>;446 def : Pat<(any_fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>;447 def : Pat<(any_fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;448 449 // Same idea for trunc, where mode 5 is round towards zero.450 def : Pat<(any_ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>;451 def : Pat<(any_ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>;452 def : Pat<(any_ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;453 454 // Same idea for roundeven, where mode 4 is round towards nearest455 // with ties to even.456 def : Pat<(any_froundeven FP32:$src), (FIEBRA 4, FP32:$src, 4)>;457 def : Pat<(any_froundeven FP64:$src), (FIDBRA 4, FP64:$src, 4)>;458 def : Pat<(any_froundeven FP128:$src), (FIXBRA 4, FP128:$src, 4)>;459 460 // Same idea for round, where mode 1 is round towards nearest with461 // ties away from zero.462 def : Pat<(any_fround FP32:$src), (FIEBRA 1, FP32:$src, 4)>;463 def : Pat<(any_fround FP64:$src), (FIDBRA 1, FP64:$src, 4)>;464 def : Pat<(any_fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>;465}466 467//===----------------------------------------------------------------------===//468// Binary arithmetic469//===----------------------------------------------------------------------===//470 471// Addition.472let Uses = [FPC], mayRaiseFPException = 1,473 Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {474 let isCommutable = 1 in {475 def AEBR : BinaryRRE<"aebr", 0xB30A, any_fadd, FP32, FP32>;476 def ADBR : BinaryRRE<"adbr", 0xB31A, any_fadd, FP64, FP64>;477 def AXBR : BinaryRRE<"axbr", 0xB34A, any_fadd, FP128, FP128>;478 }479 defm AEB : BinaryRXEAndPseudo<"aeb", 0xED0A, z_any_fadd_noreassoc, FP32,480 z_load, 4>;481 defm ADB : BinaryRXEAndPseudo<"adb", 0xED1A, z_any_fadd_noreassoc, FP64,482 z_load, 8>;483}484 485// Subtraction.486let Uses = [FPC], mayRaiseFPException = 1,487 Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {488 def SEBR : BinaryRRE<"sebr", 0xB30B, any_fsub, FP32, FP32>;489 def SDBR : BinaryRRE<"sdbr", 0xB31B, any_fsub, FP64, FP64>;490 def SXBR : BinaryRRE<"sxbr", 0xB34B, any_fsub, FP128, FP128>;491 492 defm SEB : BinaryRXEAndPseudo<"seb", 0xED0B, z_any_fsub_noreassoc, FP32,493 z_load, 4>;494 defm SDB : BinaryRXEAndPseudo<"sdb", 0xED1B, z_any_fsub_noreassoc, FP64,495 z_load, 8>;496}497 498// Multiplication.499let Uses = [FPC], mayRaiseFPException = 1 in {500 let isCommutable = 1 in {501 def MEEBR : BinaryRRE<"meebr", 0xB317, any_fmul, FP32, FP32>;502 def MDBR : BinaryRRE<"mdbr", 0xB31C, any_fmul, FP64, FP64>;503 def MXBR : BinaryRRE<"mxbr", 0xB34C, any_fmul, FP128, FP128>;504 }505 defm MEEB : BinaryRXEAndPseudo<"meeb", 0xED17, z_any_fmul_noreassoc, FP32,506 z_load, 4>;507 defm MDB : BinaryRXEAndPseudo<"mdb", 0xED1C, z_any_fmul_noreassoc, FP64,508 z_load, 8>;509}510 511// f64 multiplication of two FP32 registers.512let Uses = [FPC], mayRaiseFPException = 1 in513 def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>;514def : Pat<(any_fmul (f64 (any_fpextend FP32:$src1)),515 (f64 (any_fpextend FP32:$src2))),516 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),517 FP32:$src1, subreg_h32), FP32:$src2)>;518 519// f64 multiplication of an FP32 register and an f32 memory.520let Uses = [FPC], mayRaiseFPException = 1 in521 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, z_load, 4>;522def : Pat<(any_fmul (f64 (any_fpextend FP32:$src1)),523 (f64 (any_extloadf32 bdxaddr12only:$addr))),524 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32),525 bdxaddr12only:$addr)>;526 527// f128 multiplication of two FP64 registers.528let Uses = [FPC], mayRaiseFPException = 1 in529 def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>;530let Predicates = [FeatureNoVectorEnhancements1] in531 def : Pat<(any_fmul (f128 (any_fpextend FP64:$src1)),532 (f128 (any_fpextend FP64:$src2))),533 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),534 FP64:$src1, subreg_h64), FP64:$src2)>;535 536// f128 multiplication of an FP64 register and an f64 memory.537let Uses = [FPC], mayRaiseFPException = 1 in538 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, z_load, 8>;539let Predicates = [FeatureNoVectorEnhancements1] in540 def : Pat<(any_fmul (f128 (any_fpextend FP64:$src1)),541 (f128 (any_extloadf64 bdxaddr12only:$addr))),542 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),543 bdxaddr12only:$addr)>;544 545// Fused multiply-add.546let Uses = [FPC], mayRaiseFPException = 1 in {547 def MAEBR : TernaryRRD<"maebr", 0xB30E, z_any_fma, FP32, FP32>;548 def MADBR : TernaryRRD<"madbr", 0xB31E, z_any_fma, FP64, FP64>;549 550 defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma, FP32, FP32, z_load, 4>;551 defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma, FP64, FP64, z_load, 8>;552}553 554// Fused multiply-subtract.555let Uses = [FPC], mayRaiseFPException = 1 in {556 def MSEBR : TernaryRRD<"msebr", 0xB30F, z_any_fms, FP32, FP32>;557 def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_any_fms, FP64, FP64>;558 559 defm MSEB : TernaryRXFAndPseudo<"mseb", 0xED0F, z_any_fms, FP32, FP32, z_load, 4>;560 defm MSDB : TernaryRXFAndPseudo<"msdb", 0xED1F, z_any_fms, FP64, FP64, z_load, 8>;561}562 563// Division.564let Uses = [FPC], mayRaiseFPException = 1 in {565 def DEBR : BinaryRRE<"debr", 0xB30D, any_fdiv, FP32, FP32>;566 def DDBR : BinaryRRE<"ddbr", 0xB31D, any_fdiv, FP64, FP64>;567 def DXBR : BinaryRRE<"dxbr", 0xB34D, any_fdiv, FP128, FP128>;568 569 defm DEB : BinaryRXEAndPseudo<"deb", 0xED0D, any_fdiv, FP32, z_load, 4>;570 defm DDB : BinaryRXEAndPseudo<"ddb", 0xED1D, any_fdiv, FP64, z_load, 8>;571}572 573// Divide to integer.574let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {575 def DIEBR : TernaryRRFb<"diebr", 0xB353, FP32, FP32, FP32>;576 def DIDBR : TernaryRRFb<"didbr", 0xB35B, FP64, FP64, FP64>;577}578 579//===----------------------------------------------------------------------===//580// Comparisons581//===----------------------------------------------------------------------===//582 583let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC], CCValues = 0xF in {584 def CEBR : CompareRRE<"cebr", 0xB309, z_any_fcmp, FP32, FP32>;585 def CDBR : CompareRRE<"cdbr", 0xB319, z_any_fcmp, FP64, FP64>;586 def CXBR : CompareRRE<"cxbr", 0xB349, z_any_fcmp, FP128, FP128>;587 588 def CEB : CompareRXE<"ceb", 0xED09, z_any_fcmp, FP32, z_load, 4>;589 def CDB : CompareRXE<"cdb", 0xED19, z_any_fcmp, FP64, z_load, 8>;590 591 def KEBR : CompareRRE<"kebr", 0xB308, z_strict_fcmps, FP32, FP32>;592 def KDBR : CompareRRE<"kdbr", 0xB318, z_strict_fcmps, FP64, FP64>;593 def KXBR : CompareRRE<"kxbr", 0xB348, z_strict_fcmps, FP128, FP128>;594 595 def KEB : CompareRXE<"keb", 0xED08, z_strict_fcmps, FP32, z_load, 4>;596 def KDB : CompareRXE<"kdb", 0xED18, z_strict_fcmps, FP64, z_load, 8>;597}598 599// Test Data Class.600let Defs = [CC], CCValues = 0xC in {601 def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>;602 def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>;603 def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>;604}605 606//===----------------------------------------------------------------------===//607// Floating-point control register instructions608//===----------------------------------------------------------------------===//609 610let hasSideEffects = 1 in {611 let mayLoad = 1, mayStore = 1 in {612 // TODO: EFPC and SFPC do not touch memory at all613 let Uses = [FPC] in {614 def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>;615 def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>;616 }617 618 let Defs = [FPC] in {619 def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>;620 def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>;621 }622 }623 624 let Defs = [FPC], mayRaiseFPException = 1 in {625 def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>;626 def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>;627 }628 629 let Uses = [FPC], Defs = [FPC] in {630 def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>,631 Requires<[FeatureFPExtension]>;632 def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>;633 def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>;634 }635}636 637//===----------------------------------------------------------------------===//638// Peepholes639//===----------------------------------------------------------------------===//640 641def : Pat<(f16 fpimmneg0), (LCDFR_16 (LZER_16))>;642def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>;643def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>;644def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;645