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1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">;10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">;11 12//===----------------------------------------------------------------------===//13// Stack allocation14//===----------------------------------------------------------------------===//15 16// These pseudos carry values needed to compute the MaxcallFrameSize of the17// function. The callseq_start node requires the hasSideEffects flag.18let usesCustomInserter = 1, hasNoSchedulingInfo = 1, hasSideEffects = 1 in {19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),20 [(callseq_start timm:$amt1, timm:$amt2)]>;21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),22 [(callseq_end timm:$amt1, timm:$amt2)]>;23}24 25// Takes as input the value of the stack pointer after a dynamic allocation26// has been made. Sets the output to the address of the dynamically-27// allocated area itself, skipping the outgoing arguments.28//29// This expands to an LA or LAY instruction. We restrict the offset30// to the range of LA and keep the LAY range in reserve for when31// the size of the outgoing arguments is added.32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),33 [(set GR64:$dst, dynalloc12only:$src)]>;34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,36 usesCustomInserter = 1 in37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst),38 (ins GR64:$oldSP, GR64:$space),39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>;40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,42 hasSideEffects = 1 in43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>;44 45let Defs = [R3D, CC], Uses = [R3D, R4D], hasNoSchedulingInfo = 1,46 hasSideEffects = 1 in47 def XPLINK_STACKALLOC : Pseudo<(outs), (ins), []>;48 49//===----------------------------------------------------------------------===//50// Branch instructions51//===----------------------------------------------------------------------===//52 53// Conditional branches.54let isBranch = 1, isTerminator = 1, Uses = [CC] in {55 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form56 // with the condition-code mask being the first operand. It seems friendlier57 // to use mnemonic forms like JE and JLH when writing out the assembly though.58 let isCodeGenOnly = 1 in {59 // An assembler extended mnemonic for BRC.60 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>;61 // An assembler extended mnemonic for BRCL. (The extension is "G"62 // rather than "L" because "JL" is "Jump if Less".)63 def BRCL : CondBranchRIL<"jg#", 0xC04>;64 let isIndirectBranch = 1 in {65 def BC : CondBranchRX<"b#", 0x47>;66 def BCR : CondBranchRR<"b#r", 0x07>;67 def BIC : CondBranchRXY<"bi#", 0xe347>,68 Requires<[FeatureMiscellaneousExtensions2]>;69 }70 }71 72 // Allow using the raw forms directly from the assembler (and occasional73 // special code generation needs) as well.74 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>;75 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>;76 let isIndirectBranch = 1 in {77 def BCAsm : AsmCondBranchRX<"bc", 0x47>;78 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>;79 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>,80 Requires<[FeatureMiscellaneousExtensions2]>;81 }82 83 // Define AsmParser extended mnemonics for each general condition-code mask84 // (integer or floating-point)85 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",86 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {87 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>;88 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>;89 let isIndirectBranch = 1 in {90 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>;91 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>;92 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>,93 Requires<[FeatureMiscellaneousExtensions2]>;94 }95 }96}97 98// Unconditional branches. These are in fact simply variants of the99// conditional branches with the condition mask set to "always".100let isBranch = 1, isTerminator = 1, isBarrier = 1 in {101 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>;102 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>;103 let isIndirectBranch = 1 in {104 def B : FixedCondBranchRX<CondAlways, "b", 0x47>;105 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>;106 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>,107 Requires<[FeatureMiscellaneousExtensions2]>;108 }109}110 111// NOPs. These are again variants of the conditional branches, with the112// condition mask set to "never".113defm NOP : NeverCondBranchRX<"nop", 0x47>;114defm NOPR : NeverCondBranchRR<"nopr", 0x07>;115def JNOP : NeverCondBranchRI<"jnop", 0xA74>;116def JGNOP : NeverCondBranchRIL<"j{g|l}nop", 0xC04>;117 118// Fused compare-and-branch instructions.119//120// These instructions do not use or clobber the condition codes.121// We nevertheless pretend that the relative compare-and-branch122// instructions clobber CC, so that we can lower them to separate123// comparisons and BRCLs if the branch ends up being out of range.124let isBranch = 1, isTerminator = 1 in {125 // As for normal branches, we handle these instructions internally in126 // their raw CRJ-like form, but use assembly macros like CRJE when writing127 // them out. Using the *Pair multiclasses, we also create the raw forms.128 let Defs = [CC] in {129 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>;130 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>;131 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>;132 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>;133 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>;134 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>;135 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>;136 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>;137 }138 let isIndirectBranch = 1 in {139 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>;140 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>;141 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>;142 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>;143 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>;144 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>;145 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>;146 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>;147 }148 149 // Define AsmParser mnemonics for each integer condition-code mask.150 foreach V = [ "E", "H", "L", "HE", "LE", "LH",151 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in {152 let Defs = [CC] in {153 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>;154 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>;155 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32,156 imm32sx8>;157 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64,158 imm64sx8>;159 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>;160 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>;161 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32,162 imm32zx8>;163 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64,164 imm64zx8>;165 }166 let isIndirectBranch = 1 in {167 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>;168 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>;169 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32,170 imm32sx8>;171 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64,172 imm64sx8>;173 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>;174 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>;175 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32,176 imm32zx8>;177 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64,178 imm64zx8>;179 }180 }181}182 183// Decrement a register and branch if it is nonzero. These don't clobber CC,184// but we might need to split long relative branches into sequences that do.185let isBranch = 1, isTerminator = 1 in {186 let Defs = [CC] in {187 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>;188 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;189 }190 // This doesn't need to clobber CC since we never need to split it.191 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>,192 Requires<[FeatureHighWord]>;193 194 def BCT : BranchUnaryRX<"bct", 0x46,GR32>;195 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>;196 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>;197 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>;198}199 200let isBranch = 1, isTerminator = 1 in {201 let Defs = [CC] in {202 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>;203 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>;204 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>;205 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>;206 }207 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>;208 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>;209 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>;210 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>;211}212 213//===----------------------------------------------------------------------===//214// Trap instructions215//===----------------------------------------------------------------------===//216 217// Unconditional trap.218let hasCtrlDep = 1, hasSideEffects = 1 in219 def Trap : Alias<4, (outs), (ins), [(trap)]>;220 221// Conditional trap.222let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in223 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>;224 225// Fused compare-and-trap instructions.226let hasCtrlDep = 1, hasSideEffects = 1 in {227 // These patterns work the same way as for compare-and-branch.228 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>;229 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>;230 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>;231 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>;232 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>;233 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>;234 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>;235 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>;236 let Predicates = [FeatureMiscellaneousExtensions] in {237 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>;238 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>;239 }240 241 foreach V = [ "E", "H", "L", "HE", "LE", "LH",242 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in {243 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>;244 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>;245 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>;246 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>;247 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32,248 imm32sx16>;249 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64,250 imm64sx16>;251 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32,252 imm32zx16>;253 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64,254 imm64zx16>;255 let Predicates = [FeatureMiscellaneousExtensions] in {256 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>;257 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>;258 }259 }260}261 262//===----------------------------------------------------------------------===//263// Call and return instructions264//===----------------------------------------------------------------------===//265 266// Define the general form of the call instructions for the asm parser.267// These instructions don't hard-code %r14 as the return address register.268let isCall = 1, Defs = [CC] in {269 def BRAS : CallRI <"bras", 0xA75>;270 def BRASL : CallRIL<"brasl", 0xC05>;271 def BAS : CallRX <"bas", 0x4D>;272 def BASR : CallRR <"basr", 0x0D>;273}274 275// A symbol in the ADA (z/OS only).276def adasym : Operand<i64>;277 278// z/OS XPLINK279let Predicates = [IsTargetXPLINK64] in {280 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in {281 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops),282 [(z_call pcrel32:$I2)]>;283 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops),284 [(z_call ADDR64:$R2)]>;285 }286 287 let isCall = 1, Defs = [R3D, CC], Uses = [FPC] in {288 def CallBASR_STACKEXT : Alias<4, (outs), (ins ADDR64:$R2), []>;289 }290 291 let hasNoSchedulingInfo = 1, Defs = [CC] in {292 def ADA_ENTRY : Alias<12, (outs ADDR64:$Reg), (ins adasym:$addr,293 ADDR64:$ADA, imm64:$Offset),294 [(set i64:$Reg, (z_ada_entry i64:$addr,295 i64:$ADA, i64:$Offset))]>;296 }297 let mayLoad = 1, AddedComplexity = 20, hasNoSchedulingInfo = 1, Defs = [CC] in {298 def ADA_ENTRY_VALUE : Alias<12, (outs ADDR64:$Reg), (ins adasym:$addr,299 ADDR64:$ADA, imm64:$Offset),300 [(set i64:$Reg, (z_load (z_ada_entry301 iPTR:$addr, iPTR:$ADA, i64:$Offset)))]>;302 }303}304 305// Regular calls.306// z/Linux ELF307let Predicates = [IsTargetELF] in {308 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in {309 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),310 [(z_call pcrel32:$I2)]>;311 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),312 [(z_call ADDR64:$R2)]>;313 }314 315 // TLS calls. These will be lowered into a call to __tls_get_offset,316 // with an extra relocation specifying the TLS symbol.317 let isCall = 1, Defs = [R14D, CC] in {318 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),319 [(z_tls_gdcall tglobaltlsaddr:$I2)]>;320 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),321 [(z_tls_ldcall tglobaltlsaddr:$I2)]>;322 }323}324 325// Sibling calls. Indirect sibling calls must be via R6 for XPLink,326// R1 used for ELF327let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {328 def CallJG : Alias<6, (outs), (ins pcrel32:$I2),329 [(z_sibcall pcrel32:$I2)]>;330 def CallBR : Alias<2, (outs), (ins ADDR64:$R2),331 [(z_sibcall ADDR64:$R2)]>;332}333 334// Conditional sibling calls.335let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {336 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,337 pcrel32:$I2), []>;338 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1,339 ADDR64:$R2), []>;340}341 342// Fused compare and conditional sibling calls.343let isCall = 1, isTerminator = 1, isReturn = 1 in {344 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;345 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;346 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>;347 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>;348 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;349 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;350 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>;351 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>;352}353 354let Predicates = [IsTargetXPLINK64] in {355 // A return instruction (b 2(%r7)).356 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in357 def Return_XPLINK : Alias<4, (outs), (ins), [(z_retglue)]>;358 359 // A conditional return instruction (bc <cond>, 2(%r7)).360 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in361 def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>;362}363 364let Predicates = [IsTargetELF] in {365 // A return instruction (br %r14).366 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in367 def Return : Alias<2, (outs), (ins), [(z_retglue)]>;368 369 // A conditional return instruction (bcr <cond>, %r14).370 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in371 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;372}373 374// Fused compare and conditional returns.375let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in {376 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;377 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;378 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;379 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;380 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;381 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;382 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;383 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;384}385 386//===----------------------------------------------------------------------===//387// Select instructions388//===----------------------------------------------------------------------===//389 390def Select32 : SelectWrapper<i32, GR32>,391 Requires<[FeatureNoLoadStoreOnCond]>;392def Select64 : SelectWrapper<i64, GR64>,393 Requires<[FeatureNoLoadStoreOnCond]>;394 395// We don't define 32-bit Mux stores if we don't have STOCFH, because the396// low-only STOC should then always be used if possible.397defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8,398 nonvolatile_anyextloadi8, bdxaddr20only>,399 Requires<[FeatureHighWord]>;400defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,401 nonvolatile_anyextloadi16, bdxaddr20only>,402 Requires<[FeatureHighWord]>;403defm CondStore32Mux : CondStores<GRX32, simple_store,404 simple_load, bdxaddr20only>,405 Requires<[FeatureLoadStoreOnCond2]>;406defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8,407 nonvolatile_anyextloadi8, bdxaddr20only>;408defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,409 nonvolatile_anyextloadi16, bdxaddr20only>;410defm CondStore32 : CondStores<GR32, simple_store,411 simple_load, bdxaddr20only>;412 413defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,414 nonvolatile_anyextloadi8, bdxaddr20only>;415defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,416 nonvolatile_anyextloadi16, bdxaddr20only>;417defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,418 nonvolatile_anyextloadi32, bdxaddr20only>;419defm CondStore64 : CondStores<GR64, simple_store,420 simple_load, bdxaddr20only>;421 422//===----------------------------------------------------------------------===//423// Move instructions424//===----------------------------------------------------------------------===//425 426// Register moves.427let isMoveReg = 1 in {428 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;429 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;430}431 432let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {433 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>;434 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>;435}436 437let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in438 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>;439 440// Immediate moves.441let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {442 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,443 // deopending on the choice of register.444 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,445 Requires<[FeatureHighWord]>;446 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;447 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;448 449 // Other 16-bit immediates.450 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;451 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;452 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;453 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;454 455 // 32-bit immediates.456 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;457 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;458 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;459}460def LLGFI : InstAlias<"llgfi\t$R1, $RI1", (LLILF GR64:$R1, imm64lf32:$RI1)>;461def LLGHI : InstAlias<"llghi\t$R1, $RI1", (LLILL GR64:$R1, imm64ll16:$RI1)>;462 463// Register loads.464let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {465 // Expands to L, LY or LFH, depending on the choice of register.466 def LMux : UnaryRXYPseudo<"l", z_load, GRX32, 4>,467 Requires<[FeatureHighWord]>;468 defm L : UnaryRXPair<"l", 0x58, 0xE358, z_load, GR32, 4>;469 def LFH : UnaryRXY<"lfh", 0xE3CA, z_load, GRH32, 4>,470 Requires<[FeatureHighWord]>;471 def LG : UnaryRXY<"lg", 0xE304, z_load, GR64, 8>;472 473 // These instructions are split after register allocation, so we don't474 // want a custom inserter.475 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {476 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),477 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;478 }479}480let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {481 def LT : UnaryRXY<"lt", 0xE312, z_load, GR32, 4>;482 def LTG : UnaryRXY<"ltg", 0xE302, z_load, GR64, 8>;483}484 485let canFoldAsLoad = 1 in {486 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_z_load, GR32>;487 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_z_load, GR64>;488}489 490// Load and zero rightmost byte.491let Predicates = [FeatureLoadAndZeroRightmostByte] in {492 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>;493 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>;494 def : Pat<(and (i32 (z_load bdxaddr20only:$src)), 0xffffff00),495 (LZRF bdxaddr20only:$src)>;496 def : Pat<(and (i64 (z_load bdxaddr20only:$src)), 0xffffffffffffff00),497 (LZRG bdxaddr20only:$src)>;498}499 500// Load and trap.501let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {502 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>;503 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>;504 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>;505}506 507// Register stores.508let SimpleBDXStore = 1, mayStore = 1 in {509 // Expands to ST, STY or STFH, depending on the choice of register.510 def STMux : StoreRXYPseudo<store, GRX32, 4>,511 Requires<[FeatureHighWord]>;512 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;513 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,514 Requires<[FeatureHighWord]>;515 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;516 517 // These instructions are split after register allocation, so we don't518 // want a custom inserter.519 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {520 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),521 [(store GR128:$src, bdxaddr20only128:$dst)]>;522 }523}524def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;525def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;526 527// 8-bit immediate stores to 8-bit fields.528defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;529 530// 16-bit immediate stores to 16-, 32- or 64-bit fields.531def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;532def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;533def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;534 535// Memory-to-memory moves.536let mayLoad = 1, mayStore = 1 in537 defm MVC : MemorySS<"mvc", 0xD2, z_mvc>;538let mayLoad = 1, mayStore = 1, Defs = [CC] in {539 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>;540 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>;541 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>;542}543 544// Memset[Length][Byte] pseudos.545def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>;546def MemsetImmReg : MemsetPseudo<imm64, GR32>;547def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>;548def MemsetRegReg : MemsetPseudo<ADDR64, GR32>;549 550// Move right.551let Predicates = [FeatureMiscellaneousExtensions3],552 mayLoad = 1, mayStore = 1, Uses = [R0L] in553 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>;554 555// String moves.556let mayLoad = 1, mayStore = 1, Defs = [CC] in557 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;558 559//===----------------------------------------------------------------------===//560// Conditional move instructions561//===----------------------------------------------------------------------===//562 563let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in {564 // Select.565 let isCommutable = 1 in {566 // Expands to SELR or SELFHR or a branch-and-move sequence,567 // depending on the choice of registers.568 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>;569 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>;570 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>;571 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>;572 }573 574 // Define AsmParser extended mnemonics for each general condition-code mask.575 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",576 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {577 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0,578 GR32, GR32, GR32>;579 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0,580 GRH32, GRH32, GRH32>;581 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3,582 GR64, GR64, GR64>;583 }584}585 586let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {587 // Load immediate on condition. Matched via DAG pattern and created588 // by the PeepholeOptimizer via FoldImmediate.589 590 // Expands to LOCHI or LOCHHI, depending on the choice of register.591 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>;592 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>;593 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>;594 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>;595 596 // Move register on condition. Matched via DAG pattern and597 // created by early if-conversion.598 let isCommutable = 1 in {599 // Expands to LOCR or LOCFHR or a branch-and-move sequence,600 // depending on the choice of registers.601 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>;602 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>;603 }604 605 // Load on condition. Matched via DAG pattern.606 // Expands to LOC or LOCFH, depending on the choice of register.607 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>;608 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>;609 610 // Store on condition. Expanded from CondStore* pseudos.611 // Expands to STOC or STOCFH, depending on the choice of register.612 def STOCMux : CondStoreRSYPseudo<GRX32, 4>;613 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>;614 615 // Define AsmParser extended mnemonics for each general condition-code mask.616 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",617 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {618 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32,619 imm32sx16>;620 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64,621 imm64sx16>;622 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32,623 imm32sx16>;624 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>;625 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>;626 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>;627 }628}629 630let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in {631 // Move register on condition. Matched via DAG pattern and632 // created by early if-conversion.633 let isCommutable = 1 in {634 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>;635 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>;636 }637 638 // Load on condition. Matched via DAG pattern.639 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>;640 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>;641 642 // Store on condition. Expanded from CondStore* pseudos.643 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>;644 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>;645 646 // Define AsmParser extended mnemonics for each general condition-code mask.647 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",648 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {649 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>;650 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>;651 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>;652 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>;653 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>;654 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>;655 }656}657//===----------------------------------------------------------------------===//658// Sign extensions659//===----------------------------------------------------------------------===//660//661// Note that putting these before zero extensions mean that we will prefer662// them for anyextload*. There's not really much to choose between the two663// either way, but signed-extending loads have a short LH and a long LHY,664// while zero-extending loads have only the long LLH.665//666//===----------------------------------------------------------------------===//667 668// 32-bit extensions from registers.669def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;670def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;671 672// 64-bit extensions from registers.673def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;674def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;675def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;676 677let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in678 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>;679 680// Match 32-to-64-bit sign extensions in which the source is already681// in a 64-bit register.682def : Pat<(sext_inreg GR64:$src, i32),683 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;684 685// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,686// depending on the choice of register.687def LBMux : UnaryRXYPseudo<"lb", z_asextloadi8, GRX32, 1>,688 Requires<[FeatureHighWord]>;689def LB : UnaryRXY<"lb", 0xE376, z_asextloadi8, GR32, 1>;690def LBH : UnaryRXY<"lbh", 0xE3C0, z_asextloadi8, GRH32, 1>,691 Requires<[FeatureHighWord]>;692 693// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,694// depending on the choice of register.695def LHMux : UnaryRXYPseudo<"lh", z_asextloadi16, GRX32, 2>,696 Requires<[FeatureHighWord]>;697defm LH : UnaryRXPair<"lh", 0x48, 0xE378, z_asextloadi16, GR32, 2>;698def LHH : UnaryRXY<"lhh", 0xE3C4, z_asextloadi16, GRH32, 2>,699 Requires<[FeatureHighWord]>;700def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_z_asextloadi16, GR32>;701 702// 64-bit extensions from memory.703def LGB : UnaryRXY<"lgb", 0xE377, z_asextloadi8, GR64, 1>;704def LGH : UnaryRXY<"lgh", 0xE315, z_asextloadi16, GR64, 2>;705def LGF : UnaryRXY<"lgf", 0xE314, z_asextloadi32, GR64, 4>;706def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_z_asextloadi16, GR64>;707def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_z_asextloadi32, GR64>;708let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in709 def LTGF : UnaryRXY<"ltgf", 0xE332, z_asextloadi32, GR64, 4>;710 711//===----------------------------------------------------------------------===//712// Zero extensions713//===----------------------------------------------------------------------===//714 715// 32-bit extensions from registers.716 717// Expands to LLCR or RISB[LH]G, depending on the choice of registers.718def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>,719 Requires<[FeatureHighWord]>;720def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;721// Expands to LLHR or RISB[LH]G, depending on the choice of registers.722def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>,723 Requires<[FeatureHighWord]>;724def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;725 726// 64-bit extensions from registers.727def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;728def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;729def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;730 731// Match 32-to-64-bit zero extensions in which the source is already732// in a 64-bit register.733def : Pat<(and GR64:$src, 0xffffffff),734 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;735 736// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,737// depending on the choice of register.738def LLCMux : UnaryRXYPseudo<"llc", z_azextloadi8, GRX32, 1>,739 Requires<[FeatureHighWord]>;740def LLC : UnaryRXY<"llc", 0xE394, z_azextloadi8, GR32, 1>;741def LLCH : UnaryRXY<"llch", 0xE3C2, z_azextloadi8, GRH32, 1>,742 Requires<[FeatureHighWord]>;743 744// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,745// depending on the choice of register.746def LLHMux : UnaryRXYPseudo<"llh", z_azextloadi16, GRX32, 2>,747 Requires<[FeatureHighWord]>;748def LLH : UnaryRXY<"llh", 0xE395, z_azextloadi16, GR32, 2>;749def LLHH : UnaryRXY<"llhh", 0xE3C6, z_azextloadi16, GRH32, 2>,750 Requires<[FeatureHighWord]>;751def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_z_azextloadi16, GR32>;752 753// 64-bit extensions from memory.754def LLGC : UnaryRXY<"llgc", 0xE390, z_azextloadi8, GR64, 1>;755def LLGH : UnaryRXY<"llgh", 0xE391, z_azextloadi16, GR64, 2>;756def LLGF : UnaryRXY<"llgf", 0xE316, z_azextloadi32, GR64, 4>;757def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_z_azextloadi16, GR64>;758def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_z_azextloadi32, GR64>;759 760// 31-to-64-bit zero extensions.761def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>;762def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>;763def : Pat<(and GR64:$src, 0x7fffffff),764 (LLGTR GR64:$src)>;765def : Pat<(and (i64 (z_azextloadi32 bdxaddr20only:$src)), 0x7fffffff),766 (LLGT bdxaddr20only:$src)>;767 768// Load and zero rightmost byte.769let Predicates = [FeatureLoadAndZeroRightmostByte] in {770 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>;771 def : Pat<(and (i64 (z_azextloadi32 bdxaddr20only:$src)), 0xffffff00),772 (LLZRGF bdxaddr20only:$src)>;773}774 775// Load and trap.776let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {777 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>;778 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;779}780 781// Extend GR64s to GR128s.782let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in783 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;784 785//===----------------------------------------------------------------------===//786// "Any" extensions787//===----------------------------------------------------------------------===//788 789// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.790def : Pat<(i64 (anyext GR32:$src)),791 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;792 793// Extend GR64s to GR128s.794let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in795 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;796 797//===----------------------------------------------------------------------===//798// Truncations799//===----------------------------------------------------------------------===//800 801// Truncations of 64-bit registers to 32-bit registers.802def : Pat<(i32 (trunc GR64:$src)),803 (EXTRACT_SUBREG GR64:$src, subreg_l32)>;804 805// Truncations of 32-bit registers to 8-bit memory. STCMux expands to806// STC, STCY or STCH, depending on the choice of register.807def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,808 Requires<[FeatureHighWord]>;809defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;810def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,811 Requires<[FeatureHighWord]>;812 813// Truncations of 32-bit registers to 16-bit memory. STHMux expands to814// STH, STHY or STHH, depending on the choice of register.815def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,816 Requires<[FeatureHighWord]>;817defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;818def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,819 Requires<[FeatureHighWord]>;820def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;821 822// Truncations of 64-bit registers to memory.823defm : StoreGR64Pair<STC, STCY, truncstorei8>;824defm : StoreGR64Pair<STH, STHY, truncstorei16>;825def : StoreGR64PC<STHRL, aligned_truncstorei16>;826defm : StoreGR64Pair<ST, STY, truncstorei32>;827def : StoreGR64PC<STRL, aligned_truncstorei32>;828 829// Store characters under mask -- not (yet) used for codegen.830defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>;831def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>;832 833//===----------------------------------------------------------------------===//834// Multi-register moves835//===----------------------------------------------------------------------===//836 837// Multi-register loads.838defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>;839def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;840def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>;841def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>;842 843// Multi-register stores.844defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>;845def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;846def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>;847 848//===----------------------------------------------------------------------===//849// Byte swaps850//===----------------------------------------------------------------------===//851 852// Byte-swapping register moves.853def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;854def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;855 856// Byte-swapping loads.857def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>;858def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>;859def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>;860 861// Byte-swapping stores.862def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>;863def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>;864def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>;865 866// Byte-swapping memory-to-memory moves.867let mayLoad = 1, mayStore = 1 in868 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>;869 870//===----------------------------------------------------------------------===//871// Load address instructions872//===----------------------------------------------------------------------===//873 874// Load BDX-style addresses.875let isAsCheapAsAMove = 1, isReMaterializable = 1 in876 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>;877 878// Load a PC-relative address. There's no version of this instruction879// with a 16-bit offset, so there's no relaxation.880let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in881 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>;882 883// Load the Global Offset Table address. This will be lowered into a884// larl $R1, _GLOBAL_OFFSET_TABLE_885// instruction.886def GOT : Alias<6, (outs GR64:$R1), (ins),887 [(set GR64:$R1, (global_offset_table))]>;888 889// Load (logical) indexed address.890let Predicates = [FeatureMiscellaneousExtensions4] in {891 defm LXAB : LoadIndexedAddressRXY<"lxab", 0xE360, sext32>;892 defm LXAH : LoadIndexedAddressRXY<"lxah", 0xE362, sext32, shl1>;893 defm LXAF : LoadIndexedAddressRXY<"lxaf", 0xE364, sext32, shl2>;894 defm LXAG : LoadIndexedAddressRXY<"lxag", 0xE366, sext32, shl3>;895 defm LXAQ : LoadIndexedAddressRXY<"lxaq", 0xE368, sext32, shl4>;896 defm LLXAB : LoadIndexedAddressRXY<"llxab", 0xE361, zext32>;897 defm LLXAH : LoadIndexedAddressRXY<"llxah", 0xE363, zext32, shl1>;898 defm LLXAF : LoadIndexedAddressRXY<"llxaf", 0xE365, zext32, shl2>;899 defm LLXAG : LoadIndexedAddressRXY<"llxag", 0xE367, zext32, shl3>;900 defm LLXAQ : LoadIndexedAddressRXY<"llxaq", 0xE369, zext32, shl4>;901 902 // Peepholes to use load (logical) indexed address to implement903 // add + shift of an already extended value.904 def : Pat<(add ADDR64:$base, (shl1 (assertsext32 ADDR64:$index))),905 (LXAH ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;906 def : Pat<(add ADDR64:$base, (shl2 (assertsext32 ADDR64:$index))),907 (LXAF ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;908 def : Pat<(add ADDR64:$base, (shl3 (assertsext32 ADDR64:$index))),909 (LXAG ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;910 def : Pat<(add ADDR64:$base, (shl4 (assertsext32 ADDR64:$index))),911 (LXAQ ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;912 def : Pat<(add ADDR64:$base, (shl1 (assertzext32 ADDR64:$index))),913 (LLXAH ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;914 def : Pat<(add ADDR64:$base, (shl2 (assertzext32 ADDR64:$index))),915 (LLXAF ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;916 def : Pat<(add ADDR64:$base, (shl3 (assertzext32 ADDR64:$index))),917 (LLXAG ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;918 def : Pat<(add ADDR64:$base, (shl4 (assertzext32 ADDR64:$index))),919 (LLXAQ ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>;920}921 922//===----------------------------------------------------------------------===//923// Absolute and Negation924//===----------------------------------------------------------------------===//925 926let Defs = [CC] in {927 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {928 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>;929 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>;930 }931 let CCValues = 0xE, CompareZeroCCMask = 0xE in932 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>;933}934defm : SXU<abs, LPGFR>;935 936let Defs = [CC] in {937 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {938 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>;939 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>;940 }941 let CCValues = 0xE, CompareZeroCCMask = 0xE in942 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>;943}944defm : SXU<z_inegabs, LNGFR>;945 946let Defs = [CC] in {947 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {948 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;949 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;950 }951 let CCValues = 0xE, CompareZeroCCMask = 0xE in952 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;953}954defm : SXU<ineg, LCGFR>;955 956//===----------------------------------------------------------------------===//957// Insertion958//===----------------------------------------------------------------------===//959 960let isCodeGenOnly = 1 in961 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, z_azextloadi8, 1>;962defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, z_azextloadi8, 1>;963 964defm : InsertMem<"inserti8", IC32, GR32, z_azextloadi8, bdxaddr12pair>;965defm : InsertMem<"inserti8", IC32Y, GR32, z_azextloadi8, bdxaddr20pair>;966 967defm : InsertMem<"inserti8", IC, GR64, z_azextloadi8, bdxaddr12pair>;968defm : InsertMem<"inserti8", ICY, GR64, z_azextloadi8, bdxaddr20pair>;969 970// Insert characters under mask -- not (yet) used for codegen.971let Defs = [CC] in {972 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>;973 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>;974}975 976// Insertions of a 16-bit immediate, leaving other bits unaffected.977// We don't have or_as_insert equivalents of these operations because978// OI is available instead.979//980// IIxMux expands to II[LH]x, depending on the choice of register.981def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,982 Requires<[FeatureHighWord]>;983def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,984 Requires<[FeatureHighWord]>;985def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;986def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;987def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;988def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;989def IILL64 : BinaryAliasRI<insertll64, GR64, imm64ll16>;990def IILH64 : BinaryAliasRI<insertlh64, GR64, imm64lh16>;991def IIHL64 : BinaryAliasRI<inserthl64, GR64, imm64hl16>;992def IIHH64 : BinaryAliasRI<inserthh64, GR64, imm64hh16>;993 994// ...likewise for 32-bit immediates. For GR32s this is a general995// full-width move. (We use IILF rather than something like LLILF996// for 32-bit moves because IILF leaves the upper 32 bits of the997// GR64 unchanged.)998let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {999 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,1000 Requires<[FeatureHighWord]>;1001 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;1002 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;1003}1004def LFI : InstAlias<"lfi\t$R1, $RI1", (IILF GR32:$R1, uimm32:$RI1)>;1005def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;1006def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;1007 1008// An alternative model of inserthf, with the first operand being1009// a zero-extended value.1010def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),1011 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),1012 imm64hf32:$imm)>;1013 1014//===----------------------------------------------------------------------===//1015// Addition1016//===----------------------------------------------------------------------===//1017 1018// Addition producing a signed overflow flag.1019let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in {1020 // Addition of a register.1021 let isCommutable = 1 in {1022 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>;1023 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>;1024 }1025 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;1026 1027 // Addition to a high register.1028 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>,1029 Requires<[FeatureHighWord]>;1030 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>,1031 Requires<[FeatureHighWord]>;1032 1033 // Addition of signed 16-bit immediates.1034 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>;1035 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>;1036 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>;1037 1038 // Addition of signed 32-bit immediates.1039 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>,1040 Requires<[FeatureHighWord]>;1041 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>;1042 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>,1043 Requires<[FeatureHighWord]>;1044 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>;1045 1046 // Addition of memory.1047 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, z_asextloadi16, 2>;1048 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, z_load, 4>;1049 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, z_asextloadi16, 2>,1050 Requires<[FeatureMiscellaneousExtensions2]>;1051 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, z_asextloadi32, 4>;1052 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, z_load, 8>;1053 1054 // Addition to memory.1055 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;1056 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;1057}1058defm : SXB<z_sadd, GR64, AGFR>;1059 1060// Addition producing a carry.1061let Defs = [CC], CCValues = 0xF, IsLogical = 1 in {1062 // Addition of a register.1063 let isCommutable = 1 in {1064 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>;1065 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>;1066 }1067 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;1068 1069 // Addition to a high register.1070 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>,1071 Requires<[FeatureHighWord]>;1072 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>,1073 Requires<[FeatureHighWord]>;1074 1075 // Addition of signed 16-bit immediates.1076 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>,1077 Requires<[FeatureDistinctOps]>;1078 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>,1079 Requires<[FeatureDistinctOps]>;1080 1081 // Addition of unsigned 32-bit immediates.1082 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>;1083 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>;1084 1085 // Addition of signed 32-bit immediates.1086 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>,1087 Requires<[FeatureHighWord]>;1088 1089 // Addition of memory.1090 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, z_load, 4>;1091 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, z_azextloadi32, 4>;1092 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, z_load, 8>;1093 1094 // Addition to memory.1095 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>;1096 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>;1097}1098defm : ZXB<z_uadd, GR64, ALGFR>;1099 1100// Addition producing and using a carry.1101let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in {1102 // Addition of a register.1103 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>;1104 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>;1105 1106 // Addition of memory.1107 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, z_load, 4>;1108 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, z_load, 8>;1109}1110 1111// Addition that does not modify the condition code.1112def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>,1113 Requires<[FeatureHighWord]>;1114 1115 1116//===----------------------------------------------------------------------===//1117// Subtraction1118//===----------------------------------------------------------------------===//1119 1120// Subtraction producing a signed overflow flag.1121let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8,1122 CCIfNoSignedWrap = 1 in {1123 // Subtraction of a register.1124 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>;1125 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;1126 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>;1127 1128 // Subtraction from a high register.1129 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>,1130 Requires<[FeatureHighWord]>;1131 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>,1132 Requires<[FeatureHighWord]>;1133 1134 // Subtraction of memory.1135 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, z_asextloadi16, 2>;1136 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, z_load, 4>;1137 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, z_asextloadi16, 2>,1138 Requires<[FeatureMiscellaneousExtensions2]>;1139 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, z_asextloadi32, 4>;1140 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, z_load, 8>;1141}1142defm : SXB<z_ssub, GR64, SGFR>;1143 1144// Subtracting an immediate is the same as adding the negated immediate.1145let AddedComplexity = 1 in {1146 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2),1147 (AHIMux GR32:$src1, imm32sx16n:$src2)>,1148 Requires<[FeatureHighWord]>;1149 def : Pat<(z_ssub GR32:$src1, simm32n:$src2),1150 (AFIMux GR32:$src1, simm32n:$src2)>,1151 Requires<[FeatureHighWord]>;1152 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2),1153 (AHI GR32:$src1, imm32sx16n:$src2)>;1154 def : Pat<(z_ssub GR32:$src1, simm32n:$src2),1155 (AFI GR32:$src1, simm32n:$src2)>;1156 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2),1157 (AGHI GR64:$src1, imm64sx16n:$src2)>;1158 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2),1159 (AGFI GR64:$src1, imm64sx32n:$src2)>;1160}1161 1162// And vice versa in one special case, where we need to load a1163// constant into a register in any case, but the negated constant1164// requires fewer instructions to load.1165def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2),1166 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>;1167def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2),1168 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>;1169 1170// Subtraction producing a carry.1171let Defs = [CC], CCValues = 0x7, IsLogical = 1 in {1172 // Subtraction of a register.1173 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>;1174 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;1175 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>;1176 1177 // Subtraction from a high register.1178 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>,1179 Requires<[FeatureHighWord]>;1180 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>,1181 Requires<[FeatureHighWord]>;1182 1183 // Subtraction of unsigned 32-bit immediates.1184 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>;1185 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>;1186 1187 // Subtraction of memory.1188 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, z_load, 4>;1189 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, z_azextloadi32, 4>;1190 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, z_load, 8>;1191}1192defm : ZXB<z_usub, GR64, SLGFR>;1193 1194// Subtracting an immediate is the same as adding the negated immediate.1195let AddedComplexity = 1 in {1196 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2),1197 (ALHSIK GR32:$src1, imm32sx16n:$src2)>,1198 Requires<[FeatureDistinctOps]>;1199 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2),1200 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>,1201 Requires<[FeatureDistinctOps]>;1202}1203 1204// And vice versa in one special case (but we prefer addition).1205def : Pat<(add GR64:$src1, imm64zx32n:$src2),1206 (SLGFI GR64:$src1, imm64zx32n:$src2)>;1207 1208// Subtraction producing and using a carry.1209let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in {1210 // Subtraction of a register.1211 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>;1212 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>;1213 1214 // Subtraction of memory.1215 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, z_load, 4>;1216 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, z_load, 8>;1217}1218 1219 1220//===----------------------------------------------------------------------===//1221// AND1222//===----------------------------------------------------------------------===//1223 1224let Defs = [CC] in {1225 // ANDs of a register.1226 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {1227 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>;1228 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>;1229 }1230 1231 let isConvertibleToThreeAddress = 1 in {1232 // ANDs of a 16-bit immediate, leaving other bits unaffected.1233 // The CC result only reflects the 16-bit field, not the full register.1234 //1235 // NIxMux expands to NI[LH]x, depending on the choice of register.1236 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,1237 Requires<[FeatureHighWord]>;1238 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,1239 Requires<[FeatureHighWord]>;1240 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;1241 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;1242 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;1243 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;1244 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;1245 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;1246 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;1247 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;1248 1249 // ANDs of a 32-bit immediate, leaving other bits unaffected.1250 // The CC result only reflects the 32-bit field, which means we can1251 // use it as a zero indicator for i32 operations but not otherwise.1252 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1253 // Expands to NILF or NIHF, depending on the choice of register.1254 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,1255 Requires<[FeatureHighWord]>;1256 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;1257 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;1258 }1259 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;1260 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;1261 }1262 1263 // ANDs of memory.1264 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1265 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, z_load, 4>;1266 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, z_load, 8>;1267 }1268 1269 // AND to memory1270 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>;1271 1272 // Block AND.1273 let mayLoad = 1, mayStore = 1 in1274 defm NC : MemorySS<"nc", 0xD4, z_nc>;1275}1276defm : RMWIByte<and, bdaddr12pair, NI>;1277defm : RMWIByte<and, bdaddr20pair, NIY>;1278 1279//===----------------------------------------------------------------------===//1280// OR1281//===----------------------------------------------------------------------===//1282 1283let Defs = [CC] in {1284 // ORs of a register.1285 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {1286 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>;1287 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>;1288 }1289 1290 // ORs of a 16-bit immediate, leaving other bits unaffected.1291 // The CC result only reflects the 16-bit field, not the full register.1292 //1293 // OIxMux expands to OI[LH]x, depending on the choice of register.1294 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,1295 Requires<[FeatureHighWord]>;1296 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,1297 Requires<[FeatureHighWord]>;1298 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;1299 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;1300 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;1301 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;1302 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;1303 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;1304 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;1305 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;1306 1307 // ORs of a 32-bit immediate, leaving other bits unaffected.1308 // The CC result only reflects the 32-bit field, which means we can1309 // use it as a zero indicator for i32 operations but not otherwise.1310 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1311 // Expands to OILF or OIHF, depending on the choice of register.1312 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,1313 Requires<[FeatureHighWord]>;1314 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;1315 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;1316 }1317 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;1318 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;1319 1320 // ORs of memory.1321 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1322 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, z_load, 4>;1323 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, z_load, 8>;1324 }1325 1326 // OR to memory1327 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>;1328 1329 // Block OR.1330 let mayLoad = 1, mayStore = 1 in1331 defm OC : MemorySS<"oc", 0xD6, z_oc>;1332}1333defm : RMWIByte<or, bdaddr12pair, OI>;1334defm : RMWIByte<or, bdaddr20pair, OIY>;1335 1336//===----------------------------------------------------------------------===//1337// XOR1338//===----------------------------------------------------------------------===//1339 1340let Defs = [CC] in {1341 // XORs of a register.1342 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {1343 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>;1344 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>;1345 }1346 1347 // XORs of a 32-bit immediate, leaving other bits unaffected.1348 // The CC result only reflects the 32-bit field, which means we can1349 // use it as a zero indicator for i32 operations but not otherwise.1350 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1351 // Expands to XILF or XIHF, depending on the choice of register.1352 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,1353 Requires<[FeatureHighWord]>;1354 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;1355 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;1356 }1357 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;1358 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;1359 1360 // XORs of memory.1361 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1362 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, z_load, 4>;1363 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, z_load, 8>;1364 }1365 1366 // XOR to memory1367 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>;1368 1369 // Block XOR.1370 let mayLoad = 1, mayStore = 1 in1371 defm XC : MemorySS<"xc", 0xD7, z_xc>;1372}1373defm : RMWIByte<xor, bdaddr12pair, XI>;1374defm : RMWIByte<xor, bdaddr20pair, XIY>;1375 1376//===----------------------------------------------------------------------===//1377// Combined logical operations1378//===----------------------------------------------------------------------===//1379 1380let Predicates = [FeatureMiscellaneousExtensions3],1381 Defs = [CC] in {1382 // AND with complement.1383 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1384 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>;1385 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>;1386 }1387 1388 // OR with complement.1389 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {1390 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>;1391 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>;1392 }1393 1394 // NAND.1395 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {1396 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>;1397 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>;1398 }1399 1400 // NOR.1401 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {1402 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>;1403 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>;1404 let isAsmParserOnly = 1 in {1405 def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>;1406 def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>;1407 }1408 }1409 1410 // NXOR.1411 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {1412 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>;1413 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>;1414 }1415}1416 1417//===----------------------------------------------------------------------===//1418// Multiplication1419//===----------------------------------------------------------------------===//1420 1421// Multiplication of a register, setting the condition code. We prefer these1422// over MS(G)R if available, even though we cannot use the condition code,1423// since they are three-operand instructions.1424let Predicates = [FeatureMiscellaneousExtensions2],1425 Defs = [CC], isCommutable = 1 in {1426 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>;1427 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>;1428}1429 1430// Multiplication of a register.1431let isCommutable = 1 in {1432 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;1433 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>;1434}1435def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>;1436defm : SXB<mul, GR64, MSGFR>;1437 1438// Multiplication of a signed 16-bit immediate.1439def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;1440def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;1441 1442// Multiplication of a signed 32-bit immediate.1443def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;1444def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;1445 1446// Multiplication of memory.1447defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, z_asextloadi16, 2>;1448defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, z_load, 4>;1449def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, z_asextloadi16, 2>,1450 Requires<[FeatureMiscellaneousExtensions2]>;1451def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, z_asextloadi32, 4>;1452def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, z_load, 8>;1453 1454// Multiplication of memory, setting the condition code.1455let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in {1456 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, z_load, 4>;1457 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, z_load, 8>;1458}1459 1460// Multiplication of a register, producing two results.1461def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>;1462def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>,1463 Requires<[FeatureMiscellaneousExtensions2]>;1464def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>;1465def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>;1466 1467def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2),1468 (MGRK GR64:$src1, GR64:$src2)>;1469def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2),1470 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>;1471 1472// Multiplication of memory, producing two results.1473def M : BinaryRX <"m", 0x5C, null_frag, GR128, z_load, 4>;1474def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, z_load, 4>;1475def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, z_load, 8>,1476 Requires<[FeatureMiscellaneousExtensions2]>;1477def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, z_load, 4>;1478def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, z_load, 8>;1479 1480def : Pat<(z_smul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),1481 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;1482def : Pat<(z_umul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),1483 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;1484 1485//===----------------------------------------------------------------------===//1486// Division and remainder1487//===----------------------------------------------------------------------===//1488 1489let hasSideEffects = 1 in { // Do not speculatively execute.1490 // Division and remainder, from registers.1491 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>;1492 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>;1493 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>;1494 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>;1495 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>;1496 1497 // Division and remainder, from memory.1498 def D : BinaryRX <"d", 0x5D, null_frag, GR128, z_load, 4>;1499 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, z_load, 4>;1500 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, z_load, 8>;1501 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, z_load, 4>;1502 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, z_load, 8>;1503}1504def : Pat<(z_sdivrem GR64:$src1, GR32:$src2),1505 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>;1506def : Pat<(z_sdivrem GR64:$src1, (i32 (z_load bdxaddr20only:$src2))),1507 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;1508def : Pat<(z_sdivrem GR64:$src1, GR64:$src2),1509 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>;1510def : Pat<(z_sdivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),1511 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;1512 1513def : Pat<(z_udivrem GR32:$src1, GR32:$src2),1514 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,1515 subreg_l32)), GR32:$src2)>;1516def : Pat<(z_udivrem GR32:$src1, (i32 (z_load bdxaddr20only:$src2))),1517 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,1518 subreg_l32)), bdxaddr20only:$src2)>;1519def : Pat<(z_udivrem GR64:$src1, GR64:$src2),1520 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>;1521def : Pat<(z_udivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),1522 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>;1523 1524//===----------------------------------------------------------------------===//1525// Shifts1526//===----------------------------------------------------------------------===//1527 1528// Logical shift left.1529defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>;1530def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>;1531def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>;1532 1533// Arithmetic shift left.1534let Defs = [CC] in {1535 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>;1536 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>;1537 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>;1538}1539 1540// Logical shift right.1541defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>;1542def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>;1543def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>;1544 1545// Arithmetic shift right.1546let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {1547 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>;1548 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>;1549 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>;1550}1551 1552// Rotate left.1553def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>;1554def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;1555 1556// Rotate second operand left and inserted selected bits into first operand.1557// These can act like 32-bit operands provided that the constant start and1558// end bits (operands 2 and 3) are in the range [32, 64).1559let Defs = [CC] in {1560 let isCodeGenOnly = 1 in1561 defm RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;1562 let CCValues = 0xE, CompareZeroCCMask = 0xE in {1563 defm RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;1564 defm RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>;1565 }1566}1567 1568// On zEC12 we have a variant of RISBG that does not set CC.1569let Predicates = [FeatureMiscellaneousExtensions] in {1570 defm RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;1571 defm RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>;1572}1573 1574// Forms of RISBG that only affect one word of the destination register.1575// They do not set CC.1576let Predicates = [FeatureHighWord] in {1577 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;1578 defm RISBLL : RotateSelectAliasRIEf<GR32, GR32>;1579 defm RISBLH : RotateSelectAliasRIEf<GR32, GRH32>;1580 defm RISBHL : RotateSelectAliasRIEf<GRH32, GR32>;1581 defm RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>;1582 defm RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;1583 defm RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;1584}1585 1586// Rotate second operand left and perform a logical operation with selected1587// bits of the first operand. The CC result only describes the selected bits,1588// so isn't useful for a full comparison against zero.1589let Defs = [CC] in {1590 defm RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;1591 defm ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;1592 defm RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;1593}1594 1595//===----------------------------------------------------------------------===//1596// Comparison1597//===----------------------------------------------------------------------===//1598 1599// Signed comparisons. We put these before the unsigned comparisons because1600// some of the signed forms have COMPARE AND BRANCH equivalents whereas none1601// of the unsigned forms do.1602let Defs = [CC], CCValues = 0xE in {1603 // Comparison with a register.1604 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>;1605 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;1606 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>;1607 1608 // Comparison with a high register.1609 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>,1610 Requires<[FeatureHighWord]>;1611 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>,1612 Requires<[FeatureHighWord]>;1613 1614 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH,1615 // depending on the choice of register.1616 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>,1617 Requires<[FeatureHighWord]>;1618 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>;1619 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;1620 1621 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH,1622 // depending on the choice of register.1623 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,1624 Requires<[FeatureHighWord]>;1625 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>;1626 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>,1627 Requires<[FeatureHighWord]>;1628 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;1629 1630 // Comparison with memory.1631 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, z_asextloadi16, 2>;1632 def CMux : CompareRXYPseudo<z_scmp, GRX32, z_load, 4>,1633 Requires<[FeatureHighWord]>;1634 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, z_load, 4>;1635 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, z_load, 4>,1636 Requires<[FeatureHighWord]>;1637 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, z_asextloadi16, 2>;1638 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, z_asextloadi32, 4>;1639 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, z_load, 8>;1640 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_z_asextloadi16>;1641 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_z_load>;1642 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_z_asextloadi16>;1643 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_z_asextloadi32>;1644 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_z_load>;1645 1646 // Comparison between memory and a signed 16-bit immediate.1647 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, z_asextloadi16, imm32sx16>;1648 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, z_load, imm32sx16>;1649 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, z_load, imm64sx16>;1650}1651defm : SXB<z_scmp, GR64, CGFR>;1652 1653// Unsigned comparisons.1654let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {1655 // Comparison with a register.1656 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;1657 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;1658 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>;1659 1660 // Comparison with a high register.1661 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>,1662 Requires<[FeatureHighWord]>;1663 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>,1664 Requires<[FeatureHighWord]>;1665 1666 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI1667 // or CLIH, depending on the choice of register.1668 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,1669 Requires<[FeatureHighWord]>;1670 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;1671 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>,1672 Requires<[FeatureHighWord]>;1673 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;1674 1675 // Comparison with memory.1676 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, z_load, 4>,1677 Requires<[FeatureHighWord]>;1678 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, z_load, 4>;1679 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, z_load, 4>,1680 Requires<[FeatureHighWord]>;1681 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, z_azextloadi32, 4>;1682 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, z_load, 8>;1683 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,1684 aligned_z_azextloadi16>;1685 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,1686 aligned_z_load>;1687 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,1688 aligned_z_azextloadi16>;1689 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,1690 aligned_z_azextloadi32>;1691 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,1692 aligned_z_load>;1693 1694 // Comparison between memory and an unsigned 8-bit immediate.1695 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, z_azextloadi8, imm32zx8>;1696 1697 // Comparison between memory and an unsigned 16-bit immediate.1698 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, z_azextloadi16, imm32zx16>;1699 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, z_load, imm32zx16>;1700 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, z_load, imm64zx16>;1701}1702defm : ZXB<z_ucmp, GR64, CLGFR>;1703 1704// Memory-to-memory comparison.1705let mayLoad = 1, Defs = [CC] in {1706 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>;1707 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>;1708 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>;1709 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>;1710}1711 1712// String comparison.1713let mayLoad = 1, Defs = [CC] in1714 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;1715 1716// Test under mask.1717let Defs = [CC] in {1718 // TMxMux expands to TM[LH]x, depending on the choice of register.1719 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,1720 Requires<[FeatureHighWord]>;1721 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,1722 Requires<[FeatureHighWord]>;1723 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;1724 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;1725 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;1726 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;1727 1728 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;1729 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;1730 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;1731 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;1732 1733 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, z_anyextloadi8, imm32zx8>;1734}1735 1736def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>;1737def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>;1738 1739// Compare logical characters under mask -- not (yet) used for codegen.1740let Defs = [CC] in {1741 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>;1742 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>;1743}1744 1745//===----------------------------------------------------------------------===//1746// Prefetch and execution hint1747//===----------------------------------------------------------------------===//1748 1749let mayLoad = 1, mayStore = 1 in {1750 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;1751 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;1752}1753 1754let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in {1755 // Branch Prediction Preload1756 def BPP : BranchPreloadSMI<"bpp", 0xC7>;1757 def BPRP : BranchPreloadMII<"bprp", 0xC5>;1758 1759 // Next Instruction Access Intent1760 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>;1761}1762 1763//===----------------------------------------------------------------------===//1764// Atomic operations1765//===----------------------------------------------------------------------===//1766 1767// A serialization instruction that acts as a barrier for all memory1768// accesses, which expands to "bcr 14, 0".1769let hasSideEffects = 1 in1770def Serialize : Alias<2, (outs), (ins), []>;1771 1772let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {1773 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_i32, GR32>;1774 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_i64, GR64>;1775 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>;1776 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;1777 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_i32, GR32>;1778 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_i64, GR64>;1779 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_i32, GR32>;1780 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_i64, GR64>;1781 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_i32, GR32>;1782 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_i64, GR64>;1783}1784 1785def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;1786 1787def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;1788def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;1789 1790def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;1791 1792def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;1793def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;1794 1795def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;1796def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;1797 1798def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;1799def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;1800 1801def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;1802def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,1803 imm32lh16c>;1804 1805def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;1806def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;1807def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;1808def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;1809 1810def ATOMIC_CMP_SWAPW1811 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,1812 ADDR32:$bitshift, ADDR32:$negbitshift,1813 uimm32:$bitsize),1814 [(set GR32:$dst,1815 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,1816 ADDR32:$bitshift, ADDR32:$negbitshift,1817 uimm32:$bitsize))]> {1818 let Defs = [CC];1819 let mayLoad = 1;1820 let mayStore = 1;1821 let usesCustomInserter = 1;1822 let hasNoSchedulingInfo = 1;1823}1824 1825// Test and set.1826let mayLoad = 1, Defs = [CC] in1827 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>;1828 1829// Compare and swap.1830let Defs = [CC] in {1831 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>;1832 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>;1833}1834 1835// Compare double and swap.1836let Defs = [CC] in {1837 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>;1838 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>;1839}1840 1841// Compare and swap and store.1842let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in1843 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>;1844 1845// Perform locked operation.1846let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in1847 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>;1848 1849// Load/store pair from/to quadword.1850def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>;1851def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>;1852 1853// Load pair disjoint.1854let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {1855 def LPD : BinarySSF<"lpd", 0xC84, GR128>;1856 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>;1857}1858 1859// Compare and load.1860let Predicates = [FeatureConcurrentFunctions], Defs = [CC] in {1861 def CAL : BinarySSF<"cal", 0xC86, GR32>;1862 def CALGF : BinarySSF<"calgf", 0xC8F, GR64>;1863 def CALG : BinarySSF<"calg", 0xC87, GR64>;1864}1865 1866// Perform function with concurrent results.1867let Predicates = [FeatureConcurrentFunctions], Uses = [R0D], Defs = [CC],1868 mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {1869 def PFCR : BinaryRSY<"pfcr", 0xEB16, null_frag, GR64>;1870}1871 1872//===----------------------------------------------------------------------===//1873// Translate and convert1874//===----------------------------------------------------------------------===//1875 1876let mayLoad = 1, mayStore = 1 in1877 def TR : SideEffectBinarySSa<"tr", 0xDC>;1878 1879let mayLoad = 1, Defs = [CC, R0L, R1D] in {1880 def TRT : SideEffectBinarySSa<"trt", 0xDD>;1881 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>;1882}1883 1884let mayLoad = 1, mayStore = 1, Uses = [R0L] in1885 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>;1886 1887let mayLoad = 1, Uses = [R1D], Defs = [CC] in {1888 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>;1889 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>;1890}1891 1892let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in {1893 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>;1894 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>;1895 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>;1896 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>;1897}1898 1899let mayLoad = 1, mayStore = 1, Defs = [CC] in {1900 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>;1901 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>;1902 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>;1903 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>;1904 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>;1905 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>;1906 1907 let isAsmParserOnly = 1 in {1908 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>;1909 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>;1910 }1911}1912 1913//--------------------------------------------------------------------------1914// Setjmp/Longjmp.1915//--------------------------------------------------------------------------1916let isBarrier = 1, hasNoSchedulingInfo = 1 in {1917 let hasSideEffects = 1, usesCustomInserter = 1 in {1918 def EH_SjLj_SetJmp : Pseudo<(outs GR32:$dst), (ins ADDR64:$R2), 1919 [(set GR32:$dst, (z_eh_sjlj_setjmp ADDR64:$R2))]>;1920 let isTerminator = 1 in {1921 def EH_SjLj_LongJmp : Pseudo<(outs), (ins ADDR64:$R2), 1922 [(z_eh_sjlj_longjmp ADDR64:$R2)]>;1923 }1924 }1925 let isTerminator = 1, isCodeGenOnly = 1, Size = 0 in {1926 def EH_SjLj_Setup : Pseudo<(outs), (ins brtarget32:$dst), []>;1927 }1928}1929 1930//===----------------------------------------------------------------------===//1931// Message-security assist1932//===----------------------------------------------------------------------===//1933 1934let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in {1935 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>;1936 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>;1937 1938 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>;1939 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>;1940 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>;1941 1942 let Predicates = [FeatureMessageSecurityAssist4] in {1943 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>;1944 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>;1945 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D,1946 GR128, GR128, GR128>;1947 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>;1948 }1949 1950 let Predicates = [FeatureMessageSecurityAssist5] in1951 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>;1952 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in1953 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>;1954 1955 let Predicates = [FeatureMessageSecurityAssist8] in1956 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929,1957 GR128, GR128, GR128>;1958 1959 let Predicates = [FeatureMessageSecurityAssist9] in1960 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>;1961 1962 let Predicates = [FeatureMessageSecurityAssist12] in {1963 def KIMDOpt : SideEffectTernaryMemMemRRFc<"kimd", 0xB93E, GR64, GR128, imm32zx4>;1964 def KLMDOpt : SideEffectTernaryMemMemRRFc<"klmd", 0xB93F, GR64, GR128, imm32zx4>;1965 }1966}1967 1968//===----------------------------------------------------------------------===//1969// Guarded storage1970//===----------------------------------------------------------------------===//1971 1972// These instructions use and/or modify the guarded storage control1973// registers, which we do not otherwise model, so they should have1974// hasSideEffects.1975let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in {1976 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>;1977 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>;1978 1979 let mayLoad = 1 in1980 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>;1981 let mayStore = 1 in1982 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>;1983}1984 1985//===----------------------------------------------------------------------===//1986// Decimal arithmetic1987//===----------------------------------------------------------------------===//1988 1989defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, z_load, 4>;1990def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, z_load, 8>;1991 1992defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>;1993def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>;1994 1995let mayLoad = 1, mayStore = 1 in {1996 def MVN : SideEffectBinarySSa<"mvn", 0xD1>;1997 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>;1998 def MVO : SideEffectBinarySSb<"mvo", 0xF1>;1999 2000 def PACK : SideEffectBinarySSb<"pack", 0xF2>;2001 def PKA : SideEffectBinarySSf<"pka", 0xE9>;2002 def PKU : SideEffectBinarySSf<"pku", 0xE1>;2003 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>;2004 let Defs = [CC] in {2005 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>;2006 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>;2007 }2008}2009 2010let mayLoad = 1, mayStore = 1 in {2011 let Defs = [CC] in {2012 def AP : SideEffectBinarySSb<"ap", 0xFA>;2013 def SP : SideEffectBinarySSb<"sp", 0xFB>;2014 def ZAP : SideEffectBinarySSb<"zap", 0xF8>;2015 def SRP : SideEffectTernarySSc<"srp", 0xF0>;2016 }2017 def MP : SideEffectBinarySSb<"mp", 0xFC>;2018 def DP : SideEffectBinarySSb<"dp", 0xFD>;2019 let Defs = [CC] in {2020 def ED : SideEffectBinarySSa<"ed", 0xDE>;2021 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>;2022 }2023}2024 2025let Defs = [CC] in {2026 def CP : CompareSSb<"cp", 0xF9>;2027 def TP : TestRSL<"tp", 0xEBC0>;2028}2029 2030//===----------------------------------------------------------------------===//2031// Access registers2032//===----------------------------------------------------------------------===//2033 2034// Read a 32-bit access register into a GR32. As with all GR32 operations,2035// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful2036// when a 64-bit address is stored in a pair of access registers.2037def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>;2038 2039// Set access register.2040def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>;2041 2042// Copy access register.2043def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>;2044 2045// Load address extended.2046defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>;2047 2048// Load access multiple.2049defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>;2050 2051// Store access multiple.2052defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>;2053 2054//===----------------------------------------------------------------------===//2055// Program mask and addressing mode2056//===----------------------------------------------------------------------===//2057 2058// Extract CC and program mask into a register. CC ends up in bits 29 and 28.2059let Uses = [CC] in2060 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>;2061 2062// Set CC and program mask from a register.2063let hasSideEffects = 1, Defs = [CC] in2064 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>;2065 2066// Branch and link - like BAS, but also extracts CC and program mask.2067let isCall = 1, Uses = [CC], Defs = [CC] in {2068 def BAL : CallRX<"bal", 0x45>;2069 def BALR : CallRR<"balr", 0x05>;2070}2071 2072// Test addressing mode.2073let Defs = [CC] in2074 def TAM : SideEffectInherentE<"tam", 0x010B>;2075 2076// Set addressing mode.2077let hasSideEffects = 1 in {2078 def SAM24 : SideEffectInherentE<"sam24", 0x010C>;2079 def SAM31 : SideEffectInherentE<"sam31", 0x010D>;2080 def SAM64 : SideEffectInherentE<"sam64", 0x010E>;2081}2082 2083// Branch and set mode. Not really a call, but also sets an output register.2084let isBranch = 1, isTerminator = 1, isBarrier = 1 in2085 def BSM : CallRR<"bsm", 0x0B>;2086 2087// Branch and save and set mode.2088let isCall = 1, Defs = [CC] in2089 def BASSM : CallRR<"bassm", 0x0C>;2090 2091//===----------------------------------------------------------------------===//2092// Transactional execution2093//===----------------------------------------------------------------------===//2094 2095let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in {2096 // Transaction Begin2097 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in {2098 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>;2099 let hasNoSchedulingInfo = 1 in2100 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>;2101 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561,2102 int_s390_tbeginc, imm32zx16>;2103 }2104 2105 // Transaction End2106 let Defs = [CC] in2107 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>;2108 2109 // Transaction Abort2110 let isTerminator = 1, isBarrier = 1, mayStore = 1,2111 hasSideEffects = 1 in2112 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>;2113 2114 // Nontransactional Store2115 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;2116 2117 // Extract Transaction Nesting Depth2118 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>;2119}2120 2121//===----------------------------------------------------------------------===//2122// Processor assist2123//===----------------------------------------------------------------------===//2124 2125let Predicates = [FeatureProcessorAssist] in {2126 let hasSideEffects = 1 in2127 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>;2128 def : Pat<(int_s390_ppa_txassist GR32:$src),2129 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),2130 zero_reg, 1)>;2131}2132 2133//===----------------------------------------------------------------------===//2134// Miscellaneous Instructions.2135//===----------------------------------------------------------------------===//2136 2137// Count leading/trailing zeros.2138let Predicates = [FeatureMiscellaneousExtensions4] in {2139 def CLZG : UnaryRRE<"clzg", 0xB968, ctlz, GR64, GR64>;2140 def CTZG : UnaryRRE<"ctzg", 0xB969, cttz, GR64, GR64>;2141}2142 2143// Find leftmost one, AKA count leading zeros. The instruction actually2144// returns a pair of GR64s, the first giving the number of leading zeros2145// and the second giving a copy of the source with the leftmost one bit2146// cleared. We only use the first result here.2147let Defs = [CC] in2148 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;2149def : Pat<(i64 (ctlz GR64:$src)),2150 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;2151 2152// Population count. Counts bits set per byte or doubleword.2153let Predicates = [FeatureMiscellaneousExtensions3] in {2154 let Defs = [CC] in2155 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>;2156 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>;2157}2158let Predicates = [FeaturePopulationCount], Defs = [CC] in2159 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>;2160 2161// Bit deposit and bit extract.2162let Predicates = [FeatureMiscellaneousExtensions4] in {2163 def BDEPG : BinaryRRFa<"bdepg", 0xB96D, int_s390_bdepg, GR64, GR64, GR64>;2164 def BEXTG : BinaryRRFa<"bextg", 0xB96C, int_s390_bextg, GR64, GR64, GR64>;2165}2166 2167// Search a block of memory for a character.2168let mayLoad = 1, Defs = [CC] in2169 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>;2170let mayLoad = 1, Defs = [CC], Uses = [R0L] in2171 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>;2172 2173// Compare until substring equal.2174let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in2175 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>;2176 2177// Compare and form codeword.2178let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in2179 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>;2180 2181// Update tree.2182let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D],2183 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in2184 def UPT : SideEffectInherentE<"upt", 0x0102>;2185 2186// Checksum.2187let mayLoad = 1, Defs = [CC] in2188 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR32, GR128>;2189 2190// Compression call.2191let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in2192 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>;2193 2194// Sort lists.2195let Predicates = [FeatureEnhancedSort],2196 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in2197 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>;2198 2199// Deflate conversion call.2200let Predicates = [FeatureDeflateConversion],2201 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in2202 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939,2203 GR128, GR128, GR64>;2204 2205// NNPA.2206let Predicates = [FeatureNNPAssist],2207 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in2208 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>;2209 2210// Execute.2211let hasSideEffects = 1 in {2212 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>;2213 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>;2214 let hasNoSchedulingInfo = 1 in2215 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1,2216 bdaddr12only:$bdl1, bdaddr12only:$bd2),2217 []>;2218}2219 2220//===----------------------------------------------------------------------===//2221// .insn directive instructions2222//===----------------------------------------------------------------------===//2223 2224let isCodeGenOnly = 1, hasSideEffects = 1 in {2225 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;2226 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1,2227 imm32sx16:$I2),2228 ".insn ri,$enc,$R1,$I2", []>;2229 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,2230 AnyReg:$R3, brtarget16:$I2),2231 ".insn rie,$enc,$R1,$R3,$I2", []>;2232 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,2233 brtarget32:$I2),2234 ".insn ril,$enc,$R1,$I2", []>;2235 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,2236 uimm32:$I2),2237 ".insn rilu,$enc,$R1,$I2", []>;2238 def InsnRIS : DirectiveInsnRIS<(outs),2239 (ins imm64zx48:$enc, AnyReg:$R1,2240 imm32sx8:$I2, imm32zx4:$M3,2241 (bdaddr12only $B4, $D4):$BD4),2242 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;2243 def InsnRR : DirectiveInsnRR<(outs),2244 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),2245 ".insn rr,$enc,$R1,$R2", []>;2246 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc,2247 AnyReg:$R1, AnyReg:$R2),2248 ".insn rre,$enc,$R1,$R2", []>;2249 def InsnRRF : DirectiveInsnRRF<(outs),2250 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,2251 AnyReg:$R3, imm32zx4:$M4),2252 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;2253 def InsnRRS : DirectiveInsnRRS<(outs),2254 (ins imm64zx48:$enc, AnyReg:$R1,2255 AnyReg:$R2, imm32zx4:$M3,2256 (bdaddr12only $B4, $D4):$BD4),2257 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;2258 def InsnRS : DirectiveInsnRS<(outs),2259 (ins imm64zx32:$enc, AnyReg:$R1,2260 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),2261 ".insn rs,$enc,$R1,$R3,$BD2", []>;2262 def InsnRSE : DirectiveInsnRSE<(outs),2263 (ins imm64zx48:$enc, AnyReg:$R1,2264 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),2265 ".insn rse,$enc,$R1,$R3,$BD2", []>;2266 def InsnRSI : DirectiveInsnRSI<(outs),2267 (ins imm64zx48:$enc, AnyReg:$R1,2268 AnyReg:$R3, brtarget16:$RI2),2269 ".insn rsi,$enc,$R1,$R3,$RI2", []>;2270 def InsnRSY : DirectiveInsnRSY<(outs),2271 (ins imm64zx48:$enc, AnyReg:$R1,2272 AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2),2273 ".insn rsy,$enc,$R1,$R3,$BD2", []>;2274 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1,2275 (bdxaddr12only $B2, $D2, $X2):$XBD2),2276 ".insn rx,$enc,$R1,$XBD2", []>;2277 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,2278 (bdxaddr12only $B2, $D2, $X2):$XBD2),2279 ".insn rxe,$enc,$R1,$XBD2", []>;2280 def InsnRXF : DirectiveInsnRXF<(outs),2281 (ins imm64zx48:$enc, AnyReg:$R1,2282 AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),2283 ".insn rxf,$enc,$R1,$R3,$XBD2", []>;2284 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1,2285 (bdxaddr20only $B2, $D2, $X2):$XBD2),2286 ".insn rxy,$enc,$R1,$XBD2", []>;2287 def InsnS : DirectiveInsnS<(outs),2288 (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),2289 ".insn s,$enc,$BD2", []>;2290 def InsnSI : DirectiveInsnSI<(outs),2291 (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1,2292 imm32sx8:$I2),2293 ".insn si,$enc,$BD1,$I2", []>;2294 def InsnSIY : DirectiveInsnSIY<(outs),2295 (ins imm64zx48:$enc,2296 (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2),2297 ".insn siy,$enc,$BD1,$I2", []>;2298 def InsnSIL : DirectiveInsnSIL<(outs),2299 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,2300 imm32zx16:$I2),2301 ".insn sil,$enc,$BD1,$I2", []>;2302 def InsnSS : DirectiveInsnSS<(outs),2303 (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,2304 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),2305 ".insn ss,$enc,$RBD1,$BD2,$R3", []>;2306 def InsnSSE : DirectiveInsnSSE<(outs),2307 (ins imm64zx48:$enc,2308 (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2),2309 ".insn sse,$enc,$BD1,$BD2", []>;2310 def InsnSSF : DirectiveInsnSSF<(outs),2311 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,2312 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),2313 ".insn ssf,$enc,$BD1,$BD2,$R3", []>;2314 def InsnVRI : DirectiveInsnVRI<(outs),2315 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,2316 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),2317 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;2318 def InsnVRR : DirectiveInsnVRR<(outs),2319 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,2320 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,2321 imm32zx4:$M6),2322 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;2323 def InsnVRS : DirectiveInsnVRS<(outs),2324 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,2325 (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),2326 ".insn vrs,$enc,$BD2,$M4", []>;2327 def InsnVRV : DirectiveInsnVRV<(outs),2328 (ins imm64zx48:$enc, VR128:$V1,2329 (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),2330 ".insn vrv,$enc,$V1,$VBD2,$M3", []>;2331 def InsnVRX : DirectiveInsnVRX<(outs),2332 (ins imm64zx48:$enc, VR128:$V1,2333 (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),2334 ".insn vrx,$enc,$V1,$XBD2,$M3", []>;2335 def InsnVSI : DirectiveInsnVSI<(outs),2336 (ins imm64zx48:$enc, VR128:$V1,2337 (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),2338 ".insn vsi,$enc,$V1,$BD2,$I3", []>;2339}2340 2341//===----------------------------------------------------------------------===//2342// Peepholes.2343//===----------------------------------------------------------------------===//2344 2345// Avoid generating 2 XOR instructions. (xor (and x, y), y) is2346// equivalent to (and (xor x, -1), y)2347def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),2348 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;2349 2350// Use LCGR/AGHI for i64 xor with -1.2351def : Pat<(xor GR64:$x, (i64 -1)),2352 (AGHI (LCGR GR64:$x), (i64 -1))>;2353 2354// Shift/rotate instructions only use the last 6 bits of the second operand2355// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the2356// last 16 bits.2357// Complexity is added so that we match this before we match NILF on the AND2358// operation alone.2359let AddedComplexity = 4 in {2360 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2361 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2362 2363 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2364 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2365 2366 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2367 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2368 2369 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2370 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2371 2372 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2373 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2374 2375 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2376 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2377 2378 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2379 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2380 2381 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),2382 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;2383}2384 2385// Substitute (x*64-s) with (-s), since shift/rotate instructions only2386// use the last 6 bits of the second operand register (making it modulo 64).2387let AddedComplexity = 4 in {2388 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)),2389 (SLLG GR64:$val, (LCR GR32:$shift), 0)>;2390 2391 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)),2392 (SRAG GR64:$val, (LCR GR32:$shift), 0)>;2393 2394 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)),2395 (SRLG GR64:$val, (LCR GR32:$shift), 0)>;2396 2397 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)),2398 (RLLG GR64:$val, (LCR GR32:$shift), 0)>;2399}2400 2401// Peepholes for turning scalar operations into block operations. The length2402// is given as one less for these pseudos.2403defm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>;2404defm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>;2405defm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>;2406defm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>;2407defm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>;2408defm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>;2409defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>;2410 2411//===----------------------------------------------------------------------===//2412// Mnemonic Aliases2413//===----------------------------------------------------------------------===//2414 2415def JCT : MnemonicAlias<"jct", "brct">;2416def JCTG : MnemonicAlias<"jctg", "brctg">;2417def JC : MnemonicAlias<"jc", "brc">;2418def JCTH : MnemonicAlias<"jcth", "brcth">;2419def JAS : MnemonicAlias<"jas", "bras">;2420def JASL : MnemonicAlias<"jasl", "brasl">;2421def JXH : MnemonicAlias<"jxh", "brxh">;2422def JXLE : MnemonicAlias<"jxle", "brxle">;2423def JXHG : MnemonicAlias<"jxhg", "brxhg">;2424def JXLEG : MnemonicAlias<"jxleg", "brxlg">;2425 2426def BRU : MnemonicAlias<"bru", "j">;2427def BRUL : MnemonicAlias<"brul", "jg", "gnu">;2428def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">;2429 2430foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",2431 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {2432 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">;2433 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "gnu">;2434 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">;2435}2436