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1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Move instructions11//===----------------------------------------------------------------------===//12 13let Predicates = [FeatureVector] in {14 // Register move.15 let isMoveReg = 1 in {16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;17 def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>;18 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>;19 }20 21 // Load GR from VR element.22 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>;23 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>;24 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>;25 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>;26 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>;27 28 // Load VR element from GR.29 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>;30 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert,31 v128b, v128b, GR32, 0>;32 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert,33 v128h, v128h, GR32, 1>;34 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert,35 v128f, v128f, GR32, 2>;36 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert,37 v128g, v128g, GR64, 3>;38 39 // Load VR from GRs disjoint.40 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>;41 def VLVGP32 : BinaryAliasVRRf<GR32>;42}43 44// Extractions always assign to the full GR64, even if the element would45// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a46// subreg of the result.47class VectorExtractSubreg<ValueType type, Instruction insn>48 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),49 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;50 51def : VectorExtractSubreg<v16i8, VLGVB>;52def : VectorExtractSubreg<v8i16, VLGVH>;53def : VectorExtractSubreg<v4i32, VLGVF>;54 55//===----------------------------------------------------------------------===//56// Immediate instructions57//===----------------------------------------------------------------------===//58 59let Predicates = [FeatureVector] in {60 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {61 62 // Generate byte mask.63 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;64 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>;65 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16_timm>;66 67 // Generate mask.68 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>;69 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>;70 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>;71 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>;72 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>;73 74 // Replicate immediate.75 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>;76 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16_timm, 0>;77 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16_timm, 1>;78 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16_timm, 2>;79 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16_timm, 3>;80 }81 82 // Load element immediate.83 //84 // We want these instructions to be used ahead of VLVG* where possible.85 // However, VLVG* takes a variable BD-format index whereas VLEI takes86 // a plain immediate index. This means that VLVG* has an extra "base"87 // register operand and is 3 units more complex. Bumping the complexity88 // of the VLEI* instructions by 4 means that they are strictly better89 // than VLVG* in cases where both forms match.90 let AddedComplexity = 4 in {91 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert,92 v128b, v128b, imm32sx16trunc, imm32zx4>;93 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert,94 v128h, v128h, imm32sx16trunc, imm32zx3>;95 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert,96 v128f, v128f, imm32sx16, imm32zx2>;97 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert,98 v128g, v128g, imm64sx16, imm32zx1>;99 }100}101 102//===----------------------------------------------------------------------===//103// Loads104//===----------------------------------------------------------------------===//105 106let Predicates = [FeatureVector] in {107 // Load.108 let SimpleBDXLoad = 1 in109 defm VL : UnaryVRXAlign<"vl", 0xE706>;110 111 // Load to block boundary. The number of loaded bytes is only known112 // at run time. The instruction is really polymorphic, but v128b matches113 // the return type of the associated intrinsic.114 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>;115 116 // Load count to block boundary.117 let Defs = [CC] in118 def LCBB : InstRXE<0xE727, (outs GR32:$R1),119 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),120 "lcbb\t$R1, $XBD2, $M3",121 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2,122 imm32zx4_timm:$M3))]>;123 124 // Load with length. The number of loaded bytes is only known at run time.125 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>;126 127 // Load multiple.128 defm VLM : LoadMultipleVRSaAlign<"vlm", 0xE736>;129 130 // Load and replicate131 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>;132 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>;133 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>;134 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>;135 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>;136 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),137 (VLREPF bdxaddr12only:$addr)>;138 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),139 (VLREPG bdxaddr12only:$addr)>;140 141 // Use VLREP to load subvectors. These patterns use "12pair" because142 // LEY and LDY offer full 20-bit displacement fields. It's often better143 // to use those instructions rather than force a 20-bit displacement144 // into a GPR temporary.145 let mayLoad = 1, SimpleBDXLoad = 1, canFoldAsLoad = 1 in {146 def VL16 : UnaryAliasVRX<z_load, v16hb, bdxaddr12pair>;147 def VL32 : UnaryAliasVRX<z_load, v32sb, bdxaddr12pair>;148 def VL64 : UnaryAliasVRX<z_load, v64db, bdxaddr12pair>;149 }150 151 // Load logical element and zero.152 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>;153 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>;154 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>;155 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>;156 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>;157 def : Pat<(z_vllezf32 bdxaddr12only:$addr),158 (VLLEZF bdxaddr12only:$addr)>;159 def : Pat<(z_vllezf64 bdxaddr12only:$addr),160 (VLLEZG bdxaddr12only:$addr)>;161 let Predicates = [FeatureVectorEnhancements1] in {162 def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>;163 def : Pat<(z_vllezlf32 bdxaddr12only:$addr),164 (VLLEZLF bdxaddr12only:$addr)>;165 }166 167 // Load element.168 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>;169 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>;170 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>;171 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>;172 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),173 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;174 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),175 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;176 177 // Gather element.178 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>;179 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>;180}181 182let Predicates = [FeatureVectorPackedDecimal] in {183 // Load rightmost with length. The number of loaded bytes is only known184 // at run time. Note that while the instruction will accept immediate185 // lengths larger that 15 at runtime, those will always result in a trap,186 // so we never emit them here.187 def VLRL : BinaryVSI<"vlrl", 0xE635, null_frag, 0>;188 def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>;189 def : Pat<(int_s390_vlrl imm32zx4:$len, bdaddr12only:$addr),190 (VLRL bdaddr12only:$addr, imm32zx4:$len)>;191}192 193// Use replicating loads if we're inserting a single element into an194// undefined vector. This avoids a false dependency on the previous195// register contents.196multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype,197 SDPatternOperator load, ValueType scalartype> {198 def : Pat<(vectype (z_vector_insert199 (undef), (scalartype (load bdxaddr12only:$addr)), 0)),200 (vlrep bdxaddr12only:$addr)>;201 def : Pat<(vectype (scalar_to_vector202 (scalartype (load bdxaddr12only:$addr)))),203 (vlrep bdxaddr12only:$addr)>;204}205defm : ReplicatePeephole<VLREPB, v16i8, z_anyextloadi8, i32>;206defm : ReplicatePeephole<VLREPH, v8i16, z_anyextloadi16, i32>;207defm : ReplicatePeephole<VLREPF, v4i32, z_load, i32>;208defm : ReplicatePeephole<VLREPG, v2i64, z_load, i64>;209defm : ReplicatePeephole<VLREPF, v4f32, z_load, f32>;210defm : ReplicatePeephole<VLREPG, v2f64, z_load, f64>;211 212//===----------------------------------------------------------------------===//213// Stores214//===----------------------------------------------------------------------===//215 216let Predicates = [FeatureVector] in {217 // Store.218 let SimpleBDXStore = 1 in219 defm VST : StoreVRXAlign<"vst", 0xE70E>;220 221 // Store with length. The number of stored bytes is only known at run time.222 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>;223 224 // Store multiple.225 defm VSTM : StoreMultipleVRSaAlign<"vstm", 0xE73E>;226 227 // Store element.228 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>;229 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>;230 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>;231 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>;232 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,233 imm32zx2:$index),234 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;235 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,236 imm32zx1:$index),237 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;238 239 // Use VSTE to store subvectors. These patterns use "12pair" because240 // STEY and STDY offer full 20-bit displacement fields. It's often better241 // to use those instructions rather than force a 20-bit displacement242 // into a GPR temporary.243 let mayStore = 1, SimpleBDXStore = 1 in {244 def VST16 : StoreAliasVRX<store, v16hb, bdxaddr12pair>;245 def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>;246 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>;247 }248 249 // Scatter element.250 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>;251 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>;252}253 254let Predicates = [FeatureVectorPackedDecimal] in {255 // Store rightmost with length. The number of stored bytes is only known256 // at run time. Note that while the instruction will accept immediate257 // lengths larger that 15 at runtime, those will always result in a trap,258 // so we never emit them here.259 def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, null_frag, 0>;260 def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>;261 def : Pat<(int_s390_vstrl VR128:$val, imm32zx4:$len, bdaddr12only:$addr),262 (VSTRL VR128:$val, bdaddr12only:$addr, imm32zx4:$len)>;263}264 265//===----------------------------------------------------------------------===//266// Byte swaps267//===----------------------------------------------------------------------===//268 269let Predicates = [FeatureVectorEnhancements2] in {270 // Load byte-reversed elements.271 def VLBR : UnaryVRXGeneric<"vlbr", 0xE606>;272 def VLBRH : UnaryVRX<"vlbrh", 0xE606, z_loadbswap, v128h, 16, 1>;273 def VLBRF : UnaryVRX<"vlbrf", 0xE606, z_loadbswap, v128f, 16, 2>;274 def VLBRG : UnaryVRX<"vlbrg", 0xE606, z_loadbswap, v128g, 16, 3>;275 def VLBRQ : UnaryVRX<"vlbrq", 0xE606, z_loadbswap, v128q, 16, 4>;276 277 // Load elements reversed.278 def VLER : UnaryVRXGeneric<"vler", 0xE607>;279 def VLERH : UnaryVRX<"vlerh", 0xE607, z_loadeswap, v128h, 16, 1>;280 def VLERF : UnaryVRX<"vlerf", 0xE607, z_loadeswap, v128f, 16, 2>;281 def VLERG : UnaryVRX<"vlerg", 0xE607, z_loadeswap, v128g, 16, 3>;282 def : Pat<(v4f32 (z_loadeswap bdxaddr12only:$addr)),283 (VLERF bdxaddr12only:$addr)>;284 def : Pat<(v2f64 (z_loadeswap bdxaddr12only:$addr)),285 (VLERG bdxaddr12only:$addr)>;286 def : Pat<(v16i8 (z_loadeswap bdxaddr12only:$addr)),287 (VLBRQ bdxaddr12only:$addr)>;288 289 // Load byte-reversed element.290 def VLEBRH : TernaryVRX<"vlebrh", 0xE601, z_vlebri16, v128h, v128h, 2, imm32zx3>;291 def VLEBRF : TernaryVRX<"vlebrf", 0xE603, z_vlebri32, v128f, v128f, 4, imm32zx2>;292 def VLEBRG : TernaryVRX<"vlebrg", 0xE602, z_vlebri64, v128g, v128g, 8, imm32zx1>;293 294 // Load byte-reversed element and zero.295 def VLLEBRZ : UnaryVRXGeneric<"vllebrz", 0xE604>;296 def VLLEBRZH : UnaryVRX<"vllebrzh", 0xE604, z_vllebrzi16, v128h, 2, 1>;297 def VLLEBRZF : UnaryVRX<"vllebrzf", 0xE604, z_vllebrzi32, v128f, 4, 2>;298 def VLLEBRZG : UnaryVRX<"vllebrzg", 0xE604, z_vllebrzi64, v128g, 8, 3>;299 def VLLEBRZE : UnaryVRX<"vllebrze", 0xE604, z_vllebrzli32, v128f, 4, 6>;300 def : InstAlias<"lerv\t$V1, $XBD2",301 (VLLEBRZE VR128:$V1, bdxaddr12only:$XBD2), 0>;302 def : InstAlias<"ldrv\t$V1, $XBD2",303 (VLLEBRZG VR128:$V1, bdxaddr12only:$XBD2), 0>;304 305 // Load byte-reversed element and replicate.306 def VLBRREP : UnaryVRXGeneric<"vlbrrep", 0xE605>;307 def VLBRREPH : UnaryVRX<"vlbrreph", 0xE605, z_replicate_loadbswapi16, v128h, 2, 1>;308 def VLBRREPF : UnaryVRX<"vlbrrepf", 0xE605, z_replicate_loadbswapi32, v128f, 4, 2>;309 def VLBRREPG : UnaryVRX<"vlbrrepg", 0xE605, z_replicate_loadbswapi64, v128g, 8, 3>;310 311 // Store byte-reversed elements.312 def VSTBR : StoreVRXGeneric<"vstbr", 0xE60E>;313 def VSTBRH : StoreVRX<"vstbrh", 0xE60E, z_storebswap, v128h, 16, 1>;314 def VSTBRF : StoreVRX<"vstbrf", 0xE60E, z_storebswap, v128f, 16, 2>;315 def VSTBRG : StoreVRX<"vstbrg", 0xE60E, z_storebswap, v128g, 16, 3>;316 def VSTBRQ : StoreVRX<"vstbrq", 0xE60E, z_storebswap, v128q, 16, 4>;317 318 // Store elements reversed.319 def VSTER : StoreVRXGeneric<"vster", 0xE60F>;320 def VSTERH : StoreVRX<"vsterh", 0xE60F, z_storeeswap, v128h, 16, 1>;321 def VSTERF : StoreVRX<"vsterf", 0xE60F, z_storeeswap, v128f, 16, 2>;322 def VSTERG : StoreVRX<"vsterg", 0xE60F, z_storeeswap, v128g, 16, 3>;323 def : Pat<(z_storeeswap (v4f32 VR128:$val), bdxaddr12only:$addr),324 (VSTERF VR128:$val, bdxaddr12only:$addr)>;325 def : Pat<(z_storeeswap (v2f64 VR128:$val), bdxaddr12only:$addr),326 (VSTERG VR128:$val, bdxaddr12only:$addr)>;327 def : Pat<(z_storeeswap (v16i8 VR128:$val), bdxaddr12only:$addr),328 (VSTBRQ VR128:$val, bdxaddr12only:$addr)>;329 330 // Store byte-reversed element.331 def VSTEBRH : StoreBinaryVRX<"vstebrh", 0xE609, z_vstebri16, v128h, 2, imm32zx3>;332 def VSTEBRF : StoreBinaryVRX<"vstebrf", 0xE60B, z_vstebri32, v128f, 4, imm32zx2>;333 def VSTEBRG : StoreBinaryVRX<"vstebrg", 0xE60A, z_vstebri64, v128g, 8, imm32zx1>;334 def : InstAlias<"sterv\t$V1, $XBD2",335 (VSTEBRF VR128:$V1, bdxaddr12only:$XBD2, 0), 0>;336 def : InstAlias<"stdrv\t$V1, $XBD2",337 (VSTEBRG VR128:$V1, bdxaddr12only:$XBD2, 0), 0>;338}339 340//===----------------------------------------------------------------------===//341// Selects and permutes342//===----------------------------------------------------------------------===//343 344let Predicates = [FeatureVector] in {345 // Merge high.346 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>;347 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>;348 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>;349 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>;350 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>;351 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>;352 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>;353 354 // Merge low.355 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>;356 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>;357 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>;358 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>;359 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>;360 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>;361 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>;362 363 // Permute.364 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>;365 366 // Permute doubleword immediate.367 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>;368 369 // Bit Permute.370 let Predicates = [FeatureVectorEnhancements1] in371 def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>;372 373 // Replicate.374 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>;375 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>;376 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>;377 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>;378 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>;379 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16_timm:$index)),380 (VREPF VR128:$vec, imm32zx16:$index)>;381 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16_timm:$index)),382 (VREPG VR128:$vec, imm32zx16:$index)>;383 384 // Select.385 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>;386 387 // Blend.388 let Predicates = [FeatureVectorEnhancements3] in {389 def VBLEND : TernaryVRRdGeneric<"vblend", 0xE789>;390 def VBLENDB : TernaryVRRd<"vblendb", 0xE789, null_frag, v128b, v128b, 0>;391 def VBLENDH : TernaryVRRd<"vblendh", 0xE789, null_frag, v128h, v128h, 1>;392 def VBLENDF : TernaryVRRd<"vblendf", 0xE789, null_frag, v128f, v128f, 2>;393 def VBLENDG : TernaryVRRd<"vblendg", 0xE789, null_frag, v128g, v128g, 3>;394 def VBLENDQ : TernaryVRRd<"vblendq", 0xE789, null_frag, v128q, v128q, 4>;395 }396}397 398//===----------------------------------------------------------------------===//399// Widening and narrowing400//===----------------------------------------------------------------------===//401 402let Predicates = [FeatureVector] in {403 // Pack404 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>;405 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>;406 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>;407 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>;408 409 // Pack saturate.410 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>;411 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc,412 v128b, v128h, 1>;413 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc,414 v128h, v128f, 2>;415 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc,416 v128f, v128g, 3>;417 418 // Pack saturate logical.419 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>;420 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc,421 v128b, v128h, 1>;422 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc,423 v128h, v128f, 2>;424 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc,425 v128f, v128g, 3>;426 427 // Sign-extend to doubleword.428 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>;429 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>;430 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>;431 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>;432 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>;433 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>;434 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>;435 436 // Generate element masks.437 let Predicates = [FeatureVectorEnhancements3] in {438 def VGEM : UnaryVRRaGeneric<"vgem", 0xE754>;439 def VGEMB : UnaryVRRa<"vgemb", 0xE754, int_s390_vgemb, v128b, v128h, 0>;440 def VGEMH : UnaryVRRa<"vgemh", 0xE754, int_s390_vgemh, v128h, v128b, 1>;441 def VGEMF : UnaryVRRa<"vgemf", 0xE754, int_s390_vgemf, v128f, v128b, 2>;442 def VGEMG : UnaryVRRa<"vgemg", 0xE754, int_s390_vgemg, v128g, v128b, 3>;443 def VGEMQ : UnaryVRRa<"vgemq", 0xE754, int_s390_vgemq, v128q, v128b, 4>;444 }445 446 // Unpack high.447 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>;448 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>;449 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>;450 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>;451 let Predicates = [FeatureVectorEnhancements3] in452 def VUPHG : UnaryVRRa<"vuphg", 0xE7D7, z_unpack_high, v128q, v128g, 3>;453 454 // Unpack logical high.455 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>;456 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>;457 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>;458 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>;459 let Predicates = [FeatureVectorEnhancements3] in460 def VUPLHG : UnaryVRRa<"vuplhg", 0xE7D5, z_unpackl_high, v128q, v128g, 3>;461 462 // Unpack low.463 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>;464 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>;465 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>;466 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>;467 let Predicates = [FeatureVectorEnhancements3] in468 def VUPLG : UnaryVRRa<"vuplg", 0xE7D6, z_unpack_low, v128q, v128g, 3>;469 470 // Unpack logical low.471 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>;472 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>;473 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>;474 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>;475 let Predicates = [FeatureVectorEnhancements3] in476 def VUPLLG : UnaryVRRa<"vupllg", 0xE7D4, z_unpackl_low, v128q, v128g, 3>;477}478 479//===----------------------------------------------------------------------===//480// Instantiating generic operations for specific types.481//===----------------------------------------------------------------------===//482 483multiclass GenericVectorOps<ValueType type, ValueType inttype> {484 let Predicates = [FeatureVector] in {485 def : Pat<(type (load bdxaddr12only:$addr)),486 (VL bdxaddr12only:$addr)>;487 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr),488 (VST VR128:$src, bdxaddr12only:$addr)>;489 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)),490 (VSEL VR128:$y, VR128:$z, VR128:$x)>;491 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)),492 (VSEL VR128:$z, VR128:$y, VR128:$x)>;493 }494}495 496defm : GenericVectorOps<v16i8, v16i8>;497defm : GenericVectorOps<v8i16, v8i16>;498defm : GenericVectorOps<v4i32, v4i32>;499defm : GenericVectorOps<v2i64, v2i64>;500defm : GenericVectorOps<v4f32, v4i32>;501defm : GenericVectorOps<v2f64, v2i64>;502 503multiclass BlendVectorOps<ValueType type, ValueType inttype,504 Instruction blend> {505 let Predicates = [FeatureVectorEnhancements3] in {506 def : Pat<(type (vselect (inttype (z_vicmpl_zero VR128:$x)),507 VR128:$y, VR128:$z)),508 (blend VR128:$y, VR128:$z, VR128:$x)>;509 def : Pat<(type (vselect (inttype (z_vnot (z_vicmpl_zero VR128:$x))),510 VR128:$y, VR128:$z)),511 (blend VR128:$z, VR128:$y, VR128:$x)>;512 }513}514 515defm : BlendVectorOps<v16i8, v16i8, VBLENDB>;516defm : BlendVectorOps<v8i16, v8i16, VBLENDH>;517defm : BlendVectorOps<v4i32, v4i32, VBLENDF>;518defm : BlendVectorOps<v2i64, v2i64, VBLENDG>;519defm : BlendVectorOps<v4f32, v4i32, VBLENDF>;520defm : BlendVectorOps<v2f64, v2i64, VBLENDG>;521 522let Predicates = [FeatureVectorEnhancements3] in {523 def : Pat<(i128 (or (and VR128:$y, (z_vicmph 0, VR128:$x)),524 (and VR128:$z, (not (z_vicmph 0, VR128:$x))))),525 (VBLENDQ VR128:$y, VR128:$z, VR128:$x)>;526}527 528//===----------------------------------------------------------------------===//529// Integer arithmetic530//===----------------------------------------------------------------------===//531 532let Predicates = [FeatureVector] in {533 let isCommutable = 1 in {534 // Add.535 def VA : BinaryVRRcGeneric<"va", 0xE7F3>;536 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>;537 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>;538 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>;539 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>;540 def VAQ : BinaryVRRc<"vaq", 0xE7F3, add, v128q, v128q, 4>;541 }542 543 let isCommutable = 1 in {544 // Add compute carry.545 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>;546 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, z_vacc, v128b, v128b, 0>;547 def VACCH : BinaryVRRc<"vacch", 0xE7F1, z_vacc, v128h, v128h, 1>;548 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, z_vacc, v128f, v128f, 2>;549 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, z_vacc, v128g, v128g, 3>;550 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, z_vacc, v128q, v128q, 4>;551 552 // Add with carry.553 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>;554 def VACQ : TernaryVRRd<"vacq", 0xE7BB, z_vac, v128q, v128q, 4>;555 556 // Add with carry compute carry.557 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>;558 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, z_vaccc, v128q, v128q, 4>;559 }560 561 // And.562 let isCommutable = 1 in563 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>;564 565 // And with complement.566 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>;567 568 let isCommutable = 1 in {569 // Average.570 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>;571 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>;572 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>;573 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>;574 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>;575 let Predicates = [FeatureVectorEnhancements3] in576 def VAVGQ : BinaryVRRc<"vavgq", 0xE7F2, int_s390_vavgq, v128q, v128q, 4>;577 578 // Average logical.579 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>;580 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>;581 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>;582 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>;583 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>;584 let Predicates = [FeatureVectorEnhancements3] in585 def VAVGLQ : BinaryVRRc<"vavglq", 0xE7F0, int_s390_vavglq, v128q, v128q, 4>;586 }587 588 // Checksum.589 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>;590 591 // Count leading zeros.592 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>;593 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>;594 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>;595 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>;596 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>;597 let Predicates = [FeatureVectorEnhancements3] in598 def VCLZQ : UnaryVRRa<"vclzq", 0xE753, ctlz, v128q, v128q, 4>;599 600 // Count trailing zeros.601 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>;602 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>;603 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>;604 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>;605 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>;606 let Predicates = [FeatureVectorEnhancements3] in607 def VCTZQ : UnaryVRRa<"vctzq", 0xE752, cttz, v128q, v128q, 4>;608 609 // Divide.610 let Predicates = [FeatureVectorEnhancements3] in {611 let hasSideEffects = 1 in {612 def VD : TernaryVRRcIntGeneric<"vd", 0xE7B2>;613 def VDF : TernaryVRRcInt<"vdf", 0xE7B2, null_frag, v128f, v128f, 2>;614 def VDG : TernaryVRRcInt<"vdg", 0xE7B2, null_frag, v128g, v128g, 3>;615 def VDQ : TernaryVRRcInt<"vdq", 0xE7B2, null_frag, v128q, v128q, 4>;616 }617 def : Pat<(v4i32 (sdiv VR128:$x, VR128:$y)), (VDF VR128:$x, VR128:$y, 0)>;618 def : Pat<(v2i64 (sdiv VR128:$x, VR128:$y)), (VDG VR128:$x, VR128:$y, 0)>;619 def : Pat<(i128 (sdiv VR128:$x, VR128:$y)), (VDQ VR128:$x, VR128:$y, 0)>;620 }621 622 // Divide logical.623 let Predicates = [FeatureVectorEnhancements3] in {624 let hasSideEffects = 1 in {625 def VDL : TernaryVRRcIntGeneric<"vdl", 0xE7B0>;626 def VDLF : TernaryVRRcInt<"vdlf", 0xE7B0, null_frag, v128f, v128f, 2>;627 def VDLG : TernaryVRRcInt<"vdlg", 0xE7B0, null_frag, v128g, v128g, 3>;628 def VDLQ : TernaryVRRcInt<"vdlq", 0xE7B0, null_frag, v128q, v128q, 4>;629 }630 def : Pat<(v4i32 (udiv VR128:$x, VR128:$y)), (VDLF VR128:$x, VR128:$y, 0)>;631 def : Pat<(v2i64 (udiv VR128:$x, VR128:$y)), (VDLG VR128:$x, VR128:$y, 0)>;632 def : Pat<(i128 (udiv VR128:$x, VR128:$y)), (VDLQ VR128:$x, VR128:$y, 0)>;633 }634 635 // Evaluate.636 let Predicates = [FeatureVectorEnhancements3] in637 def VEVAL : QuaternaryVRIk<"veval", 0xE788, int_s390_veval, v128b>;638 639 let isCommutable = 1 in {640 // Not exclusive or.641 let Predicates = [FeatureVectorEnhancements1] in642 def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>;643 644 // Exclusive or.645 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;646 }647 648 // Galois field multiply sum.649 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>;650 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>;651 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>;652 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>;653 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>;654 655 // Galois field multiply sum and accumulate.656 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>;657 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>;658 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>;659 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>;660 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>;661 662 // Load complement.663 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>;664 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>;665 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>;666 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>;667 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>;668 let Predicates = [FeatureVectorEnhancements3] in669 def VLCQ : UnaryVRRa<"vlcq", 0xE7DE, ineg, v128q, v128q, 4>;670 671 // Load positive.672 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>;673 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, abs, v128b, v128b, 0>;674 def VLPH : UnaryVRRa<"vlph", 0xE7DF, abs, v128h, v128h, 1>;675 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, abs, v128f, v128f, 2>;676 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, abs, v128g, v128g, 3>;677 let Predicates = [FeatureVectorEnhancements3] in678 def VLPQ : UnaryVRRa<"vlpq", 0xE7DF, abs, v128q, v128q, 4>;679 680 let isCommutable = 1 in {681 // Maximum.682 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>;683 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, smax, v128b, v128b, 0>;684 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, smax, v128h, v128h, 1>;685 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, smax, v128f, v128f, 2>;686 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, smax, v128g, v128g, 3>;687 let Predicates = [FeatureVectorEnhancements3] in688 def VMXQ : BinaryVRRc<"vmxq", 0xE7FF, smax, v128q, v128q, 4>;689 690 // Maximum logical.691 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>;692 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, umax, v128b, v128b, 0>;693 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, umax, v128h, v128h, 1>;694 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, umax, v128f, v128f, 2>;695 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, umax, v128g, v128g, 3>;696 let Predicates = [FeatureVectorEnhancements3] in697 def VMXLQ : BinaryVRRc<"vmxlq", 0xE7FD, umax, v128q, v128q, 4>;698 }699 700 let isCommutable = 1 in {701 // Minimum.702 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>;703 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, smin, v128b, v128b, 0>;704 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, smin, v128h, v128h, 1>;705 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, smin, v128f, v128f, 2>;706 def VMNG : BinaryVRRc<"vmng", 0xE7FE, smin, v128g, v128g, 3>;707 let Predicates = [FeatureVectorEnhancements3] in708 def VMNQ : BinaryVRRc<"vmnq", 0xE7FE, smin, v128q, v128q, 4>;709 710 // Minimum logical.711 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>;712 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, umin, v128b, v128b, 0>;713 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, umin, v128h, v128h, 1>;714 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, umin, v128f, v128f, 2>;715 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, umin, v128g, v128g, 3>;716 let Predicates = [FeatureVectorEnhancements3] in717 def VMNLQ : BinaryVRRc<"vmnlq", 0xE7FC, umin, v128q, v128q, 4>;718 }719 720 let isCommutable = 1 in {721 // Multiply and add low.722 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>;723 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd<mul>, v128b, v128b, 0>;724 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd<mul>, v128h, v128h, 1>;725 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd<mul>, v128f, v128f, 2>;726 let Predicates = [FeatureVectorEnhancements3] in {727 def VMALG : TernaryVRRd<"vmalg", 0xE7AA, z_muladd<mul>, v128g, v128g, 3>;728 def VMALQ : TernaryVRRd<"vmalq", 0xE7AA, z_muladd<mul>, v128q, v128q, 4>;729 }730 731 // Multiply and add high.732 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>;733 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, z_vmah, v128b, v128b, 0>;734 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, z_vmah, v128h, v128h, 1>;735 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, z_vmah, v128f, v128f, 2>;736 let Predicates = [FeatureVectorEnhancements3] in {737 def VMAHG : TernaryVRRd<"vmahg", 0xE7AB, z_vmah, v128g, v128g, 3>;738 def VMAHQ : TernaryVRRd<"vmahq", 0xE7AB, z_vmah, v128q, v128q, 4>;739 }740 741 // Multiply and add logical high.742 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>;743 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, z_vmalh, v128b, v128b, 0>;744 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, z_vmalh, v128h, v128h, 1>;745 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, z_vmalh, v128f, v128f, 2>;746 let Predicates = [FeatureVectorEnhancements3] in {747 def VMALHG : TernaryVRRd<"vmalhg", 0xE7A9, z_vmalh, v128g, v128g, 3>;748 def VMALHQ : TernaryVRRd<"vmalhq", 0xE7A9, z_vmalh, v128q, v128q, 4>;749 }750 751 // Multiply and add even.752 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>;753 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, z_muladd<z_vme>, v128h, v128b, 0>;754 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, z_muladd<z_vme>, v128f, v128h, 1>;755 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, z_muladd<z_vme>, v128g, v128f, 2>;756 let Predicates = [FeatureVectorEnhancements3] in757 def VMAEG : TernaryVRRd<"vmaeg", 0xE7AE, z_muladd<z_vme>, v128q, v128g, 3>;758 759 // Multiply and add logical even.760 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>;761 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, z_muladd<z_vmle>, v128h, v128b, 0>;762 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, z_muladd<z_vmle>, v128f, v128h, 1>;763 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, z_muladd<z_vmle>, v128g, v128f, 2>;764 let Predicates = [FeatureVectorEnhancements3] in765 def VMALEG : TernaryVRRd<"vmaleg", 0xE7AC, z_muladd<z_vmle>, v128q, v128g, 3>;766 767 // Multiply and add odd.768 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>;769 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, z_muladd<z_vmo>, v128h, v128b, 0>;770 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, z_muladd<z_vmo>, v128f, v128h, 1>;771 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, z_muladd<z_vmo>, v128g, v128f, 2>;772 let Predicates = [FeatureVectorEnhancements3] in773 def VMAOG : TernaryVRRd<"vmaog", 0xE7AF, z_muladd<z_vmo>, v128q, v128g, 3>;774 775 // Multiply and add logical odd.776 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>;777 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, z_muladd<z_vmlo>, v128h, v128b, 0>;778 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, z_muladd<z_vmlo>, v128f, v128h, 1>;779 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, z_muladd<z_vmlo>, v128g, v128f, 2>;780 let Predicates = [FeatureVectorEnhancements3] in781 def VMALOG : TernaryVRRd<"vmalog", 0xE7AD, z_muladd<z_vmlo>, v128q, v128g, 3>;782 }783 784 let isCommutable = 1 in {785 // Multiply high.786 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>;787 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, mulhs, v128b, v128b, 0>;788 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, mulhs, v128h, v128h, 1>;789 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, mulhs, v128f, v128f, 2>;790 let Predicates = [FeatureVectorEnhancements3] in {791 def VMHG : BinaryVRRc<"vmhg", 0xE7A3, mulhs, v128g, v128g, 3>;792 def VMHQ : BinaryVRRc<"vmhq", 0xE7A3, mulhs, v128q, v128q, 4>;793 }794 795 // Multiply logical high.796 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>;797 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, mulhu, v128b, v128b, 0>;798 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, mulhu, v128h, v128h, 1>;799 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, mulhu, v128f, v128f, 2>;800 let Predicates = [FeatureVectorEnhancements3] in {801 def VMLHG : BinaryVRRc<"vmlhg", 0xE7A1, mulhu, v128g, v128g, 3>;802 def VMLHQ : BinaryVRRc<"vmlhq", 0xE7A1, mulhu, v128q, v128q, 4>;803 }804 805 // Multiply low.806 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>;807 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>;808 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>;809 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>;810 let Predicates = [FeatureVectorEnhancements3] in {811 def VMLG : BinaryVRRc<"vmlg", 0xE7A2, mul, v128g, v128g, 3>;812 def VMLQ : BinaryVRRc<"vmlq", 0xE7A2, mul, v128q, v128q, 4>;813 }814 815 // Multiply even.816 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>;817 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, z_vme, v128h, v128b, 0>;818 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, z_vme, v128f, v128h, 1>;819 def VMEF : BinaryVRRc<"vmef", 0xE7A6, z_vme, v128g, v128f, 2>;820 let Predicates = [FeatureVectorEnhancements3] in821 def VMEG : BinaryVRRc<"vmeg", 0xE7A6, z_vme, v128q, v128g, 3>;822 823 // Multiply logical even.824 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>;825 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, z_vmle, v128h, v128b, 0>;826 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, z_vmle, v128f, v128h, 1>;827 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, z_vmle, v128g, v128f, 2>;828 let Predicates = [FeatureVectorEnhancements3] in829 def VMLEG : BinaryVRRc<"vmleg", 0xE7A4, z_vmle, v128q, v128g, 3>;830 831 // Multiply odd.832 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>;833 def VMOB : BinaryVRRc<"vmob", 0xE7A7, z_vmo, v128h, v128b, 0>;834 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, z_vmo, v128f, v128h, 1>;835 def VMOF : BinaryVRRc<"vmof", 0xE7A7, z_vmo, v128g, v128f, 2>;836 let Predicates = [FeatureVectorEnhancements3] in837 def VMOG : BinaryVRRc<"vmog", 0xE7A7, z_vmo, v128q, v128g, 3>;838 839 // Multiply logical odd.840 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>;841 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, z_vmlo, v128h, v128b, 0>;842 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, z_vmlo, v128f, v128h, 1>;843 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, z_vmlo, v128g, v128f, 2>;844 let Predicates = [FeatureVectorEnhancements3] in845 def VMLOG : BinaryVRRc<"vmlog", 0xE7A5, z_vmlo, v128q, v128g, 3>;846 }847 848 // Multiply sum logical.849 let Predicates = [FeatureVectorEnhancements1], isCommutable = 1 in {850 def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>;851 def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg,852 v128q, v128g, v128g, v128q, 3>;853 }854 855 // Nand.856 let Predicates = [FeatureVectorEnhancements1], isCommutable = 1 in857 def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>;858 859 // Nor.860 let isCommutable = 1 in861 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>;862 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>;863 864 // Or.865 let isCommutable = 1 in866 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>;867 868 // Or with complement.869 let Predicates = [FeatureVectorEnhancements1] in870 def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>;871 872 // Population count.873 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>;874 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>;875 let Predicates = [FeatureVectorEnhancements1] in {876 def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>;877 def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>;878 def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>;879 def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>;880 }881 882 // Remainder.883 let Predicates = [FeatureVectorEnhancements3] in {884 let hasSideEffects = 1 in {885 def VR : TernaryVRRcIntGeneric<"vr", 0xE7B3>;886 def VRF : TernaryVRRcInt<"vrf", 0xE7B3, null_frag, v128f, v128f, 2>;887 def VRG : TernaryVRRcInt<"vrg", 0xE7B3, null_frag, v128g, v128g, 3>;888 def VRQ : TernaryVRRcInt<"vrq", 0xE7B3, null_frag, v128q, v128q, 4>;889 }890 def : Pat<(v4i32 (srem VR128:$x, VR128:$y)), (VRF VR128:$x, VR128:$y, 0)>;891 def : Pat<(v2i64 (srem VR128:$x, VR128:$y)), (VRG VR128:$x, VR128:$y, 0)>;892 def : Pat<(i128 (srem VR128:$x, VR128:$y)), (VRQ VR128:$x, VR128:$y, 0)>;893 }894 895 // Remainder logical.896 let Predicates = [FeatureVectorEnhancements3] in {897 let hasSideEffects = 1 in {898 def VRL : TernaryVRRcIntGeneric<"vrl", 0xE7B1>;899 def VRLF : TernaryVRRcInt<"vrlf", 0xE7B1, null_frag, v128f, v128f, 2>;900 def VRLG : TernaryVRRcInt<"vrlg", 0xE7B1, null_frag, v128g, v128g, 3>;901 def VRLQ : TernaryVRRcInt<"vrlq", 0xE7B1, null_frag, v128q, v128q, 4>;902 }903 def : Pat<(v4i32 (urem VR128:$x, VR128:$y)), (VRLF VR128:$x, VR128:$y, 0)>;904 def : Pat<(v2i64 (urem VR128:$x, VR128:$y)), (VRLG VR128:$x, VR128:$y, 0)>;905 def : Pat<(i128 (urem VR128:$x, VR128:$y)), (VRLQ VR128:$x, VR128:$y, 0)>;906 }907 908 // Element rotate left logical (with vector shift amount).909 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>;910 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, rotl, v128b, v128b, 0>;911 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, rotl, v128h, v128h, 1>;912 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, rotl, v128f, v128f, 2>;913 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, rotl, v128g, v128g, 3>;914 915 // Element rotate left logical (with scalar shift amount).916 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>;917 def VERLLB : BinaryVRSa<"verllb", 0xE733, z_vrotl_by_scalar, v128b, v128b, 0>;918 def VERLLH : BinaryVRSa<"verllh", 0xE733, z_vrotl_by_scalar, v128h, v128h, 1>;919 def VERLLF : BinaryVRSa<"verllf", 0xE733, z_vrotl_by_scalar, v128f, v128f, 2>;920 def VERLLG : BinaryVRSa<"verllg", 0xE733, z_vrotl_by_scalar, v128g, v128g, 3>;921 922 // Element rotate and insert under mask.923 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>;924 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>;925 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>;926 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>;927 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>;928 929 // Element shift left (with vector shift amount).930 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>;931 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>;932 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>;933 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>;934 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>;935 936 // Element shift left (with scalar shift amount).937 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>;938 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>;939 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>;940 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>;941 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>;942 943 // Element shift right arithmetic (with vector shift amount).944 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>;945 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>;946 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>;947 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>;948 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>;949 950 // Element shift right arithmetic (with scalar shift amount).951 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>;952 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>;953 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>;954 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>;955 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>;956 957 // Element shift right logical (with vector shift amount).958 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>;959 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>;960 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>;961 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>;962 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>;963 964 // Element shift right logical (with scalar shift amount).965 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>;966 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>;967 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>;968 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>;969 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>;970 971 // Shift left.972 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>;973 974 // Shift left by byte.975 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>;976 977 // Shift left double by byte.978 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>;979 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8_timm:$z),980 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>;981 982 // Shift left double by bit.983 let Predicates = [FeatureVectorEnhancements2] in {984 def VSLD : TernaryVRId<"vsld", 0xE786, z_shl_double_bit, v128b, v128b, 0>;985 def : Pat<(int_s390_vsld VR128:$x, VR128:$y, imm32zx8_timm:$z),986 (VSLD VR128:$x, VR128:$y, imm32zx8:$z)>;987 }988 989 // Shift right arithmetic.990 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>;991 992 // Shift right arithmetic by byte.993 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>;994 995 // Shift right logical.996 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>;997 998 // Shift right logical by byte.999 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>;1000 1001 // Shift right double by bit.1002 let Predicates = [FeatureVectorEnhancements2] in {1003 def VSRD : TernaryVRId<"vsrd", 0xE787, z_shr_double_bit, v128b, v128b, 0>;1004 def : Pat<(int_s390_vsrd VR128:$x, VR128:$y, imm32zx8_timm:$z),1005 (VSRD VR128:$x, VR128:$y, imm32zx8:$z)>;1006 }1007 1008 // Subtract.1009 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>;1010 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>;1011 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>;1012 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>;1013 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>;1014 def VSQ : BinaryVRRc<"vsq", 0xE7F7, sub, v128q, v128q, 4>;1015 1016 // Subtract compute borrow indication.1017 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>;1018 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, z_vscbi, v128b, v128b, 0>;1019 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, z_vscbi, v128h, v128h, 1>;1020 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, z_vscbi, v128f, v128f, 2>;1021 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, z_vscbi, v128g, v128g, 3>;1022 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, z_vscbi, v128q, v128q, 4>;1023 1024 // Subtract with borrow indication.1025 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>;1026 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, z_vsbi, v128q, v128q, 4>;1027 1028 // Subtract with borrow compute borrow indication.1029 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>;1030 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, z_vsbcbi, v128q, v128q, 4>;1031 1032 // Sum across doubleword.1033 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>;1034 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>;1035 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>;1036 1037 // Sum across quadword.1038 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>;1039 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>;1040 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>;1041 1042 // Sum across word.1043 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>;1044 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>;1045 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>;1046}1047 1048// Instantiate the bitwise ops for type TYPE.1049multiclass BitwiseVectorOps<ValueType type, SDPatternOperator not_op> {1050 let Predicates = [FeatureVector] in {1051 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>;1052 def : Pat<(type (and VR128:$x, (not_op VR128:$y))),1053 (VNC VR128:$x, VR128:$y)>;1054 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>;1055 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>;1056 def : Pat<(type (or (and VR128:$x, VR128:$z),1057 (and VR128:$y, (not_op VR128:$z)))),1058 (VSEL VR128:$x, VR128:$y, VR128:$z)>;1059 def : Pat<(type (not_op (or VR128:$x, VR128:$y))),1060 (VNO VR128:$x, VR128:$y)>;1061 def : Pat<(type (not_op VR128:$x)), (VNO VR128:$x, VR128:$x)>;1062 }1063 let Predicates = [FeatureVectorEnhancements1] in {1064 def : Pat<(type (not_op (xor VR128:$x, VR128:$y))),1065 (VNX VR128:$x, VR128:$y)>;1066 def : Pat<(type (not_op (and VR128:$x, VR128:$y))),1067 (VNN VR128:$x, VR128:$y)>;1068 def : Pat<(type (or VR128:$x, (not_op VR128:$y))),1069 (VOC VR128:$x, VR128:$y)>;1070 }1071 let Predicates = [FeatureVectorEnhancements3] in {1072 def : Pat<(type (and VR128:$x, (and VR128:$y, VR128:$z))),1073 (VEVAL VR128:$x, VR128:$y, VR128:$z, 1)>;1074 def : Pat<(type (and (not_op VR128:$z), (and VR128:$x, VR128:$y))),1075 (VEVAL VR128:$x, VR128:$y, VR128:$z, 2)>;1076 def : Pat<(type (and VR128:$x, (xor VR128:$y, VR128:$z))),1077 (VEVAL VR128:$x, VR128:$y, VR128:$z, 6)>;1078 def : Pat<(type (and VR128:$x, (or VR128:$y, VR128:$z))),1079 (VEVAL VR128:$x, VR128:$y, VR128:$z, 7)>;1080 def : Pat<(type (and VR128:$x, (not_op (or VR128:$y, VR128:$z)))),1081 (VEVAL VR128:$x, VR128:$y, VR128:$z, 8)>;1082 def : Pat<(type (and VR128:$x, (not_op (xor VR128:$y, VR128:$z)))),1083 (VEVAL VR128:$x, VR128:$y, VR128:$z, 9)>;1084 def : Pat<(type (and VR128:$x, (or VR128:$y, (not_op VR128:$z)))),1085 (VEVAL VR128:$x, VR128:$y, VR128:$z, 11)>;1086 def : Pat<(type (and VR128:$x, (not_op (and VR128:$y, VR128:$z)))),1087 (VEVAL VR128:$x, VR128:$y, VR128:$z, 14)>;1088 def : Pat<(type (and (or VR128:$x, VR128:$y), (xor VR128:$z, (and VR128:$x, VR128:$y)))),1089 (VEVAL VR128:$x, VR128:$y, VR128:$z, 22)>;1090 def : Pat<(type (or (and VR128:$x, VR128:$y), (and VR128:$z, (or VR128:$x, VR128:$y)))),1091 (VEVAL VR128:$x, VR128:$y, VR128:$z, 23)>;1092 def : Pat<(type (and (xor VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z))),1093 (VEVAL VR128:$x, VR128:$y, VR128:$z, 24)>;1094 def : Pat<(type (and (or VR128:$x, VR128:$y), (not_op (xor VR128:$y, VR128:$z)))),1095 (VEVAL VR128:$x, VR128:$y, VR128:$z, 25)>;1096 def : Pat<(type (and (or VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z))),1097 (VEVAL VR128:$x, VR128:$y, VR128:$z, 26)>;1098 def : Pat<(type (and (or VR128:$x, VR128:$z), (or VR128:$y, (not_op VR128:$z)))),1099 (VEVAL VR128:$x, VR128:$y, VR128:$z, 27)>;1100 def : Pat<(type (xor VR128:$x, (and VR128:$y, VR128:$z))),1101 (VEVAL VR128:$x, VR128:$y, VR128:$z, 30)>;1102 def : Pat<(type (or VR128:$x, (and VR128:$y, VR128:$z))),1103 (VEVAL VR128:$x, VR128:$y, VR128:$z, 31)>;1104 def : Pat<(type (and (not_op VR128:$z), (xor VR128:$x, VR128:$y))),1105 (VEVAL VR128:$x, VR128:$y, VR128:$z, 40)>;1106 def : Pat<(type (and (or VR128:$x, VR128:$y), (not_op (xor VR128:$z, (and VR128:$x, VR128:$y))))),1107 (VEVAL VR128:$x, VR128:$y, VR128:$z, 41)>;1108 def : Pat<(type (and (not_op VR128:$z), (or VR128:$x, VR128:$y))),1109 (VEVAL VR128:$x, VR128:$y, VR128:$z, 42)>;1110 def : Pat<(type (or (and VR128:$x, VR128:$y), (and (not_op VR128:$z), (or VR128:$x, VR128:$y)))),1111 (VEVAL VR128:$x, VR128:$y, VR128:$z, 43)>;1112 def : Pat<(type (xor VR128:$y, (or VR128:$x, (and VR128:$y, VR128:$z)))),1113 (VEVAL VR128:$x, VR128:$y, VR128:$z, 44)>;1114 def : Pat<(type (xor VR128:$x, (and VR128:$y, (not_op VR128:$z)))),1115 (VEVAL VR128:$x, VR128:$y, VR128:$z, 45)>;1116 def : Pat<(type (and (or VR128:$x, VR128:$y), (not_op (and VR128:$y, VR128:$z)))),1117 (VEVAL VR128:$x, VR128:$y, VR128:$z, 46)>;1118 def : Pat<(type (or VR128:$x, (and VR128:$y, (not_op VR128:$z)))),1119 (VEVAL VR128:$x, VR128:$y, VR128:$z, 47)>;1120 def : Pat<(type (or (xor VR128:$x, VR128:$y), (and VR128:$x, VR128:$z))),1121 (VEVAL VR128:$x, VR128:$y, VR128:$z, 61)>;1122 def : Pat<(type (or (xor VR128:$x, VR128:$y), (and VR128:$x, (not_op VR128:$z)))),1123 (VEVAL VR128:$x, VR128:$y, VR128:$z, 62)>;1124 def : Pat<(type (xor (or VR128:$x, VR128:$y), (or VR128:$z, (and VR128:$x, VR128:$y)))),1125 (VEVAL VR128:$x, VR128:$y, VR128:$z, 104)>;1126 def : Pat<(type (xor VR128:$x, (xor VR128:$y, VR128:$z))),1127 (VEVAL VR128:$x, VR128:$y, VR128:$z, 105)>;1128 def : Pat<(type (xor VR128:$z, (or VR128:$x, VR128:$y))),1129 (VEVAL VR128:$x, VR128:$y, VR128:$z, 106)>;1130 def : Pat<(type (or (and VR128:$x, VR128:$y), (xor VR128:$z, (or VR128:$x, VR128:$y)))),1131 (VEVAL VR128:$x, VR128:$y, VR128:$z, 107)>;1132 def : Pat<(type (or (xor VR128:$y, VR128:$z), (and VR128:$x, (not_op VR128:$y)))),1133 (VEVAL VR128:$x, VR128:$y, VR128:$z, 110)>;1134 def : Pat<(type (or VR128:$x, (xor VR128:$y, VR128:$z))),1135 (VEVAL VR128:$x, VR128:$y, VR128:$z, 111)>;1136 def : Pat<(type (or (xor VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z))),1137 (VEVAL VR128:$x, VR128:$y, VR128:$z, 126)>;1138 def : Pat<(type (or VR128:$x, (or VR128:$y, VR128:$z))),1139 (VEVAL VR128:$x, VR128:$y, VR128:$z, 127)>;1140 def : Pat<(type (not_op (or VR128:$x, (or VR128:$y, VR128:$z)))),1141 (VEVAL VR128:$x, VR128:$y, VR128:$z, 128)>;1142 def : Pat<(type (not_op (or (xor VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z)))),1143 (VEVAL VR128:$x, VR128:$y, VR128:$z, 129)>;1144 def : Pat<(type (not_op (or VR128:$z, (xor VR128:$x, VR128:$y)))),1145 (VEVAL VR128:$x, VR128:$y, VR128:$z, 130)>;1146 def : Pat<(type (and (not_op (xor VR128:$x, VR128:$y)), (or VR128:$x, (not_op VR128:$z)))),1147 (VEVAL VR128:$x, VR128:$y, VR128:$z, 131)>;1148 def : Pat<(type (xor (or VR128:$y, VR128:$z), (or (not_op VR128:$x), (and VR128:$y, VR128:$z)))),1149 (VEVAL VR128:$x, VR128:$y, VR128:$z, 134)>;1150 def : Pat<(type (not_op (xor VR128:$x, (or VR128:$y, VR128:$z)))),1151 (VEVAL VR128:$x, VR128:$y, VR128:$z, 135)>;1152 def : Pat<(type (or (not_op (or VR128:$y, VR128:$z)), (and VR128:$x, (and VR128:$y, VR128:$z)))),1153 (VEVAL VR128:$x, VR128:$y, VR128:$z, 137)>;1154 def : Pat<(type (and (not_op VR128:$z), (or VR128:$x, (not_op VR128:$y)))),1155 (VEVAL VR128:$x, VR128:$y, VR128:$z, 138)>;1156 def : Pat<(type (or (and VR128:$x, VR128:$y), (not_op (or VR128:$y, VR128:$z)))),1157 (VEVAL VR128:$x, VR128:$y, VR128:$z, 139)>;1158 def : Pat<(type (or (not_op (or VR128:$y, VR128:$z)), (and VR128:$x, (xor VR128:$y, VR128:$z)))),1159 (VEVAL VR128:$x, VR128:$y, VR128:$z, 142)>;1160 def : Pat<(type (or VR128:$x, (not_op (or VR128:$y, VR128:$z)))),1161 (VEVAL VR128:$x, VR128:$y, VR128:$z, 143)>;1162 def : Pat<(type (not_op (xor VR128:$x, (xor VR128:$y, VR128:$z)))),1163 (VEVAL VR128:$x, VR128:$y, VR128:$z, 150)>;1164 def : Pat<(type (or (and VR128:$x, VR128:$y), (not_op (xor VR128:$z, (or VR128:$x, VR128:$y))))),1165 (VEVAL VR128:$x, VR128:$y, VR128:$z, 151)>;1166 def : Pat<(type (not_op (or (and VR128:$x, VR128:$y), (xor VR128:$y, VR128:$z)))),1167 (VEVAL VR128:$x, VR128:$y, VR128:$z, 152)>;1168 def : Pat<(type (xor VR128:$z, (or VR128:$x, (not_op VR128:$y)))),1169 (VEVAL VR128:$x, VR128:$y, VR128:$z, 154)>;1170 def : Pat<(type (or (and VR128:$x, VR128:$y), (not_op (xor VR128:$y, VR128:$z)))),1171 (VEVAL VR128:$x, VR128:$y, VR128:$z, 155)>;1172 def : Pat<(type (or (not_op (or VR128:$y, VR128:$z)), (xor VR128:$x, (and VR128:$y, VR128:$z)))),1173 (VEVAL VR128:$x, VR128:$y, VR128:$z, 158)>;1174 def : Pat<(type (or VR128:$x, (not_op (xor VR128:$y, VR128:$z)))),1175 (VEVAL VR128:$x, VR128:$y, VR128:$z, 159)>;1176 def : Pat<(type (not_op (or VR128:$z, (and VR128:$x, VR128:$y)))),1177 (VEVAL VR128:$x, VR128:$y, VR128:$z, 168)>;1178 def : Pat<(type (not_op (xor VR128:$z, (and VR128:$x, VR128:$y)))),1179 (VEVAL VR128:$x, VR128:$y, VR128:$z, 169)>;1180 def : Pat<(type (or (not_op VR128:$z), (and VR128:$x, VR128:$y))),1181 (VEVAL VR128:$x, VR128:$y, VR128:$z, 171)>;1182 def : Pat<(type (and (not_op (and VR128:$x, VR128:$y)), (or VR128:$x, (not_op VR128:$z)))),1183 (VEVAL VR128:$x, VR128:$y, VR128:$z, 172)>;1184 def : Pat<(type (not_op (and (xor VR128:$x, VR128:$z), (or VR128:$y, VR128:$z)))),1185 (VEVAL VR128:$x, VR128:$y, VR128:$z, 173)>;1186 def : Pat<(type (or (not_op VR128:$z), (and VR128:$x, (not_op VR128:$y)))),1187 (VEVAL VR128:$x, VR128:$y, VR128:$z, 174)>;1188 def : Pat<(type (or (xor VR128:$x, VR128:$y), (not_op (or VR128:$x, VR128:$z)))),1189 (VEVAL VR128:$x, VR128:$y, VR128:$z, 188)>;1190 def : Pat<(type (not_op (and (xor VR128:$x, VR128:$z), (xor VR128:$y, VR128:$z)))),1191 (VEVAL VR128:$x, VR128:$y, VR128:$z, 189)>;1192 def : Pat<(type (or (not_op VR128:$z), (xor VR128:$x, VR128:$y))),1193 (VEVAL VR128:$x, VR128:$y, VR128:$z, 190)>;1194 def : Pat<(type (or (not_op VR128:$z), (or VR128:$x, VR128:$y))),1195 (VEVAL VR128:$x, VR128:$y, VR128:$z, 191)>;1196 def : Pat<(type (or (not_op (or VR128:$x, VR128:$y)), (and (not_op VR128:$z), (xor VR128:$x, VR128:$y)))),1197 (VEVAL VR128:$x, VR128:$y, VR128:$z, 232)>;1198 def : Pat<(type (xor (not_op (and VR128:$x, VR128:$y)), (and VR128:$z, (or VR128:$x, VR128:$y)))),1199 (VEVAL VR128:$x, VR128:$y, VR128:$z, 233)>;1200 def : Pat<(type (not_op (and VR128:$z, (or VR128:$x, VR128:$y)))),1201 (VEVAL VR128:$x, VR128:$y, VR128:$z, 234)>;1202 def : Pat<(type (not_op (and VR128:$z, (xor VR128:$x, VR128:$y)))),1203 (VEVAL VR128:$x, VR128:$y, VR128:$z, 235)>;1204 def : Pat<(type (or VR128:$x, (not_op (and VR128:$y, VR128:$z)))),1205 (VEVAL VR128:$x, VR128:$y, VR128:$z, 239)>;1206 def : Pat<(type (not_op (and VR128:$x, (and VR128:$y, VR128:$z)))),1207 (VEVAL VR128:$x, VR128:$y, VR128:$z, 254)>;1208 }1209}1210 1211defm : BitwiseVectorOps<v16i8, z_vnot>;1212defm : BitwiseVectorOps<v8i16, z_vnot>;1213defm : BitwiseVectorOps<v4i32, z_vnot>;1214defm : BitwiseVectorOps<v2i64, z_vnot>;1215defm : BitwiseVectorOps<i128, not>;1216 1217// Instantiate additional patterns for absolute-related expressions on1218// type TYPE. LC is the negate instruction for TYPE and LP is the absolute1219// instruction.1220multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc,1221 Instruction lp, int shift> {1222 let Predicates = [FeatureVector] in {1223 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)),1224 (z_vneg VR128:$x), VR128:$x)),1225 (lc (lp VR128:$x))>;1226 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))),1227 VR128:$x, (z_vneg VR128:$x))),1228 (lc (lp VR128:$x))>;1229 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)),1230 VR128:$x, (z_vneg VR128:$x))),1231 (lc (lp VR128:$x))>;1232 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))),1233 (z_vneg VR128:$x), VR128:$x)),1234 (lc (lp VR128:$x))>;1235 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),1236 (z_vneg VR128:$x)),1237 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),1238 VR128:$x))),1239 (lp VR128:$x)>;1240 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),1241 VR128:$x),1242 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),1243 (z_vneg VR128:$x)))),1244 (lc (lp VR128:$x))>;1245 }1246}1247 1248defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>;1249defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>;1250defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>;1251defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>;1252 1253// Instantiate packs/packu: recognize a saturating truncation and convert1254// into the corresponding packs/packu instruction.1255multiclass SignedSaturatingTruncate<ValueType input, ValueType output,1256 Instruction packs> {1257 def : Pat<1258 (output (z_pack1259 (smin (smax (input VR128:$a), ssat_trunc_min_vec), ssat_trunc_max_vec),1260 (smin (smax (input VR128:$b), ssat_trunc_min_vec), ssat_trunc_max_vec)1261 )),1262 (packs VR128:$a, VR128:$b)1263 >;1264 1265 def : Pat<1266 (output (z_pack1267 (smax (smin (input VR128:$a), ssat_trunc_max_vec), ssat_trunc_min_vec),1268 (smax (smin (input VR128:$b), ssat_trunc_max_vec), ssat_trunc_min_vec)1269 )),1270 (packs VR128:$a, VR128:$b)1271 >;1272}1273 1274defm : SignedSaturatingTruncate<v8i16, v16i8, VPKSH>;1275defm : SignedSaturatingTruncate<v4i32, v8i16, VPKSF>;1276defm : SignedSaturatingTruncate<v2i64, v4i32, VPKSG>;1277 1278multiclass UnsignedSaturatingTruncate<ValueType input, ValueType output,1279 Instruction packu> {1280 def : Pat<1281 (output (z_pack1282 (umin (input VR128:$a), usat_trunc_max_vec),1283 (umin (input VR128:$b), usat_trunc_max_vec)1284 )),1285 (packu VR128:$a, VR128:$b)1286 >;1287}1288 1289defm : UnsignedSaturatingTruncate<v8i16, v16i8, VPKLSH>;1290defm : UnsignedSaturatingTruncate<v4i32, v8i16, VPKLSF>;1291defm : UnsignedSaturatingTruncate<v2i64, v4i32, VPKLSG>;1292 1293// Instantiate comparison patterns to recognize VACC/VSCBI for TYPE.1294multiclass IntegerComputeCarryOrBorrow<ValueType type,1295 Instruction vacc, Instruction vscbi> {1296 let Predicates = [FeatureVector] in {1297 def : Pat<(z_vzext1 (type (z_vicmphl VR128:$x, (add VR128:$x, VR128:$y)))),1298 (vacc VR128:$x, VR128:$y)>;1299 def : Pat<(z_vzext1 (type (z_vicmphl VR128:$y, (add VR128:$x, VR128:$y)))),1300 (vacc VR128:$x, VR128:$y)>;1301 def : Pat<(z_vzext1 (z_vnot (type (z_vicmphl VR128:$y, VR128:$x)))),1302 (vscbi VR128:$x, VR128:$y)>;1303 }1304}1305defm : IntegerComputeCarryOrBorrow<v16i8, VACCB, VSCBIB>;1306defm : IntegerComputeCarryOrBorrow<v8i16, VACCH, VSCBIH>;1307defm : IntegerComputeCarryOrBorrow<v4i32, VACCF, VSCBIF>;1308defm : IntegerComputeCarryOrBorrow<v2i64, VACCG, VSCBIG>;1309 1310// Instantiate full-vector shifts.1311multiclass FullVectorShiftOps<SDPatternOperator shift,1312 Instruction sbit, Instruction sbyte> {1313 let Predicates = [FeatureVector] in {1314 def : Pat<(shift (i128 VR128:$x), imm32nobytes:$amt),1315 (sbit VR128:$x, (VREPIB (UIMM8 imm:$amt)))>;1316 def : Pat<(shift (i128 VR128:$x), imm32nobits:$amt),1317 (sbyte VR128:$x, (VREPIB (UIMM8 imm:$amt)))>;1318 def : Pat<(shift (i128 VR128:$x), imm32:$amt),1319 (sbit (sbyte VR128:$x, (VREPIB (UIMM8 imm:$amt))),1320 (VREPIB (UIMM8 imm:$amt)))>;1321 def : Pat<(shift (i128 VR128:$x), GR32:$amt),1322 (sbit (sbyte VR128:$x, (VREPB (VLVGP32 GR32:$amt, GR32:$amt), 15)),1323 (VREPB (VLVGP32 GR32:$amt, GR32:$amt), 15))>;1324 }1325}1326defm : FullVectorShiftOps<vshiftop<shl>, VSL, VSLB>;1327defm : FullVectorShiftOps<vshiftop<srl>, VSRL, VSRLB>;1328defm : FullVectorShiftOps<vshiftop<sra>, VSRA, VSRAB>;1329 1330//===----------------------------------------------------------------------===//1331// Integer comparison1332//===----------------------------------------------------------------------===//1333 1334let Predicates = [FeatureVector] in {1335 // Element compare.1336 let Defs = [CC] in {1337 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>;1338 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>;1339 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>;1340 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>;1341 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>;1342 let Predicates = [FeatureVectorEnhancements3] in1343 def VECQ : CompareVRRa<"vecq", 0xE7DB, z_scmp, v128q, 4>;1344 }1345 1346 // Element compare logical.1347 let Defs = [CC] in {1348 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>;1349 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>;1350 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>;1351 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>;1352 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>;1353 let Predicates = [FeatureVectorEnhancements3] in1354 def VECLQ : CompareVRRa<"veclq", 0xE7D9, z_ucmp, v128q, 4>;1355 }1356 1357 // Compare equal.1358 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>;1359 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes,1360 v128b, v128b, 0>;1361 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes,1362 v128h, v128h, 1>;1363 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes,1364 v128f, v128f, 2>;1365 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes,1366 v128g, v128g, 3>;1367 let Predicates = [FeatureVectorEnhancements3] in1368 defm VCEQQ : BinaryVRRbSPair<"vceqq", 0xE7F8, z_vicmpe, z_vicmpes,1369 v128q, v128q, 4>;1370 1371 // Compare high.1372 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>;1373 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs,1374 v128b, v128b, 0>;1375 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs,1376 v128h, v128h, 1>;1377 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs,1378 v128f, v128f, 2>;1379 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs,1380 v128g, v128g, 3>;1381 let Predicates = [FeatureVectorEnhancements3] in1382 defm VCHQ : BinaryVRRbSPair<"vchq", 0xE7FB, z_vicmph, z_vicmphs,1383 v128q, v128q, 4>;1384 1385 // Compare high logical.1386 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>;1387 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls,1388 v128b, v128b, 0>;1389 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls,1390 v128h, v128h, 1>;1391 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls,1392 v128f, v128f, 2>;1393 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls,1394 v128g, v128g, 3>;1395 let Predicates = [FeatureVectorEnhancements3] in1396 defm VCHLQ : BinaryVRRbSPair<"vchlq", 0xE7F9, z_vicmphl, z_vicmphls,1397 v128q, v128q, 4>;1398 1399 // Test under mask.1400 let Defs = [CC] in1401 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>;1402}1403 1404//===----------------------------------------------------------------------===//1405// Floating-point arithmetic1406//===----------------------------------------------------------------------===//1407 1408// See comments in SystemZInstrFP.td for the suppression flags and1409// rounding modes.1410multiclass VectorRounding<Instruction insn, TypedReg tr> {1411 def : FPConversion<insn, any_frint, tr, tr, 0, 0>;1412 def : FPConversion<insn, any_fnearbyint, tr, tr, 4, 0>;1413 def : FPConversion<insn, any_ffloor, tr, tr, 4, 7>;1414 def : FPConversion<insn, any_fceil, tr, tr, 4, 6>;1415 def : FPConversion<insn, any_ftrunc, tr, tr, 4, 5>;1416 def : FPConversion<insn, any_froundeven, tr, tr, 4, 4>;1417 def : FPConversion<insn, any_fround, tr, tr, 4, 1>;1418}1419 1420let Predicates = [FeatureVector] in {1421 // Add.1422 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in {1423 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>;1424 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, any_fadd, v128db, v128db, 3, 0>;1425 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, any_fadd, v64db, v64db, 3, 8, 0,1426 "adbr">;1427 let Predicates = [FeatureVectorEnhancements1] in {1428 def VFASB : BinaryVRRc<"vfasb", 0xE7E3, any_fadd, v128sb, v128sb, 2, 0>;1429 def WFASB : BinaryVRRc<"wfasb", 0xE7E3, any_fadd, v32sb, v32sb, 2, 8, 0,1430 "aebr">;1431 def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, any_fadd, v128xb, v128xb, 4, 8>;1432 }1433 }1434 1435 // Convert from fixed.1436 let Uses = [FPC], mayRaiseFPException = 1 in {1437 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>;1438 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>;1439 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>;1440 }1441 def : FPConversion<VCDGB, any_sint_to_fp, v128db, v128g, 0, 0>;1442 let Predicates = [FeatureVectorEnhancements2] in {1443 let Uses = [FPC], mayRaiseFPException = 1 in {1444 let isAsmParserOnly = 1 in1445 def VCFPS : TernaryVRRaFloatGeneric<"vcfps", 0xE7C3>;1446 def VCEFB : TernaryVRRa<"vcefb", 0xE7C3, null_frag, v128sb, v128g, 2, 0>;1447 def WCEFB : TernaryVRRa<"wcefb", 0xE7C3, null_frag, v32sb, v32f, 2, 8>;1448 }1449 def : FPConversion<VCEFB, any_sint_to_fp, v128sb, v128f, 0, 0>;1450 }1451 1452 // Convert from logical.1453 let Uses = [FPC], mayRaiseFPException = 1 in {1454 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>;1455 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>;1456 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>;1457 }1458 def : FPConversion<VCDLGB, any_uint_to_fp, v128db, v128g, 0, 0>;1459 let Predicates = [FeatureVectorEnhancements2] in {1460 let Uses = [FPC], mayRaiseFPException = 1 in {1461 let isAsmParserOnly = 1 in1462 def VCFPL : TernaryVRRaFloatGeneric<"vcfpl", 0xE7C1>;1463 def VCELFB : TernaryVRRa<"vcelfb", 0xE7C1, null_frag, v128sb, v128g, 2, 0>;1464 def WCELFB : TernaryVRRa<"wcelfb", 0xE7C1, null_frag, v32sb, v32f, 2, 8>;1465 }1466 def : FPConversion<VCELFB, any_uint_to_fp, v128sb, v128f, 0, 0>;1467 }1468 1469 // Convert to fixed.1470 let Uses = [FPC], mayRaiseFPException = 1 in {1471 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>;1472 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>;1473 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>;1474 }1475 // Rounding mode should agree with SystemZInstrFP.td.1476 def : FPConversion<VCGDB, any_fp_to_sint, v128g, v128db, 0, 5>;1477 let Predicates = [FeatureVectorEnhancements2] in {1478 let Uses = [FPC], mayRaiseFPException = 1 in {1479 let isAsmParserOnly = 1 in1480 def VCSFP : TernaryVRRaFloatGeneric<"vcsfp", 0xE7C2>;1481 def VCFEB : TernaryVRRa<"vcfeb", 0xE7C2, null_frag, v128sb, v128g, 2, 0>;1482 def WCFEB : TernaryVRRa<"wcfeb", 0xE7C2, null_frag, v32sb, v32f, 2, 8>;1483 }1484 // Rounding mode should agree with SystemZInstrFP.td.1485 def : FPConversion<VCFEB, any_fp_to_sint, v128f, v128sb, 0, 5>;1486 }1487 1488 // Convert to logical.1489 let Uses = [FPC], mayRaiseFPException = 1 in {1490 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>;1491 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>;1492 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>;1493 }1494 // Rounding mode should agree with SystemZInstrFP.td.1495 def : FPConversion<VCLGDB, any_fp_to_uint, v128g, v128db, 0, 5>;1496 let Predicates = [FeatureVectorEnhancements2] in {1497 let Uses = [FPC], mayRaiseFPException = 1 in {1498 let isAsmParserOnly = 1 in1499 def VCLFP : TernaryVRRaFloatGeneric<"vclfp", 0xE7C0>;1500 def VCLFEB : TernaryVRRa<"vclfeb", 0xE7C0, null_frag, v128sb, v128g, 2, 0>;1501 def WCLFEB : TernaryVRRa<"wclfeb", 0xE7C0, null_frag, v32sb, v32f, 2, 8>;1502 }1503 // Rounding mode should agree with SystemZInstrFP.td.1504 def : FPConversion<VCLFEB, any_fp_to_uint, v128f, v128sb, 0, 5>;1505 }1506 1507 // Divide.1508 let Uses = [FPC], mayRaiseFPException = 1 in {1509 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>;1510 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, any_fdiv, v128db, v128db, 3, 0>;1511 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, any_fdiv, v64db, v64db, 3, 8, 0,1512 "ddbr">;1513 let Predicates = [FeatureVectorEnhancements1] in {1514 def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, any_fdiv, v128sb, v128sb, 2, 0>;1515 def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, any_fdiv, v32sb, v32sb, 2, 8, 0,1516 "debr">;1517 def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, any_fdiv, v128xb, v128xb, 4, 8>;1518 }1519 }1520 1521 // Load FP integer.1522 let Uses = [FPC], mayRaiseFPException = 1 in {1523 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>;1524 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>;1525 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>;1526 }1527 defm : VectorRounding<VFIDB, v128db>;1528 defm : VectorRounding<WFIDB, v64db>;1529 let Predicates = [FeatureVectorEnhancements1] in {1530 let Uses = [FPC], mayRaiseFPException = 1 in {1531 def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>;1532 def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>;1533 def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>;1534 }1535 defm : VectorRounding<VFISB, v128sb>;1536 defm : VectorRounding<WFISB, v32sb>;1537 defm : VectorRounding<WFIXB, v128xb>;1538 }1539 1540 // Load lengthened.1541 let Uses = [FPC], mayRaiseFPException = 1 in {1542 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>;1543 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_any_vextend, v128db, v128sb, 2, 0>;1544 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, any_fpextend, v64db, v32sb, 2, 8, 0,1545 "ldebr">;1546 }1547 let Predicates = [FeatureVectorEnhancements1] in {1548 let Uses = [FPC], mayRaiseFPException = 1 in {1549 let isAsmParserOnly = 1 in {1550 def VFLL : UnaryVRRaFloatGeneric<"vfll", 0xE7C4>;1551 def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>;1552 def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>;1553 }1554 def WFLLD : UnaryVRRa<"wflld", 0xE7C4, any_fpextend, v128xb, v64db, 3, 8>;1555 }1556 def : Pat<(f128 (any_fpextend (f32 VR32:$src))),1557 (WFLLD (WLDEB VR32:$src))>;1558 }1559 1560 // Load rounded.1561 let Uses = [FPC], mayRaiseFPException = 1 in {1562 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>;1563 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>;1564 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>;1565 }1566 def : Pat<(v4f32 (z_any_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>;1567 def : FPConversion<WLEDB, any_fpround, v32sb, v64db, 0, 0>;1568 let Predicates = [FeatureVectorEnhancements1] in {1569 let Uses = [FPC], mayRaiseFPException = 1 in {1570 let isAsmParserOnly = 1 in {1571 def VFLR : TernaryVRRaFloatGeneric<"vflr", 0xE7C5>;1572 def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>;1573 def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>;1574 }1575 def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>;1576 }1577 def : FPConversion<WFLRX, any_fpround, v64db, v128xb, 0, 0>;1578 def : Pat<(f32 (any_fpround (f128 VR128:$src))),1579 (WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>;1580 }1581 1582 // Maximum.1583 multiclass VectorMax<Instruction insn, TypedReg tr> {1584 def : FPMinMax<insn, any_fmaxnum, tr, 4>;1585 def : FPMinMax<insn, any_fmaximum, tr, 1>;1586 }1587 let Predicates = [FeatureVectorEnhancements1] in {1588 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in {1589 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>;1590 def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb,1591 v128db, v128db, 3, 0>;1592 def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag,1593 v64db, v64db, 3, 8>;1594 def VFMAXSB : TernaryVRRcFloat<"vfmaxsb", 0xE7EF, int_s390_vfmaxsb,1595 v128sb, v128sb, 2, 0>;1596 def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag,1597 v32sb, v32sb, 2, 8>;1598 def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag,1599 v128xb, v128xb, 4, 8>;1600 }1601 defm : VectorMax<VFMAXDB, v128db>;1602 defm : VectorMax<WFMAXDB, v64db>;1603 defm : VectorMax<VFMAXSB, v128sb>;1604 defm : VectorMax<WFMAXSB, v32sb>;1605 defm : VectorMax<WFMAXXB, v128xb>;1606 }1607 1608 // Minimum.1609 multiclass VectorMin<Instruction insn, TypedReg tr> {1610 def : FPMinMax<insn, any_fminnum, tr, 4>;1611 def : FPMinMax<insn, any_fminimum, tr, 1>;1612 }1613 let Predicates = [FeatureVectorEnhancements1] in {1614 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in {1615 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>;1616 def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb,1617 v128db, v128db, 3, 0>;1618 def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag,1619 v64db, v64db, 3, 8>;1620 def VFMINSB : TernaryVRRcFloat<"vfminsb", 0xE7EE, int_s390_vfminsb,1621 v128sb, v128sb, 2, 0>;1622 def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag,1623 v32sb, v32sb, 2, 8>;1624 def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag,1625 v128xb, v128xb, 4, 8>;1626 }1627 defm : VectorMin<VFMINDB, v128db>;1628 defm : VectorMin<WFMINDB, v64db>;1629 defm : VectorMin<VFMINSB, v128sb>;1630 defm : VectorMin<WFMINSB, v32sb>;1631 defm : VectorMin<WFMINXB, v128xb>;1632 }1633 1634 // Multiply.1635 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in {1636 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>;1637 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, any_fmul, v128db, v128db, 3, 0>;1638 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, any_fmul, v64db, v64db, 3, 8, 0,1639 "mdbr">;1640 let Predicates = [FeatureVectorEnhancements1] in {1641 def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, any_fmul, v128sb, v128sb, 2, 0>;1642 def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, any_fmul, v32sb, v32sb, 2, 8, 0,1643 "meebr">;1644 def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, any_fmul, v128xb, v128xb, 4, 8>;1645 }1646 }1647 1648 // Multiply and add.1649 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in {1650 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>;1651 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, any_fma, v128db, v128db, 0, 3>;1652 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, any_fma, v64db, v64db, 8, 3,1653 "madbr">;1654 let Predicates = [FeatureVectorEnhancements1] in {1655 def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, any_fma, v128sb, v128sb, 0, 2>;1656 def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, any_fma, v32sb, v32sb, 8, 2,1657 "maebr">;1658 def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, any_fma, v128xb, v128xb, 8, 4>;1659 }1660 }1661 1662 // Multiply and subtract.1663 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in {1664 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>;1665 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, any_fms, v128db, v128db, 0, 3>;1666 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, any_fms, v64db, v64db, 8, 3,1667 "msdbr">;1668 let Predicates = [FeatureVectorEnhancements1] in {1669 def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, any_fms, v128sb, v128sb, 0, 2>;1670 def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, any_fms, v32sb, v32sb, 8, 2,1671 "msebr">;1672 def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, any_fms, v128xb, v128xb, 8, 4>;1673 }1674 }1675 1676 // Negative multiply and add.1677 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1,1678 Predicates = [FeatureVectorEnhancements1] in {1679 def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>;1680 def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, any_fnma, v128db, v128db, 0, 3>;1681 def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, any_fnma, v64db, v64db, 8, 3>;1682 def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, any_fnma, v128sb, v128sb, 0, 2>;1683 def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, any_fnma, v32sb, v32sb, 8, 2>;1684 def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, any_fnma, v128xb, v128xb, 8, 4>;1685 }1686 1687 // Negative multiply and subtract.1688 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1,1689 Predicates = [FeatureVectorEnhancements1] in {1690 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>;1691 def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, any_fnms, v128db, v128db, 0, 3>;1692 def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, any_fnms, v64db, v64db, 8, 3>;1693 def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, any_fnms, v128sb, v128sb, 0, 2>;1694 def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, any_fnms, v32sb, v32sb, 8, 2>;1695 def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, any_fnms, v128xb, v128xb, 8, 4>;1696 }1697 1698 // Perform sign operation.1699 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>;1700 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>;1701 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>;1702 let Predicates = [FeatureVectorEnhancements1] in {1703 def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>;1704 def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>;1705 def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>;1706 }1707 1708 // Load complement.1709 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>;1710 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>;1711 let Predicates = [FeatureVectorEnhancements1] in {1712 def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>;1713 def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>;1714 def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>;1715 }1716 1717 // Load negative.1718 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>;1719 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>;1720 let Predicates = [FeatureVectorEnhancements1] in {1721 def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>;1722 def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>;1723 def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>;1724 }1725 1726 // Load positive.1727 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>;1728 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>;1729 let Predicates = [FeatureVectorEnhancements1] in {1730 def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>;1731 def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>;1732 def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>;1733 }1734 1735 // Square root.1736 let Uses = [FPC], mayRaiseFPException = 1 in {1737 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>;1738 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, any_fsqrt, v128db, v128db, 3, 0>;1739 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, any_fsqrt, v64db, v64db, 3, 8, 0,1740 "sqdbr">;1741 let Predicates = [FeatureVectorEnhancements1] in {1742 def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, any_fsqrt, v128sb, v128sb, 2, 0>;1743 def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, any_fsqrt, v32sb, v32sb, 2, 8, 0,1744 "sqebr">;1745 def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, any_fsqrt, v128xb, v128xb, 4, 8>;1746 }1747 }1748 1749 // Subtract.1750 let Uses = [FPC], mayRaiseFPException = 1 in {1751 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>;1752 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, any_fsub, v128db, v128db, 3, 0>;1753 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, any_fsub, v64db, v64db, 3, 8, 0,1754 "sdbr">;1755 let Predicates = [FeatureVectorEnhancements1] in {1756 def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, any_fsub, v128sb, v128sb, 2, 0>;1757 def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, any_fsub, v32sb, v32sb, 2, 8, 0,1758 "sebr">;1759 def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, any_fsub, v128xb, v128xb, 4, 8>;1760 }1761 }1762 1763 // Test data class immediate.1764 let Defs = [CC] in {1765 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>;1766 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>;1767 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>;1768 let Predicates = [FeatureVectorEnhancements1] in {1769 def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>;1770 def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>;1771 def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>;1772 }1773 }1774}1775 1776//===----------------------------------------------------------------------===//1777// Floating-point comparison1778//===----------------------------------------------------------------------===//1779 1780let Predicates = [FeatureVector] in {1781 // Compare scalar.1782 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {1783 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>;1784 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_any_fcmp, v64db, 3, "cdbr">;1785 let Predicates = [FeatureVectorEnhancements1] in {1786 def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_any_fcmp, v32sb, 2, "cebr">;1787 def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_any_fcmp, v128xb, 4>;1788 }1789 }1790 1791 // Compare and signal scalar.1792 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in {1793 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>;1794 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, z_strict_fcmps, v64db, 3, "kdbr">;1795 let Predicates = [FeatureVectorEnhancements1] in {1796 def WFKSB : CompareVRRa<"wfksb", 0xE7CA, z_strict_fcmps, v32sb, 2, "kebr">;1797 def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, z_strict_fcmps, v128xb, 4>;1798 }1799 }1800 1801 // Compare equal.1802 let Uses = [FPC], mayRaiseFPException = 1 in {1803 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>;1804 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_any_vfcmpe, z_vfcmpes,1805 v128g, v128db, 3, 0>;1806 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag,1807 v64g, v64db, 3, 8>;1808 let Predicates = [FeatureVectorEnhancements1] in {1809 defm VFCESB : BinaryVRRcSPair<"vfcesb", 0xE7E8, z_any_vfcmpe, z_vfcmpes,1810 v128f, v128sb, 2, 0>;1811 defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag,1812 v32f, v32sb, 2, 8>;1813 defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag,1814 v128q, v128xb, 4, 8>;1815 }1816 }1817 1818 // Compare and signal equal.1819 let Uses = [FPC], mayRaiseFPException = 1,1820 Predicates = [FeatureVectorEnhancements1] in {1821 defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, z_strict_vfcmpes, null_frag,1822 v128g, v128db, 3, 4>;1823 defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag,1824 v64g, v64db, 3, 12>;1825 defm VFKESB : BinaryVRRcSPair<"vfkesb", 0xE7E8, z_strict_vfcmpes, null_frag,1826 v128f, v128sb, 2, 4>;1827 defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag,1828 v32f, v32sb, 2, 12>;1829 defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag,1830 v128q, v128xb, 4, 12>;1831 }1832 1833 // Compare high.1834 let Uses = [FPC], mayRaiseFPException = 1 in {1835 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>;1836 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_any_vfcmph, z_vfcmphs,1837 v128g, v128db, 3, 0>;1838 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag,1839 v64g, v64db, 3, 8>;1840 let Predicates = [FeatureVectorEnhancements1] in {1841 defm VFCHSB : BinaryVRRcSPair<"vfchsb", 0xE7EB, z_any_vfcmph, z_vfcmphs,1842 v128f, v128sb, 2, 0>;1843 defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag,1844 v32f, v32sb, 2, 8>;1845 defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag,1846 v128q, v128xb, 4, 8>;1847 }1848 }1849 1850 // Compare and signal high.1851 let Uses = [FPC], mayRaiseFPException = 1,1852 Predicates = [FeatureVectorEnhancements1] in {1853 defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, z_strict_vfcmphs, null_frag,1854 v128g, v128db, 3, 4>;1855 defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag,1856 v64g, v64db, 3, 12>;1857 defm VFKHSB : BinaryVRRcSPair<"vfkhsb", 0xE7EB, z_strict_vfcmphs, null_frag,1858 v128f, v128sb, 2, 4>;1859 defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag,1860 v32f, v32sb, 2, 12>;1861 defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag,1862 v128q, v128xb, 4, 12>;1863 }1864 1865 // Compare high or equal.1866 let Uses = [FPC], mayRaiseFPException = 1 in {1867 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>;1868 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_any_vfcmphe, z_vfcmphes,1869 v128g, v128db, 3, 0>;1870 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag,1871 v64g, v64db, 3, 8>;1872 let Predicates = [FeatureVectorEnhancements1] in {1873 defm VFCHESB : BinaryVRRcSPair<"vfchesb", 0xE7EA, z_any_vfcmphe, z_vfcmphes,1874 v128f, v128sb, 2, 0>;1875 defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag,1876 v32f, v32sb, 2, 8>;1877 defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag,1878 v128q, v128xb, 4, 8>;1879 }1880 }1881 1882 // Compare and signal high or equal.1883 let Uses = [FPC], mayRaiseFPException = 1,1884 Predicates = [FeatureVectorEnhancements1] in {1885 defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, z_strict_vfcmphes, null_frag,1886 v128g, v128db, 3, 4>;1887 defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag,1888 v64g, v64db, 3, 12>;1889 defm VFKHESB : BinaryVRRcSPair<"vfkhesb", 0xE7EA, z_strict_vfcmphes, null_frag,1890 v128f, v128sb, 2, 4>;1891 defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag,1892 v32f, v32sb, 2, 12>;1893 defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag,1894 v128q, v128xb, 4, 12>;1895 }1896}1897 1898//===----------------------------------------------------------------------===//1899// Support for 128-bit integer values in vector registers1900//===----------------------------------------------------------------------===//1901 1902// Loads and stores.1903let Predicates = [FeatureVector] in {1904 def : Pat<(i128 (load bdxaddr12only:$addr)),1905 (VL bdxaddr12only:$addr)>;1906 def : Pat<(store (i128 VR128:$src), bdxaddr12only:$addr),1907 (VST VR128:$src, bdxaddr12only:$addr)>;1908}1909 1910// Full i128 move from GPR pair.1911let Predicates = [FeatureVector] in1912 def : Pat<(i128 (or (zext GR64:$x), (shl (anyext GR64:$y), (i32 64)))),1913 (VLVGP GR64:$y, GR64:$x)>;1914 1915// Any-extensions from GPR to i128.1916let Predicates = [FeatureVector] in {1917 def : Pat<(i128 (anyext GR32:$x)), (VLVGP32 GR32:$x, GR32:$x)>;1918 def : Pat<(i128 (anyext GR64:$x)), (VLVGP GR64:$x, GR64:$x)>;1919}1920 1921// Any-extending loads into i128.1922let Predicates = [FeatureVector] in {1923 def : Pat<(i128 (z_extloadi8 bdxaddr12only:$addr)),1924 (VLREPB bdxaddr12only:$addr)>;1925 def : Pat<(i128 (z_extloadi16 bdxaddr12only:$addr)),1926 (VLREPH bdxaddr12only:$addr)>;1927 def : Pat<(i128 (z_extloadi32 bdxaddr12only:$addr)),1928 (VLREPF bdxaddr12only:$addr)>;1929 def : Pat<(i128 (z_extloadi64 bdxaddr12only:$addr)),1930 (VLREPG bdxaddr12only:$addr)>;1931}1932 1933// Truncations from i128 to GPR.1934let Predicates = [FeatureVector] in {1935 def : Pat<(i32 (trunc (i128 VR128:$vec))),1936 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 3), subreg_l32)>;1937 def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 32)))),1938 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 2), subreg_l32)>;1939 def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 64)))),1940 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 1), subreg_l32)>;1941 def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 96)))),1942 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 0), subreg_l32)>;1943 def : Pat<(i64 (trunc (i128 VR128:$vec))),1944 (VLGVG VR128:$vec, zero_reg, 1)>;1945 def : Pat<(i64 (trunc (srl (i128 VR128:$vec), (i32 64)))),1946 (VLGVG VR128:$vec, zero_reg, 0)>;1947}1948 1949// Truncating stores from i128.1950let Predicates = [FeatureVector] in {1951 def : Pat<(truncstorei8 (i128 VR128:$x), bdxaddr12only:$addr),1952 (VSTEB VR128:$x, bdxaddr12only:$addr, 15)>;1953 def : Pat<(truncstorei16 (i128 VR128:$x), bdxaddr12only:$addr),1954 (VSTEH VR128:$x, bdxaddr12only:$addr, 7)>;1955 def : Pat<(truncstorei32 (i128 VR128:$x), bdxaddr12only:$addr),1956 (VSTEF VR128:$x, bdxaddr12only:$addr, 3)>;1957 def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 32)), bdxaddr12only:$addr),1958 (VSTEF VR128:$x, bdxaddr12only:$addr, 2)>;1959 def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 64)), bdxaddr12only:$addr),1960 (VSTEF VR128:$x, bdxaddr12only:$addr, 1)>;1961 def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 96)), bdxaddr12only:$addr),1962 (VSTEF VR128:$x, bdxaddr12only:$addr, 0)>;1963 def : Pat<(truncstorei64 (i128 VR128:$x), bdxaddr12only:$addr),1964 (VSTEG VR128:$x, bdxaddr12only:$addr, 1)>;1965 def : Pat<(truncstorei64 (srl (i128 VR128:$x), (i32 64)), bdxaddr12only:$addr),1966 (VSTEG VR128:$x, bdxaddr12only:$addr, 0)>;1967}1968 1969// Zero-extensions from GPR to i128.1970let Predicates = [FeatureVector] in {1971 def : Pat<(i128 (zext8 (anyext GR32:$x))),1972 (VLVGB (VGBM 0), GR32:$x, zero_reg, 15)>;1973 def : Pat<(i128 (zext16 (anyext GR32:$x))),1974 (VLVGH (VGBM 0), GR32:$x, zero_reg, 7)>;1975 def : Pat<(i128 (zext GR32:$x)),1976 (VLVGF (VGBM 0), GR32:$x, zero_reg, 3)>;1977 def : Pat<(i128 (zext GR64:$x)),1978 (VLVGG (VGBM 0), GR64:$x, zero_reg, 1)>;1979}1980 1981// Zero-extending loads into i128.1982let Predicates = [FeatureVector] in {1983 def : Pat<(i128 (z_zextloadi8 bdxaddr12only:$addr)),1984 (VLEB (VGBM 0), bdxaddr12only:$addr, 15)>;1985 def : Pat<(i128 (z_zextloadi16 bdxaddr12only:$addr)),1986 (VLEH (VGBM 0), bdxaddr12only:$addr, 7)>;1987 def : Pat<(i128 (z_zextloadi32 bdxaddr12only:$addr)),1988 (VLEF (VGBM 0), bdxaddr12only:$addr, 3)>;1989 def : Pat<(i128 (z_zextloadi64 bdxaddr12only:$addr)),1990 (VLEG (VGBM 0), bdxaddr12only:$addr, 1)>;1991}1992 1993// Zero-extensions from VR element to i128 on z17.1994let Predicates = [FeatureVectorEnhancements3] in {1995 def : Pat<(i128 (zext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),1996 (VUPLHG VR128:$src)>;1997 def : Pat<(i128 (zext (i64 (z_vector_extract (v2i64 VR128:$src), 1)))),1998 (VUPLLG VR128:$src)>;1999 def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 0)))),2000 (VUPLHG (VUPLHF VR128:$src))>;2001 def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 1)))),2002 (VUPLHG (VUPLLF VR128:$src))>;2003 def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 2)))),2004 (VUPLLG (VUPLHF VR128:$src))>;2005 def : Pat<(i128 (zext (i32 (z_vector_extract (v4i32 VR128:$src), 3)))),2006 (VUPLLG (VUPLLF VR128:$src))>;2007}2008 2009// In-register i128 sign-extensions on z17.2010let Predicates = [FeatureVectorEnhancements3] in {2011 def : Pat<(i128 (sext_inreg VR128:$x, i8)), (VUPLG (VSEGB VR128:$x))>;2012 def : Pat<(i128 (sext_inreg VR128:$x, i16)), (VUPLG (VSEGH VR128:$x))>;2013 def : Pat<(i128 (sext_inreg VR128:$x, i32)), (VUPLG (VSEGF VR128:$x))>;2014 def : Pat<(i128 (sext_inreg VR128:$x, i64)), (VUPLG VR128:$x)>;2015}2016 2017// In-register i128 sign-extensions.2018let Predicates = [FeatureVector] in {2019 def : Pat<(i128 (sext_inreg VR128:$x, i8)),2020 (VSRAB (VREPB VR128:$x, 15), (VREPIB 120))>;2021 def : Pat<(i128 (sext_inreg VR128:$x, i16)),2022 (VSRAB (VREPH VR128:$x, 7), (VREPIB 112))>;2023 def : Pat<(i128 (sext_inreg VR128:$x, i32)),2024 (VSRAB (VREPF VR128:$x, 3), (VREPIB 96))>;2025 def : Pat<(i128 (sext_inreg VR128:$x, i64)),2026 (VSRAB (VREPG VR128:$x, 1), (VREPIB 64))>;2027}2028 2029// Sign-extensions from GPR to i128 on z17.2030let Predicates = [FeatureVectorEnhancements3] in {2031 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)),2032 (VUPLG (VLVGP (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)),2033 (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32))))>;2034 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i16)),2035 (VUPLG (VLVGP (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)),2036 (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32))))>;2037 def : Pat<(i128 (sext GR32:$x)),2038 (VUPLG (VLVGP (LGFR GR32:$x), (LGFR GR32:$x)))>;2039 def : Pat<(i128 (sext GR64:$x)),2040 (VUPLG (VLVGP GR64:$x, GR64:$x))>;2041}2042 2043// Sign-extensions from GPR to i128.2044let Predicates = [FeatureVector] in {2045 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)),2046 (VLVGP (SRAG (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),2047 GR32:$x, subreg_l32)), zero_reg, 63),2048 (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),2049 GR32:$x, subreg_l32)))>;2050 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i16)),2051 (VLVGP (SRAG (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),2052 GR32:$x, subreg_l32)), zero_reg, 63),2053 (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)),2054 GR32:$x, subreg_l32)))>;2055 def : Pat<(i128 (sext GR32:$x)),2056 (VLVGP (SRAG (LGFR GR32:$x), zero_reg, 63), (LGFR GR32:$x))>;2057 def : Pat<(i128 (sext GR64:$x)),2058 (VLVGP (SRAG GR64:$x, zero_reg, 63), GR64:$x)>;2059}2060 2061// Sign-extending loads into i128.2062let Predicates = [FeatureVector] in {2063 def : Pat<(i128 (z_sextloadi8 bdxaddr12only:$addr)),2064 (VSRAB (VLREPB bdxaddr12only:$addr), (VREPIB 120))>;2065 def : Pat<(i128 (z_sextloadi16 bdxaddr12only:$addr)),2066 (VSRAB (VLREPH bdxaddr12only:$addr), (VREPIB 112))>;2067 def : Pat<(i128 (z_sextloadi32 bdxaddr12only:$addr)),2068 (VSRAB (VLREPF bdxaddr12only:$addr), (VREPIB 96))>;2069 def : Pat<(i128 (z_sextloadi64 bdxaddr12only:$addr)),2070 (VSRAB (VLREPG bdxaddr12only:$addr), (VREPIB 64))>;2071}2072 2073// Sign-extensions from VR element to i128 on z17.2074let Predicates = [FeatureVectorEnhancements3] in {2075 def : Pat<(i128 (sext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),2076 (VUPHG VR128:$src)>;2077 def : Pat<(i128 (sext (i64 (z_vector_extract (v2i64 VR128:$src), 1)))),2078 (VUPLG VR128:$src)>;2079 def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 0)))),2080 (VUPHG (VUPHF VR128:$src))>;2081 def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 1)))),2082 (VUPHG (VUPLF VR128:$src))>;2083 def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 2)))),2084 (VUPLG (VUPHF VR128:$src))>;2085 def : Pat<(i128 (sext (i32 (z_vector_extract (v4i32 VR128:$src), 3)))),2086 (VUPLG (VUPLF VR128:$src))>;2087}2088 2089// i128 comparison pseudo-instructions.2090let Predicates = [FeatureVector], Defs = [CC],2091 usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {2092 def SCmp128Hi : Pseudo<(outs), (ins VR128:$src1, VR128:$src2),2093 [(set CC, (z_scmp128hi (i128 VR128:$src1),2094 (i128 VR128:$src2)))]>;2095 def UCmp128Hi : Pseudo<(outs), (ins VR128:$src1, VR128:$src2),2096 [(set CC, (z_ucmp128hi (i128 VR128:$src1),2097 (i128 VR128:$src2)))]>;2098}2099 2100// i128 select pseudo-instructions.2101let Predicates = [FeatureVector] in2102 def Select128 : SelectWrapper<i128, VR128>;2103 2104//===----------------------------------------------------------------------===//2105// Conversions2106//===----------------------------------------------------------------------===//2107 2108let Predicates = [FeatureVector] in {2109def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;2110def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;2111def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;2112def : Pat<(v16i8 (bitconvert (i128 VR128:$src))), (v16i8 VR128:$src)>;2113def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;2114def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;2115def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>;2116 2117def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;2118def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;2119def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;2120def : Pat<(v8i16 (bitconvert (i128 VR128:$src))), (v8i16 VR128:$src)>;2121def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;2122def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;2123def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>;2124 2125def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;2126def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;2127def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;2128def : Pat<(v4i32 (bitconvert (i128 VR128:$src))), (v4i32 VR128:$src)>;2129def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;2130def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;2131def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>;2132 2133def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;2134def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;2135def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;2136def : Pat<(v2i64 (bitconvert (i128 VR128:$src))), (v2i64 VR128:$src)>;2137def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;2138def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;2139def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>;2140 2141def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;2142def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;2143def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;2144def : Pat<(v4f32 (bitconvert (i128 VR128:$src))), (v4f32 VR128:$src)>;2145def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;2146def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;2147def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>;2148 2149def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;2150def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;2151def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;2152def : Pat<(v2f64 (bitconvert (i128 VR128:$src))), (v2f64 VR128:$src)>;2153def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;2154def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;2155def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>;2156 2157def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>;2158def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>;2159def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>;2160def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>;2161def : Pat<(f128 (bitconvert (i128 VR128:$src))), (f128 VR128:$src)>;2162def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>;2163def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>;2164 2165def : Pat<(i128 (bitconvert (v16i8 VR128:$src))), (i128 VR128:$src)>;2166def : Pat<(i128 (bitconvert (v8i16 VR128:$src))), (i128 VR128:$src)>;2167def : Pat<(i128 (bitconvert (v4i32 VR128:$src))), (i128 VR128:$src)>;2168def : Pat<(i128 (bitconvert (v2i64 VR128:$src))), (i128 VR128:$src)>;2169def : Pat<(i128 (bitconvert (v4f32 VR128:$src))), (i128 VR128:$src)>;2170def : Pat<(i128 (bitconvert (v2f64 VR128:$src))), (i128 VR128:$src)>;2171def : Pat<(i128 (bitconvert (f128 VR128:$src))), (i128 VR128:$src)>;2172} // End Predicates = [FeatureVector]2173 2174//===----------------------------------------------------------------------===//2175// Replicating scalars2176//===----------------------------------------------------------------------===//2177 2178// Define patterns for replicating a scalar GR32 into a vector of type TYPE.2179// INDEX is 8 minus the element size in bytes.2180class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index>2181 : Pat<(type (z_replicate GR32:$scalar)),2182 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>;2183 2184def : VectorReplicateScalar<v16i8, VREPB, 7>;2185def : VectorReplicateScalar<v8i16, VREPH, 3>;2186def : VectorReplicateScalar<v4i32, VREPF, 1>;2187 2188// i64 replications are just a single instruction.2189def : Pat<(v2i64 (z_replicate GR64:$scalar)),2190 (VLVGP GR64:$scalar, GR64:$scalar)>;2191 2192//===----------------------------------------------------------------------===//2193// Floating-point insertion and extraction2194//===----------------------------------------------------------------------===//2195 2196// Moving 32-bit values between GPRs and FPRs can be done using VLVGF2197// and VLGVF.2198let Predicates = [FeatureVector] in {2199 def LEFR : UnaryAliasVRS<VR32, GR32>;2200 def LFER : UnaryAliasVRS<GR64, VR32>;2201 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>;2202 def : Pat<(i32 (bitconvert (f32 VR32:$src))),2203 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>;2204 def LEFR_16 : UnaryAliasVRS<VR16, GR32>;2205 def LFER_16 : UnaryAliasVRS<GR32, VR16>;2206}2207 2208// Floating-point values are stored in element 0 of the corresponding2209// vector register. Scalar to vector conversion is just a subreg and2210// scalar replication can just replicate element 0 of the vector register.2211multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls,2212 SubRegIndex subreg> {2213 def : Pat<(vt (scalar_to_vector cls:$scalar)),2214 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>;2215 def : Pat<(vt (z_replicate cls:$scalar)),2216 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar,2217 subreg), 0)>;2218}2219defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_h32>;2220defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>;2221 2222// Match v2f64 insertions. The AddedComplexity counters the 3 added by2223// TableGen for the base register operand in VLVG-based integer insertions2224// and ensures that this version is strictly better.2225let AddedComplexity = 4 in {2226 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),2227 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,2228 subreg_h64), VR128:$vec, 1)>;2229 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),2230 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,2231 subreg_h64), 0)>;2232}2233 2234// We extract floating-point element X by replicating (for elements other2235// than 0) and then taking a high subreg. The AddedComplexity counters the2236// 3 added by TableGen for the base register operand in VLGV-based integer2237// extractions and ensures that this version is strictly better.2238let AddedComplexity = 4 in {2239 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)),2240 (EXTRACT_SUBREG VR128:$vec, subreg_h32)>;2241 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)),2242 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_h32)>;2243 2244 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)),2245 (EXTRACT_SUBREG VR128:$vec, subreg_h64)>;2246 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)),2247 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_h64)>;2248}2249 2250//===----------------------------------------------------------------------===//2251// Support for 128-bit floating-point values in vector registers2252//===----------------------------------------------------------------------===//2253 2254let Predicates = [FeatureVectorEnhancements1] in {2255 def : Pat<(f128 (load bdxaddr12only:$addr)),2256 (VL bdxaddr12only:$addr)>;2257 def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr),2258 (VST VR128:$src, bdxaddr12only:$addr)>;2259 2260 def : Pat<(f128 fpimm0), (VZERO)>;2261 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>;2262}2263 2264//===----------------------------------------------------------------------===//2265// String instructions2266//===----------------------------------------------------------------------===//2267 2268let Predicates = [FeatureVector] in {2269 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>;2270 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb,2271 z_vfae_cc, v128b, v128b, 0>;2272 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh,2273 z_vfae_cc, v128h, v128h, 1>;2274 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef,2275 z_vfae_cc, v128f, v128f, 2>;2276 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb,2277 z_vfaez_cc, v128b, v128b, 0, 2>;2278 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh,2279 z_vfaez_cc, v128h, v128h, 1, 2>;2280 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf,2281 z_vfaez_cc, v128f, v128f, 2, 2>;2282 2283 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>;2284 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb,2285 z_vfee_cc, v128b, v128b, 0>;2286 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh,2287 z_vfee_cc, v128h, v128h, 1>;2288 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef,2289 z_vfee_cc, v128f, v128f, 2>;2290 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb,2291 z_vfeez_cc, v128b, v128b, 0, 2>;2292 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh,2293 z_vfeez_cc, v128h, v128h, 1, 2>;2294 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf,2295 z_vfeez_cc, v128f, v128f, 2, 2>;2296 2297 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>;2298 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb,2299 z_vfene_cc, v128b, v128b, 0>;2300 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh,2301 z_vfene_cc, v128h, v128h, 1>;2302 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef,2303 z_vfene_cc, v128f, v128f, 2>;2304 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb,2305 z_vfenez_cc, v128b, v128b, 0, 2>;2306 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh,2307 z_vfenez_cc, v128h, v128h, 1, 2>;2308 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf,2309 z_vfenez_cc, v128f, v128f, 2, 2>;2310 2311 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>;2312 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb,2313 z_vistr_cc, v128b, v128b, 0>;2314 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh,2315 z_vistr_cc, v128h, v128h, 1>;2316 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf,2317 z_vistr_cc, v128f, v128f, 2>;2318 2319 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>;2320 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb,2321 z_vstrc_cc, v128b, v128b, 0>;2322 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch,2323 z_vstrc_cc, v128h, v128h, 1>;2324 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf,2325 z_vstrc_cc, v128f, v128f, 2>;2326 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb,2327 z_vstrcz_cc, v128b, v128b, 0, 2>;2328 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh,2329 z_vstrcz_cc, v128h, v128h, 1, 2>;2330 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf,2331 z_vstrcz_cc, v128f, v128f, 2, 2>;2332}2333 2334let Predicates = [FeatureVectorEnhancements2] in {2335 defm VSTRS : TernaryExtraVRRdGeneric<"vstrs", 0xE78B>;2336 defm VSTRSB : TernaryExtraVRRd<"vstrsb", 0xE78B,2337 z_vstrs_cc, v128b, v128b, 0>;2338 defm VSTRSH : TernaryExtraVRRd<"vstrsh", 0xE78B,2339 z_vstrs_cc, v128b, v128h, 1>;2340 defm VSTRSF : TernaryExtraVRRd<"vstrsf", 0xE78B,2341 z_vstrs_cc, v128b, v128f, 2>;2342 let Defs = [CC] in {2343 def VSTRSZB : TernaryVRRd<"vstrszb", 0xE78B,2344 z_vstrsz_cc, v128b, v128b, 0, 2>;2345 def VSTRSZH : TernaryVRRd<"vstrszh", 0xE78B,2346 z_vstrsz_cc, v128b, v128h, 1, 2>;2347 def VSTRSZF : TernaryVRRd<"vstrszf", 0xE78B,2348 z_vstrsz_cc, v128b, v128f, 2, 2>;2349 }2350}2351 2352//===----------------------------------------------------------------------===//2353// NNP assist instructions2354//===----------------------------------------------------------------------===//2355 2356let Predicates = [FeatureVector, FeatureNNPAssist] in {2357 let Uses = [FPC], mayRaiseFPException = 1 in2358 def VCFN : UnaryVRRaFloatGeneric<"vcfn", 0xE65D>;2359 def : Pat<(int_s390_vcfn VR128:$x, imm32zx4_timm:$m),2360 (VCFN VR128:$x, 1, imm32zx4:$m)>;2361 2362 let Uses = [FPC], mayRaiseFPException = 1 in2363 def VCLFNL : UnaryVRRaFloatGeneric<"vclfnl", 0xE65E>;2364 def : Pat<(int_s390_vclfnls VR128:$x, imm32zx4_timm:$m),2365 (VCLFNL VR128:$x, 2, imm32zx4:$m)>;2366 2367 let Uses = [FPC], mayRaiseFPException = 1 in2368 def VCLFNH : UnaryVRRaFloatGeneric<"vclfnh", 0xE656>;2369 def : Pat<(int_s390_vclfnhs VR128:$x, imm32zx4_timm:$m),2370 (VCLFNH VR128:$x, 2, imm32zx4:$m)>;2371 2372 let Uses = [FPC], mayRaiseFPException = 1 in2373 def VCNF : UnaryVRRaFloatGeneric<"vcnf", 0xE655>;2374 def : Pat<(int_s390_vcnf VR128:$x, imm32zx4_timm:$m),2375 (VCNF VR128:$x, imm32zx4:$m, 1)>;2376 2377 let Uses = [FPC], mayRaiseFPException = 1 in2378 def VCRNF : BinaryVRRcFloatGeneric<"vcrnf", 0xE675>;2379 def : Pat<(int_s390_vcrnfs VR128:$x, VR128:$y, imm32zx4_timm:$m),2380 (VCRNF VR128:$x, VR128:$y, imm32zx4:$m, 2)>;2381}2382 2383//===----------------------------------------------------------------------===//2384// Packed-decimal instructions2385//===----------------------------------------------------------------------===//2386 2387let Predicates = [FeatureVectorPackedDecimal] in {2388 def VLIP : BinaryVRIh<"vlip", 0xE649>;2389 2390 def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>;2391 def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>;2392 2393 let Defs = [CC] in {2394 let Predicates = [FeatureVectorPackedDecimalEnhancement] in {2395 def VCVBOpt : TernaryVRRi<"vcvb", 0xE650, GR32>;2396 def VCVBGOpt : TernaryVRRi<"vcvbg", 0xE652, GR64>;2397 }2398 def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>;2399 def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>;2400 def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>;2401 def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>;2402 2403 def VAP : QuaternaryVRIf<"vap", 0xE671>;2404 def VSP : QuaternaryVRIf<"vsp", 0xE673>;2405 2406 def VMP : QuaternaryVRIf<"vmp", 0xE678>;2407 def VMSP : QuaternaryVRIf<"vmsp", 0xE679>;2408 2409 def VDP : QuaternaryVRIf<"vdp", 0xE67A>;2410 def VRP : QuaternaryVRIf<"vrp", 0xE67B>;2411 def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>;2412 2413 def VSRP : QuaternaryVRIg<"vsrp", 0xE659>;2414 def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>;2415 2416 def VTP : TestVRRg<"vtp", 0xE65F>;2417 def VCP : CompareVRRh<"vcp", 0xE677>;2418 }2419}2420 2421let Predicates = [FeatureVectorPackedDecimalEnhancement2] in {2422 def VSCHP : BinaryExtraVRRbGeneric<"vschp", 0xE674>;2423 def VSCHSP : BinaryExtraVRRb<"vschsp", 0xE674, 2>;2424 def VSCHDP : BinaryExtraVRRb<"vschdp", 0xE674, 3>;2425 def VSCHXP : BinaryExtraVRRb<"vschxp", 0xE674, 4>;2426 2427 def VSCSHP : BinaryVRRb<"vscshp", 0xE67C, null_frag, v128b, v128b>;2428 2429 def VCSPH : TernaryVRRj<"vcsph", 0xE67D>;2430 2431 let Defs = [CC] in2432 def VCLZDP : BinaryVRRk<"vclzdp", 0xE651>;2433 2434 let Defs = [CC] in2435 def VSRPR : QuaternaryVRIf<"vsrpr", 0xE672>;2436 2437 let Defs = [CC] in {2438 def VPKZR : QuaternaryVRIf<"vpkzr", 0xE670>;2439 def VUPKZH : BinaryVRRk<"vupkzh", 0xE654>;2440 def VUPKZL : BinaryVRRk<"vupkzl", 0xE65C>;2441 }2442}2443 2444let Predicates = [FeatureVectorPackedDecimalEnhancement3] in {2445 def VCVBQ : BinaryVRRk<"vcvbq", 0xE64E>;2446 let Defs = [CC] in2447 def VCVDQ : TernaryVRIj<"vcvdq", 0xE64A>;2448 2449 let Defs = [CC] in {2450 def VTPOpt : TestExtraVRRg<"vtp", 0xE65F>;2451 def VTZ : TestExtraVRIl<"vtz", 0xE67F>;2452 }2453}2454