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1//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Class definitions.11//===----------------------------------------------------------------------===//12 13class SystemZReg<string n> : Register<n> {14 let Namespace = "SystemZ";15}16 17class SystemZRegWithSubregs<string n, list<Register> subregs>18 : RegisterWithSubRegs<n, subregs> {19 let Namespace = "SystemZ";20}21 22let Namespace = "SystemZ" in {23def subreg_h16 : SubRegIndex<16, 16>;24def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_hl32.25def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_hh32.26def subreg_l64 : SubRegIndex<64, 0>;27def subreg_h64 : SubRegIndex<64, 64>;28def subreg_lh32 : ComposedSubRegIndex<subreg_l64, subreg_h32>;29def subreg_ll32 : ComposedSubRegIndex<subreg_l64, subreg_l32>;30}31 32// Define a register class that contains values of types TYPES and an33// associated operand called NAME. SIZE is the size and alignment34// of the registers and REGLIST is the list of individual registers.35// If the user provides an alternate order list of regs, it will be used for36// XPLINK. Otherwise, by default, XPLINK will use the regList ordering as well37multiclass SystemZRegClass<string name, list<ValueType> types, int size,38 dag regList, list<dag> altRegList = [regList],39 bit allocatable = 1,40 RegInfoByHwMode RI = RegInfoByHwMode<[], []>> {41 def AsmOperand : AsmOperandClass {42 let Name = name;43 let ParserMethod = "parse"#name;44 let RenderMethod = "addRegOperands";45 }46 let isAllocatable = allocatable in47 def Bit : RegisterClass<"SystemZ", types, size, regList> {48 let Size = size;49 let AltOrders = altRegList;50 let AltOrderSelect = [{51 const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();52 return S.isTargetXPLINK64();53 }];54 let RegInfos = RI;55 }56 def "" : RegisterOperand<!cast<RegisterClass>(name#"Bit")> {57 let ParserMatchClass = !cast<AsmOperandClass>(name#"AsmOperand");58 }59}60 61//===----------------------------------------------------------------------===//62// General-purpose registers63//===----------------------------------------------------------------------===//64 65// Lower 32 bits of one of the 16 64-bit general-purpose registers66class GPR32<bits<16> num, string n> : SystemZReg<n> {67 let HWEncoding = num;68}69 70// One of the 16 64-bit general-purpose registers.71class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>72 : SystemZRegWithSubregs<n, [low, high]> {73 let HWEncoding = num;74 let SubRegIndices = [subreg_l32, subreg_h32];75 let CoveredBySubRegs = 1;76}77 78// 8 even-odd pairs of GPR64s.79class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>80 : SystemZRegWithSubregs<n, [high, low]> {81 let HWEncoding = num;82 let SubRegIndices = [subreg_h64, subreg_l64];83 let CoveredBySubRegs = 1;84}85 86// General-purpose registers87foreach I = 0-15 in {88 def R#I#L : GPR32<I, "r"#I>;89 def R#I#H : GPR32<I, "r"#I>;90 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,91 DwarfRegNum<[I]>;92}93 94foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {95 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),96 !cast<GPR64>("R"#I#"D")>;97}98 99/// zLinux: Allocate the callee-saved R6-R13 backwards. That way they can be100/// saved together with R14 and R15 in one prolog instruction.101/// XPLINK64: Allocate all registers in natural order102defm GR32 : SystemZRegClass<"GR32", [i32], 32,103 (add (sequence "R%uL", 0, 5),104 (sequence "R%uL", 15, 6)),105 [(add (sequence "R%uL", 0, 15))]>;106defm GRH32 : SystemZRegClass<"GRH32", [i32], 32,107 (add (sequence "R%uH", 0, 5),108 (sequence "R%uH", 15, 6)),109 [(add (sequence "R%uH", 0, 15))]>;110defm GR64 : SystemZRegClass<"GR64", [i64], 64,111 (add (sequence "R%uD", 0, 5),112 (sequence "R%uD", 15, 6)),113 [(add (sequence "R%uD", 0, 15))]>;114 115// Combine the low and high GR32s into a single class. This can only be116// used for virtual registers if the high-word facility is available.117/// XPLINK64: Allocate all registers in natural order118defm GRX32 : SystemZRegClass<"GRX32", [i32], 32,119 (add (sequence "R%uL", 0, 5),120 (sequence "R%uH", 0, 5),121 R15L, R15H, R14L, R14H, R13L, R13H,122 R12L, R12H, R11L, R11H, R10L, R10H,123 R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H),124 [(add125 R0L, R1L, R2L, R3L, R0H, R1H, R2H, R3H,126 R4L, R4H, R5L, R5H, R6L, R6H, R7L, R7H,127 R8L, R8H, R9L, R9H, R10L,R10H,R11L,R11H,128 R12L,R12H,R13L,R13H,R14L,R14H,R15L,R15H)129 ]>;130 131// On machines without SIMD support, i128 is not a legal type, so model the132// register pairs as untyped instead.133// XPLINK64: Allocate all registers in natural order134defm GR128 : SystemZRegClass<"GR128", [untyped], 128,135 (add R0Q, R2Q, R4Q, R12Q, R10Q, R8Q, R6Q, R14Q),136 [(add R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q)]>;137 138// Base and index registers. Everything except R0, which in an address139// context evaluates as 0.140// XPLINK64: Allocate all registers in natural order141defm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L),142 [(add (sequence "R%uL", 1, 15))]>;143defm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D),144 [(add (sequence "R%uD", 1, 15))]>;145 146// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs147// of a GR128.148// XPLINK64: Allocate all registers in natural order149defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q),150 [(add R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q)]>;151 152// Any type register. Used for .insn directives when we don't know what the153// register types could be.154defm AnyReg : SystemZRegClass<"AnyReg",155 [i64, f64, v8i8, v4i16, v2i32, v2f32], 64,156 (add (sequence "R%uD", 0, 15),157 (sequence "F%uD", 0, 15),158 (sequence "V%u", 0, 15)),159 [], 0/*allocatable*/>;160 161//===----------------------------------------------------------------------===//162// Floating-point registers163//===----------------------------------------------------------------------===//164 165// Maps FPR register numbers to their DWARF encoding.166class DwarfMapping<int id> { int Id = id; }167 168def F0Dwarf : DwarfMapping<16>;169def F2Dwarf : DwarfMapping<17>;170def F4Dwarf : DwarfMapping<18>;171def F6Dwarf : DwarfMapping<19>;172 173def F1Dwarf : DwarfMapping<20>;174def F3Dwarf : DwarfMapping<21>;175def F5Dwarf : DwarfMapping<22>;176def F7Dwarf : DwarfMapping<23>;177 178def F8Dwarf : DwarfMapping<24>;179def F10Dwarf : DwarfMapping<25>;180def F12Dwarf : DwarfMapping<26>;181def F14Dwarf : DwarfMapping<27>;182 183def F9Dwarf : DwarfMapping<28>;184def F11Dwarf : DwarfMapping<29>;185def F13Dwarf : DwarfMapping<30>;186def F15Dwarf : DwarfMapping<31>;187 188def F16Dwarf : DwarfMapping<68>;189def F18Dwarf : DwarfMapping<69>;190def F20Dwarf : DwarfMapping<70>;191def F22Dwarf : DwarfMapping<71>;192 193def F17Dwarf : DwarfMapping<72>;194def F19Dwarf : DwarfMapping<73>;195def F21Dwarf : DwarfMapping<74>;196def F23Dwarf : DwarfMapping<75>;197 198def F24Dwarf : DwarfMapping<76>;199def F26Dwarf : DwarfMapping<77>;200def F28Dwarf : DwarfMapping<78>;201def F30Dwarf : DwarfMapping<79>;202 203def F25Dwarf : DwarfMapping<80>;204def F27Dwarf : DwarfMapping<81>;205def F29Dwarf : DwarfMapping<82>;206def F31Dwarf : DwarfMapping<83>;207 208// Upper 16 bits of one of the floating-point registers209class FPR16<bits<16> num, string n> : SystemZReg<n> {210 let HWEncoding = num;211}212 213// Upper 32 bits of one of the floating-point registers214class FPR32<bits<16> num, string n, FPR16 high>215 : SystemZRegWithSubregs<n, [high]> {216 let HWEncoding = num;217 let SubRegIndices = [subreg_h16];218}219 220// One of the floating-point registers.221class FPR64<bits<16> num, string n, FPR32 high>222 : SystemZRegWithSubregs<n, [high]> {223 let HWEncoding = num;224 let SubRegIndices = [subreg_h32];225}226 227// 8 pairs of FPR64s, with a one-register gap inbetween.228class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>229 : SystemZRegWithSubregs<n, [high, low]> {230 let HWEncoding = num;231 let SubRegIndices = [subreg_h64, subreg_l64];232 let CoveredBySubRegs = 1;233}234 235// Floating-point registers. Registers 16-31 require the vector facility.236foreach I = 0-15 in {237 def F#I#H : FPR16<I, "f"#I>;238 def F#I#S : FPR32<I, "f"#I, !cast<FPR16>("F"#I#"H")>;239 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,240 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;241}242foreach I = 16-31 in {243 def F#I#H : FPR16<I, "v"#I>;244 def F#I#S : FPR32<I, "v"#I, !cast<FPR16>("F"#I#"H")>;245 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,246 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;247}248 249foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {250 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),251 !cast<FPR64>("F"#I#"D")>;252}253 254// There's no store-multiple instruction for FPRs, so we're not fussy255// about the order in which call-saved registers are allocated.256// Adjust the spill size of f16 to 32 bits in case of no vector support.257def FP16RI : RegInfoByHwMode<[DefaultMode, NoVecHwMode],258 [RegInfo<16,16,16>, RegInfo<16,32,32>]>;259defm FP16 : SystemZRegClass<"FP16", [f16], 16, (sequence "F%uH", 0, 15),260 [(sequence "F%uH", 0, 15)], 1, FP16RI>;261defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>;262defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;263defm FP128 : SystemZRegClass<"FP128", [f128], 128,264 (add F0Q, F1Q, F4Q, F5Q, F8Q, F9Q, F12Q, F13Q)>;265 266//===----------------------------------------------------------------------===//267// Vector registers268//===----------------------------------------------------------------------===//269 270// A full 128-bit vector register, with an FPR64 as its high part.271class VR128<bits<16> num, string n, FPR64 high>272 : SystemZRegWithSubregs<n, [high]> {273 let HWEncoding = num;274 let SubRegIndices = [subreg_h64];275}276 277// Full vector registers.278foreach I = 0-31 in {279 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,280 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;281}282 283// Class used to store 16-bit fp values in the first element of a vector284// register.285defm VR16 : SystemZRegClass<"VR16", [f16], 16,286 (add (sequence "F%uH", 0, 7),287 (sequence "F%uH", 16, 31),288 (sequence "F%uH", 8, 15))>;289 290// Class used to store 32-bit values in the first element of a vector291// register. f32 scalars are used for the WLEDB and WLDEB instructions.292defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32,293 (add (sequence "F%uS", 0, 7),294 (sequence "F%uS", 16, 31),295 (sequence "F%uS", 8, 15))>;296 297// Class used to store 64-bit values in the upper half of a vector register.298// The vector facility also includes scalar f64 instructions that operate299// on the full vector register set.300defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,301 (add (sequence "F%uD", 0, 7),302 (sequence "F%uD", 16, 31),303 (sequence "F%uD", 8, 15))>;304 305// The subset of vector registers that can be used for floating-point306// operations too.307defm VF128 : SystemZRegClass<"VF128",308 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,309 (sequence "V%u", 0, 15)>;310 311// All vector registers.312defm VR128 : SystemZRegClass<"VR128",313 [v16i8, v8i16, v4i32, v2i64, i128,314 v4f32, v2f64, f128],315 128, (add (sequence "V%u", 0, 7),316 (sequence "V%u", 16, 31),317 (sequence "V%u", 8, 15))>;318 319// Attaches a ValueType to a register operand, to make the instruction320// definitions easier.321class TypedReg<ValueType vtin, RegisterOperand opin> {322 ValueType vt = vtin;323 RegisterOperand op = opin;324}325 326def v16hb : TypedReg<f16, VR16>;327def v32f : TypedReg<i32, VR32>;328def v32sb : TypedReg<f32, VR32>;329def v64g : TypedReg<i64, VR64>;330def v64db : TypedReg<f64, VR64>;331def v128b : TypedReg<v16i8, VR128>;332def v128h : TypedReg<v8i16, VR128>;333def v128f : TypedReg<v4i32, VR128>;334def v128g : TypedReg<v2i64, VR128>;335def v128q : TypedReg<i128, VR128>;336def v128sb : TypedReg<v4f32, VR128>;337def v128db : TypedReg<v2f64, VR128>;338def v128xb : TypedReg<f128, VR128>;339def v128any : TypedReg<untyped, VR128>;340 341//===----------------------------------------------------------------------===//342// Other registers343//===----------------------------------------------------------------------===//344 345// The 2-bit condition code field of the PSW. Every register named in an346// inline asm needs a class associated with it.347def CC : SystemZReg<"cc">;348let isAllocatable = 0, CopyCost = -1 in349 def CCR : RegisterClass<"SystemZ", [i32], 32, (add CC)>;350 351// The floating-point control register.352// Note: We only model the current rounding modes and the IEEE masks.353// IEEE flags and DXC are not modeled here.354def FPC : SystemZReg<"fpc">;355let isAllocatable = 0 in356 def FPCRegs : RegisterClass<"SystemZ", [i32], 32, (add FPC)>;357 358// Access registers.359class ACR32<bits<16> num, string n> : SystemZReg<n> {360 let HWEncoding = num;361}362foreach I = 0-15 in {363 def A#I : ACR32<I, "a"#I>, DwarfRegNum<[!add(I, 48)]>;364}365defm AR32 : SystemZRegClass<"AR32", [i32], 32,366 (add (sequence "A%u", 0, 15)), [], 0>;367 368// Control registers.369class CREG64<bits<16> num, string n> : SystemZReg<n> {370 let HWEncoding = num;371}372foreach I = 0-15 in {373 def C#I : CREG64<I, "c"#I>, DwarfRegNum<[!add(I, 32)]>;374}375defm CR64 : SystemZRegClass<"CR64", [i64], 64,376 (add (sequence "C%u", 0, 15)), [], 0>;377