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1//=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for ZEC12 to support instruction10// scheduling and other instruction cost heuristics.11//12// Pseudos expanded right after isel do not need to be modelled here.13//14//===----------------------------------------------------------------------===//15 16def ZEC12Model : SchedMachineModel {17 18 let UnsupportedFeatures = Arch10UnsupportedFeatures.List;19 20 let IssueWidth = 3;21 let MicroOpBufferSize = 40; // Issue queues22 let LoadLatency = 1; // Optimistic load latency.23 24 let PostRAScheduler = 1;25 26 // Extra cycles for a mispredicted branch.27 let MispredictPenalty = 16;28}29 30let SchedModel = ZEC12Model in {31// These definitions need the SchedModel value. They could be put in a32// subtarget common include file, but it seems the include system in Tablegen33// currently (2016) rejects multiple includes of same file.34 35// Decoder grouping rules36let NumMicroOps = 1 in {37 def : WriteRes<NormalGr, []>;38 def : WriteRes<BeginGroup, []> { let BeginGroup = 1; }39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }40}41def : WriteRes<GroupAlone, []> {42 let NumMicroOps = 3;43 let BeginGroup = 1;44 let EndGroup = 1;45}46def : WriteRes<GroupAlone2, []> {47 let NumMicroOps = 6;48 let BeginGroup = 1;49 let EndGroup = 1;50}51def : WriteRes<GroupAlone3, []> {52 let NumMicroOps = 9;53 let BeginGroup = 1;54 let EndGroup = 1;55}56 57// Incoming latency removed from the register operand which is used together58// with a memory operand by the instruction.59def : ReadAdvance<RegReadAdv, 4>;60 61// LoadLatency (above) is not used for instructions in this file. This is62// instead the role of LSULatency, which is the latency value added to the63// result of loads and instructions with folded memory operands.64def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }65 66let NumMicroOps = 0 in {67 foreach L = 1-30 in {68 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }69 }70}71 72// Execution units.73def ZEC12_FXUnit : ProcResource<2>;74def ZEC12_LSUnit : ProcResource<2>;75def ZEC12_FPUnit : ProcResource<1>;76def ZEC12_DFUnit : ProcResource<1>;77def ZEC12_VBUnit : ProcResource<1>;78def ZEC12_MCD : ProcResource<1>;79 80// Subtarget specific definitions of scheduling resources.81let NumMicroOps = 0 in {82 def : WriteRes<FXU, [ZEC12_FXUnit]>;83 def : WriteRes<LSU, [ZEC12_LSUnit]>;84 def : WriteRes<FPU, [ZEC12_FPUnit]>;85 def : WriteRes<DFU, [ZEC12_DFUnit]>;86 foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {87 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;88 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;90 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;91 }}92 93 def : WriteRes<VBU, [ZEC12_VBUnit]>; // Virtual Branching Unit94}95 96def : WriteRes<MCD, [ZEC12_MCD]> { let NumMicroOps = 3;97 let BeginGroup = 1;98 let EndGroup = 1; }99 100// -------------------------- INSTRUCTIONS ---------------------------------- //101 102// InstRW constructs have been used in order to preserve the103// readability of the InstrInfo files.104 105// For each instruction, as matched by a regexp, provide a list of106// resources that it needs. These will be combined into a SchedClass.107 108//===----------------------------------------------------------------------===//109// Stack allocation110//===----------------------------------------------------------------------===//111 112// Pseudo -> LA / LAY113def : InstRW<[WLat1, FXU, NormalGr], (instregex "ADJDYNALLOC$")>;114 115//===----------------------------------------------------------------------===//116// Branch instructions117//===----------------------------------------------------------------------===//118 119// Branch120def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;121def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?J(G)?(Asm.*)?$")>;122def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;123def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;124def : InstRW<[WLat1, FXU, EndGroup], (instregex "BRCT(G)?$")>;125def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCTH$")>;126def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;127def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],128 (instregex "B(R)?X(H|L).*$")>;129 130// Compare and branch131def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;132def : InstRW<[WLat1, FXU, LSU, GroupAlone],133 (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;134 135//===----------------------------------------------------------------------===//136// Trap instructions137//===----------------------------------------------------------------------===//138 139// Trap140def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Cond)?Trap$")>;141 142// Compare and trap143def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(G)?(I|R)T(Asm.*)?$")>;144def : InstRW<[WLat1, FXU, NormalGr], (instregex "CL(G)?RT(Asm.*)?$")>;145def : InstRW<[WLat1, FXU, NormalGr], (instregex "CL(F|G)IT(Asm.*)?$")>;146def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;147 148//===----------------------------------------------------------------------===//149// Call and return instructions150//===----------------------------------------------------------------------===//151 152// Call153def : InstRW<[WLat1, FXU2, VBU, GroupAlone], (instregex "(Call)?BRAS$")>;154def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BRASL(_XPLINK64)?$")>;155def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BAS(R)?(_XPLINK64|_STACKEXT)?$")>;156def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;157 158// Return159def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return(_XPLINK)?$")>;160def : InstRW<[WLat1, LSU, NormalGr], (instregex "CondReturn(_XPLINK)?$")>;161 162//===----------------------------------------------------------------------===//163// Move instructions164//===----------------------------------------------------------------------===//165 166// Moves167def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;168def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "MVI(Y)?$")>;169 170// Move character171def : InstRW<[WLat1, FXU, LSU3, GroupAlone], (instregex "MVC$")>;172def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVCL(E|U)?$")>;173 174// Pseudo -> reg move175def : InstRW<[WLat1, FXU, NormalGr], (instregex "COPY(_TO_REGCLASS)?$")>;176def : InstRW<[WLat1, FXU, NormalGr], (instregex "EXTRACT_SUBREG$")>;177def : InstRW<[WLat1, FXU, NormalGr], (instregex "INSERT_SUBREG$")>;178def : InstRW<[WLat1, FXU, NormalGr], (instregex "REG_SEQUENCE$")>;179 180// Loads181def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;182def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;183def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;184 185def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIH(F|H|L)$")>;186def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIL(F|H|L)$")>;187 188def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>;189def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;190def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR$")>;191 192// Load and trap193def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "L(FH|G)?AT$")>;194 195// Load and test196def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXU, NormalGr], (instregex "LT(G)?$")>;197def : InstRW<[WLat1, FXU, NormalGr], (instregex "LT(G)?R$")>;198 199// Stores200def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;201def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST128$")>;202def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;203 204// String moves.205def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVST$")>;206 207//===----------------------------------------------------------------------===//208// Conditional move instructions209//===----------------------------------------------------------------------===//210 211def : InstRW<[WLat2, FXU, NormalGr], (instregex "LOC(G)?R(Asm.*)?$")>;212def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],213 (instregex "LOC(G)?(Asm.*)?$")>;214def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STOC(G)?(Asm.*)?$")>;215 216//===----------------------------------------------------------------------===//217// Sign extensions218//===----------------------------------------------------------------------===//219 220def : InstRW<[WLat1, FXU, NormalGr], (instregex "L(B|H|G)R$")>;221def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(B|H|F)R$")>;222 223def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LTGF$")>;224def : InstRW<[WLat1, FXU, NormalGr], (instregex "LTGFR$")>;225 226def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;227def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(Y)?$")>;228def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;229def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(B|H|F)$")>;230def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(H|F)RL$")>;231 232//===----------------------------------------------------------------------===//233// Zero extensions234//===----------------------------------------------------------------------===//235 236def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;237def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;238def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLG(C|H|F|T)R$")>;239def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;240def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;241def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LL(C|H)H$")>;242def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;243def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;244 245// Load and trap246def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LLG(F|T)?AT$")>;247 248//===----------------------------------------------------------------------===//249// Truncations250//===----------------------------------------------------------------------===//251 252def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STC(H|Y|Mux)?$")>;253def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;254def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STCM(H|Y)?$")>;255 256//===----------------------------------------------------------------------===//257// Multi-register moves258//===----------------------------------------------------------------------===//259 260// Load multiple (estimated average of 5 ops)261def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LM(H|Y|G)?$")>;262 263// Load multiple disjoint264def : InstRW<[WLat30, WLat30, MCD], (instregex "LMD$")>;265 266// Store multiple (estimated average of 3 ops)267def : InstRW<[WLat1, LSU2, FXU5, GroupAlone], (instregex "STM(H|Y|G)?$")>;268 269//===----------------------------------------------------------------------===//270// Byte swaps271//===----------------------------------------------------------------------===//272 273def : InstRW<[WLat1, FXU, NormalGr], (instregex "LRV(G)?R$")>;274def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LRV(G|H)?$")>;275def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STRV(G|H)?$")>;276def : InstRW<[WLat30, MCD], (instregex "MVCIN$")>;277 278//===----------------------------------------------------------------------===//279// Load address instructions280//===----------------------------------------------------------------------===//281 282def : InstRW<[WLat1, FXU, NormalGr], (instregex "LA(Y|RL)?$")>;283 284// Load the Global Offset Table address285def : InstRW<[WLat1, FXU, NormalGr], (instregex "GOT$")>;286 287//===----------------------------------------------------------------------===//288// Absolute and Negation289//===----------------------------------------------------------------------===//290 291def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "LP(G)?R$")>;292def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "L(N|P)GFR$")>;293def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "LN(R|GR)$")>;294def : InstRW<[WLat1, FXU, NormalGr], (instregex "LC(R|GR)$")>;295def : InstRW<[WLat2, WLat2, FXU2, GroupAlone], (instregex "LCGFR$")>;296 297//===----------------------------------------------------------------------===//298// Insertion299//===----------------------------------------------------------------------===//300 301def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "IC(Y)?$")>;302def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],303 (instregex "IC32(Y)?$")>;304def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],305 (instregex "ICM(H|Y)?$")>;306def : InstRW<[WLat1, FXU, NormalGr], (instregex "II(F|H|L)Mux$")>;307def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHF(64)?$")>;308def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHH(64)?$")>;309def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHL(64)?$")>;310def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILF(64)?$")>;311def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILH(64)?$")>;312def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILL(64)?$")>;313 314//===----------------------------------------------------------------------===//315// Addition316//===----------------------------------------------------------------------===//317 318def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],319 (instregex "A(L)?(Y)?$")>;320def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "A(L)?SI$")>;321def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],322 (instregex "AH(Y)?$")>;323def : InstRW<[WLat1, FXU, NormalGr], (instregex "AIH$")>;324def : InstRW<[WLat1, FXU, NormalGr], (instregex "AFI(Mux)?$")>;325def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGFI$")>;326def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGHI(K)?$")>;327def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGR(K)?$")>;328def : InstRW<[WLat1, FXU, NormalGr], (instregex "AHI(K)?$")>;329def : InstRW<[WLat1, FXU, NormalGr], (instregex "AHIMux(K)?$")>;330def : InstRW<[WLat1, FXU, NormalGr], (instregex "AL(FI|HSIK)$")>;331def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],332 (instregex "ALGF$")>;333def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGHSIK$")>;334def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGF(I|R)$")>;335def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGR(K)?$")>;336def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALR(K)?$")>;337def : InstRW<[WLat1, FXU, NormalGr], (instregex "AR(K)?$")>;338def : InstRW<[WLat1, FXU, NormalGr], (instregex "A(L)?HHHR$")>;339def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "A(L)?HHLR$")>;340def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALSIH(N)?$")>;341def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],342 (instregex "A(L)?G$")>;343def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "A(L)?GSI$")>;344 345// Logical addition with carry346def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, GroupAlone],347 (instregex "ALC(G)?$")>;348def : InstRW<[WLat2, WLat2, FXU, GroupAlone], (instregex "ALC(G)?R$")>;349 350// Add with sign extension (32 -> 64)351def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],352 (instregex "AGF$")>;353def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "AGFR$")>;354 355//===----------------------------------------------------------------------===//356// Subtraction357//===----------------------------------------------------------------------===//358 359def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],360 (instregex "S(G|Y)?$")>;361def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],362 (instregex "SH(Y)?$")>;363def : InstRW<[WLat1, FXU, NormalGr], (instregex "SGR(K)?$")>;364def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLFI$")>;365def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],366 (instregex "SL(G|GF|Y)?$")>;367def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLGF(I|R)$")>;368def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLGR(K)?$")>;369def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLR(K)?$")>;370def : InstRW<[WLat1, FXU, NormalGr], (instregex "SR(K)?$")>;371def : InstRW<[WLat1, FXU, NormalGr], (instregex "S(L)?HHHR$")>;372def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "S(L)?HHLR$")>;373 374// Subtraction with borrow375def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, GroupAlone],376 (instregex "SLB(G)?$")>;377def : InstRW<[WLat2, WLat2, FXU, GroupAlone], (instregex "SLB(G)?R$")>;378 379// Subtraction with sign extension (32 -> 64)380def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],381 (instregex "SGF$")>;382def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "SGFR$")>;383 384//===----------------------------------------------------------------------===//385// AND386//===----------------------------------------------------------------------===//387 388def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],389 (instregex "N(G|Y)?$")>;390def : InstRW<[WLat1, FXU, NormalGr], (instregex "NGR(K)?$")>;391def : InstRW<[WLat1, FXU, NormalGr], (instregex "NI(FMux|HMux|LMux)$")>;392def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "NI(Y)?$")>;393def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHF(64)?$")>;394def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHH(64)?$")>;395def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHL(64)?$")>;396def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILF(64)?$")>;397def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILH(64)?$")>;398def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILL(64)?$")>;399def : InstRW<[WLat1, FXU, NormalGr], (instregex "NR(K)?$")>;400def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "NC$")>;401 402//===----------------------------------------------------------------------===//403// OR404//===----------------------------------------------------------------------===//405 406def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],407 (instregex "O(G|Y)?$")>;408def : InstRW<[WLat1, FXU, NormalGr], (instregex "OGR(K)?$")>;409def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "OI(Y)?$")>;410def : InstRW<[WLat1, FXU, NormalGr], (instregex "OI(FMux|HMux|LMux)$")>;411def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHF(64)?$")>;412def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHH(64)?$")>;413def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHL(64)?$")>;414def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILF(64)?$")>;415def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILH(64)?$")>;416def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILL(64)?$")>;417def : InstRW<[WLat1, FXU, NormalGr], (instregex "OR(K)?$")>;418def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "OC$")>;419 420//===----------------------------------------------------------------------===//421// XOR422//===----------------------------------------------------------------------===//423 424def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],425 (instregex "X(G|Y)?$")>;426def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "XI(Y)?$")>;427def : InstRW<[WLat1, FXU, NormalGr], (instregex "XIFMux$")>;428def : InstRW<[WLat1, FXU, NormalGr], (instregex "XGR(K)?$")>;429def : InstRW<[WLat1, FXU, NormalGr], (instregex "XIHF(64)?$")>;430def : InstRW<[WLat1, FXU, NormalGr], (instregex "XILF(64)?$")>;431def : InstRW<[WLat1, FXU, NormalGr], (instregex "XR(K)?$")>;432def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "XC$")>;433 434//===----------------------------------------------------------------------===//435// Multiplication436//===----------------------------------------------------------------------===//437 438def : InstRW<[WLat6LSU, RegReadAdv, FXU, LSU, NormalGr],439 (instregex "MS(GF|Y)?$")>;440def : InstRW<[WLat6, FXU, NormalGr], (instregex "MS(R|FI)$")>;441def : InstRW<[WLat8LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "MSG$")>;442def : InstRW<[WLat8, FXU, NormalGr], (instregex "MSGR$")>;443def : InstRW<[WLat6, FXU, NormalGr], (instregex "MSGF(I|R)$")>;444def : InstRW<[WLat11LSU, RegReadAdv, FXU2, LSU, GroupAlone],445 (instregex "MLG$")>;446def : InstRW<[WLat9, FXU2, GroupAlone], (instregex "MLGR$")>;447def : InstRW<[WLat5, FXU, NormalGr], (instregex "MGHI$")>;448def : InstRW<[WLat5, FXU, NormalGr], (instregex "MHI$")>;449def : InstRW<[WLat5LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "MH(Y)?$")>;450def : InstRW<[WLat7, FXU2, GroupAlone], (instregex "M(L)?R$")>;451def : InstRW<[WLat7LSU, RegReadAdv, FXU2, LSU, GroupAlone],452 (instregex "M(FY|L)?$")>;453 454//===----------------------------------------------------------------------===//455// Division and remainder456//===----------------------------------------------------------------------===//457 458def : InstRW<[WLat30, FPU4, FXU5, GroupAlone3], (instregex "DR$")>;459def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU4, GroupAlone3],460 (instregex "D$")>;461def : InstRW<[WLat30, FPU4, FXU4, GroupAlone3], (instregex "DSG(F)?R$")>;462def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU3, GroupAlone3],463 (instregex "DSG(F)?$")>;464def : InstRW<[WLat30, FPU4, FXU5, GroupAlone3], (instregex "DL(G)?R$")>;465def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU4, GroupAlone3],466 (instregex "DL(G)?$")>;467 468//===----------------------------------------------------------------------===//469// Shifts470//===----------------------------------------------------------------------===//471 472def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLL(G|K)?$")>;473def : InstRW<[WLat1, FXU, NormalGr], (instregex "SRL(G|K)?$")>;474def : InstRW<[WLat1, FXU, NormalGr], (instregex "SRA(G|K)?$")>;475def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLA(G|K)?$")>;476def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],477 (instregex "S(L|R)D(A|L)$")>;478 479// Rotate480def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;481 482// Rotate and insert483def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)(Opt)?$")>;484def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)(Opt)?$")>;485def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?(Opt)?$")>;486def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;487 488// Rotate and Select489def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(Opt)?$")>;490 491//===----------------------------------------------------------------------===//492// Comparison493//===----------------------------------------------------------------------===//494 495def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "C(G|Y|Mux|RL)?$")>;496def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(F|H)I(Mux)?$")>;497def : InstRW<[WLat1, FXU, NormalGr], (instregex "CG(F|H)I$")>;498def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;499def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(G)?R$")>;500def : InstRW<[WLat1, FXU, NormalGr], (instregex "CIH$")>;501def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CHF$")>;502def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CHSI$")>;503def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],504 (instregex "CL(Y|Mux)?$")>;505def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLFHSI$")>;506def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLFI(Mux)?$")>;507def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLG$")>;508def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLG(HRL|HSI)$")>;509def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLGF$")>;510def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLGFRL$")>;511def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLGF(I|R)$")>;512def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLGR$")>;513def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLGRL$")>;514def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLHF$")>;515def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;516def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLIH$")>;517def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLI(Y)?$")>;518def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLR$")>;519def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLRL$")>;520def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(L)?HHR$")>;521def : InstRW<[WLat2, FXU, NormalGr], (instregex "C(L)?HLR$")>;522 523// Compare halfword524def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CH(Y)?$")>;525def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CHRL$")>;526def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGH$")>;527def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CGHRL$")>;528def : InstRW<[WLat2LSU, FXU2, LSU, GroupAlone], (instregex "CHHSI$")>;529 530// Compare with sign extension (32 -> 64)531def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGF$")>;532def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CGFRL$")>;533def : InstRW<[WLat2, FXU, NormalGr], (instregex "CGFR$")>;534 535// Compare logical character536def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "CLC$")>;537def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLCL(E|U)?$")>;538def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLST$")>;539 540// Test under mask541def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "TM(Y)?$")>;542def : InstRW<[WLat1, FXU, NormalGr], (instregex "TM(H|L)Mux$")>;543def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMHH(64)?$")>;544def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMHL(64)?$")>;545def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMLH(64)?$")>;546def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMLL(64)?$")>;547 548// Compare logical characters under mask549def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],550 (instregex "CLM(H|Y)?$")>;551 552//===----------------------------------------------------------------------===//553// Prefetch and execution hint554//===----------------------------------------------------------------------===//555 556def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;557def : InstRW<[WLat1, LSU, NormalGr], (instregex "BP(R)?P$")>;558def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIAI$")>;559 560//===----------------------------------------------------------------------===//561// Atomic operations562//===----------------------------------------------------------------------===//563 564def : InstRW<[WLat1, LSU, EndGroup], (instregex "Serialize$")>;565 566def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAA(G)?$")>;567def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAAL(G)?$")>;568def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAN(G)?$")>;569def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAO(G)?$")>;570def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAX(G)?$")>;571 572// Test and set573def : InstRW<[WLat1LSU, FXU, LSU, EndGroup], (instregex "TS$")>;574 575// Compare and swap576def : InstRW<[WLat2LSU, WLat2LSU, FXU2, LSU, GroupAlone],577 (instregex "CS(G|Y)?$")>;578 579// Compare double and swap580def : InstRW<[WLat5LSU, WLat5LSU, FXU5, LSU, GroupAlone2],581 (instregex "CDS(Y)?$")>;582def : InstRW<[WLat12, WLat12, FXU6, LSU2, GroupAlone],583 (instregex "CDSG$")>;584 585// Compare and swap and store586def : InstRW<[WLat30, MCD], (instregex "CSST$")>;587 588// Perform locked operation589def : InstRW<[WLat30, MCD], (instregex "PLO$")>;590 591// Load/store pair from/to quadword592def : InstRW<[WLat4LSU, LSU2, GroupAlone], (instregex "LPQ$")>;593def : InstRW<[WLat1, FXU2, LSU2, GroupAlone], (instregex "STPQ$")>;594 595// Load pair disjoint596def : InstRW<[WLat2LSU, WLat2LSU, LSU2, GroupAlone], (instregex "LPD(G)?$")>;597 598//===----------------------------------------------------------------------===//599// Translate and convert600//===----------------------------------------------------------------------===//601 602def : InstRW<[WLat1, LSU, GroupAlone], (instregex "TR$")>;603def : InstRW<[WLat30, WLat30, WLat30, FXU3, LSU2, GroupAlone2],604 (instregex "TRT$")>;605def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRTR$")>;606def : InstRW<[WLat30, WLat30, MCD], (instregex "TRE$")>;607def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRT(R)?E(Opt)?$")>;608def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TR(T|O)(T|O)(Opt)?$")>;609def : InstRW<[WLat30, WLat30, WLat30, MCD],610 (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;611def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(CUUTF|CUTFU)(Opt)?$")>;612 613//===----------------------------------------------------------------------===//614// Message-security assist615//===----------------------------------------------------------------------===//616 617def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD],618 (instregex "KM(C|F|O|CTR)?$")>;619def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(KIMD|KLMD|KMAC|PCC)$")>;620 621//===----------------------------------------------------------------------===//622// Decimal arithmetic623//===----------------------------------------------------------------------===//624 625def : InstRW<[WLat30, RegReadAdv, FXU, DFU2, LSU2, GroupAlone2],626 (instregex "CVBG$")>;627def : InstRW<[WLat20, RegReadAdv, FXU, DFU, LSU, GroupAlone],628 (instregex "CVB(Y)?$")>;629def : InstRW<[WLat1, FXU3, DFU4, LSU, GroupAlone3], (instregex "CVDG$")>;630def : InstRW<[WLat1, FXU2, DFU, LSU, GroupAlone], (instregex "CVD(Y)?$")>;631def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "MV(N|O|Z)$")>;632def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "(PACK|PKA|PKU)$")>;633def : InstRW<[WLat10, LSU5, GroupAlone], (instregex "UNPK(A|U)$")>;634def : InstRW<[WLat1, FXU, LSU2, GroupAlone], (instregex "UNPK$")>;635 636def : InstRW<[WLat11LSU, FXU, DFU4, LSU2, GroupAlone],637 (instregex "(A|S|ZA)P$")>;638def : InstRW<[WLat1, FXU, DFU4, LSU2, GroupAlone], (instregex "(M|D)P$")>;639def : InstRW<[WLat15, FXU2, DFU4, LSU3, GroupAlone], (instregex "SRP$")>;640def : InstRW<[WLat11, DFU4, LSU2, GroupAlone], (instregex "CP$")>;641def : InstRW<[WLat5LSU, DFU2, LSU2, GroupAlone], (instregex "TP$")>;642def : InstRW<[WLat30, MCD], (instregex "ED(MK)?$")>;643 644//===----------------------------------------------------------------------===//645// Access registers646//===----------------------------------------------------------------------===//647 648// Extract/set/copy access register649def : InstRW<[WLat3, LSU, NormalGr], (instregex "(EAR|SAR|CPYA)$")>;650 651// Load address extended652def : InstRW<[WLat5, LSU, FXU, GroupAlone], (instregex "LAE(Y)?$")>;653 654// Load/store access multiple (not modeled precisely)655def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LAM(Y)?$")>;656def : InstRW<[WLat1, FXU5, LSU5, GroupAlone], (instregex "STAM(Y)?$")>;657 658//===----------------------------------------------------------------------===//659// Program mask and addressing mode660//===----------------------------------------------------------------------===//661 662// Insert Program Mask663def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;664 665// Set Program Mask666def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;667 668// Branch and link669def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "BAL(R)?$")>;670 671// Test addressing mode672def : InstRW<[WLat1, FXU, NormalGr], (instregex "TAM$")>;673 674// Set addressing mode675def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAM(24|31|64)$")>;676 677// Branch (and save) and set mode.678def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BSM$")>;679def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "BASSM$")>;680 681//===----------------------------------------------------------------------===//682// Transactional execution683//===----------------------------------------------------------------------===//684 685// Transaction begin686def : InstRW<[WLat9, LSU2, FXU5, GroupAlone], (instregex "TBEGIN(C)?$")>;687 688// Transaction end689def : InstRW<[WLat4, LSU, GroupAlone], (instregex "TEND$")>;690 691// Transaction abort692def : InstRW<[WLat30, MCD], (instregex "TABORT$")>;693 694// Extract Transaction Nesting Depth695def : InstRW<[WLat30, MCD], (instregex "ETND$")>;696 697// Nontransactional store698def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "NTSTG$")>;699 700//===----------------------------------------------------------------------===//701// Processor assist702//===----------------------------------------------------------------------===//703 704def : InstRW<[WLat30, MCD], (instregex "PPA$")>;705 706//===----------------------------------------------------------------------===//707// Miscellaneous Instructions.708//===----------------------------------------------------------------------===//709 710// Find leftmost one711def : InstRW<[WLat7, WLat7, FXU2, GroupAlone], (instregex "FLOGR$")>;712 713// Population count714def : InstRW<[WLat3, WLat3, FXU, NormalGr], (instregex "POPCNT$")>;715 716// String instructions717def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "SRST(U)?$")>;718def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CUSE$")>;719 720// Various complex instructions721def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CFC$")>;722def : InstRW<[WLat30, WLat30, WLat30, WLat30, WLat30, WLat30, MCD],723 (instregex "UPT$")>;724def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CKSM$")>;725def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CMPSC$")>;726 727// Execute728def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;729 730//===----------------------------------------------------------------------===//731// .insn directive instructions732//===----------------------------------------------------------------------===//733 734// An "empty" sched-class will be assigned instead of the "invalid sched-class".735// getNumDecoderSlots() will then return 1 instead of 0.736def : InstRW<[], (instregex "Insn.*")>;737 738 739// ----------------------------- Floating point ----------------------------- //740 741//===----------------------------------------------------------------------===//742// FP: Move instructions743//===----------------------------------------------------------------------===//744 745// Load zero746def : InstRW<[WLat1, FXU, NormalGr], (instregex "LZ(DR|ER|ER_16)$")>;747def : InstRW<[WLat2, FXU2, GroupAlone], (instregex "LZXR$")>;748 749// Load750def : InstRW<[WLat1, FXU, NormalGr], (instregex "LER(16)?$")>;751def : InstRW<[WLat1, FXU, NormalGr], (instregex "LD(R|R16|R32|GR)$")>;752def : InstRW<[WLat3, FXU, NormalGr], (instregex "LGDR$")>;753def : InstRW<[WLat2, FXU2, GroupAlone], (instregex "LXR$")>;754 755// Load and Test756def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;757def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "LTXBR$")>;758 759// Copy sign760def : InstRW<[WLat5, FXU2, GroupAlone], (instregex "CPSDR(d|s|h)(d|s|h)$")>;761 762//===----------------------------------------------------------------------===//763// FP: Load instructions764//===----------------------------------------------------------------------===//765 766def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(E16|E|D)(Y|E32)?$")>;767def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;768 769//===----------------------------------------------------------------------===//770// FP: Store instructions771//===----------------------------------------------------------------------===//772 773def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(E16|E|D)(Y)?$")>;774def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STX$")>;775 776//===----------------------------------------------------------------------===//777// FP: Conversion instructions778//===----------------------------------------------------------------------===//779 780// Load rounded781def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;782def : InstRW<[WLat9, FPU2, NormalGr], (instregex "L(E|D)XBR(A)?$")>;783 784// Load lengthened785def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;786def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;787def : InstRW<[WLat11LSU, FPU4, LSU, GroupAlone], (instregex "LX(E|D)B$")>;788def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "LX(E|D)BR$")>;789 790// Convert from fixed / logical791def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;792def : InstRW<[WLat11, FXU, FPU4, GroupAlone2], (instregex "CX(F|G)BR(A?)$")>;793def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;794def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;795def : InstRW<[WLat11, FXU, FPU4, GroupAlone2], (instregex "CXL(F|G)BR$")>;796 797// Convert to fixed / logical798def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],799 (instregex "C(F|G)(E|D)BR(A?)$")>;800def : InstRW<[WLat12, WLat12, FXU, FPU2, GroupAlone],801 (instregex "C(F|G)XBR(A?)$")>;802def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],803 (instregex "CL(F|G)(E|D)BR$")>;804def : InstRW<[WLat12, WLat12, FXU, FPU2, GroupAlone], (instregex "CL(F|G)XBR$")>;805 806//===----------------------------------------------------------------------===//807// FP: Unary arithmetic808//===----------------------------------------------------------------------===//809 810// Load Complement / Negative / Positive811def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "L(C|N|P)(E|D)BR$")>;812def : InstRW<[WLat1, FXU, NormalGr], (instregex "L(C|N|P)DFR(_32|_16)?$")>;813def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "L(C|N|P)XBR$")>;814 815// Square root816def : InstRW<[WLat30, FPU, LSU, NormalGr], (instregex "SQ(E|D)B$")>;817def : InstRW<[WLat30, FPU, NormalGr], (instregex "SQ(E|D)BR$")>;818def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "SQXBR$")>;819 820// Load FP integer821def : InstRW<[WLat7, FPU, NormalGr], (instregex "FI(E|D)BR(A)?$")>;822def : InstRW<[WLat15, FPU4, GroupAlone], (instregex "FIXBR(A)?$")>;823 824//===----------------------------------------------------------------------===//825// FP: Binary arithmetic826//===----------------------------------------------------------------------===//827 828// Addition829def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],830 (instregex "A(E|D)B$")>;831def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "A(E|D)BR$")>;832def : InstRW<[WLat20, WLat20, FPU4, GroupAlone], (instregex "AXBR$")>;833 834// Subtraction835def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],836 (instregex "S(E|D)B$")>;837def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "S(E|D)BR$")>;838def : InstRW<[WLat20, WLat20, FPU4, GroupAlone], (instregex "SXBR$")>;839 840// Multiply841def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],842 (instregex "M(D|DE|EE)B$")>;843def : InstRW<[WLat7, FPU, NormalGr], (instregex "M(D|DE|EE)BR$")>;844def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone],845 (instregex "MXDB$")>;846def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MXDBR$")>;847def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "MXBR$")>;848 849// Multiply and add / subtract850def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],851 (instregex "M(A|S)EB$")>;852def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)EBR$")>;853def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],854 (instregex "M(A|S)DB$")>;855def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)DBR$")>;856 857// Division858def : InstRW<[WLat30, RegReadAdv, FPU, LSU, NormalGr], (instregex "D(E|D)B$")>;859def : InstRW<[WLat30, FPU, NormalGr], (instregex "D(E|D)BR$")>;860def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "DXBR$")>;861 862// Divide to integer863def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "DI(E|D)BR$")>;864 865//===----------------------------------------------------------------------===//866// FP: Comparisons867//===----------------------------------------------------------------------===//868 869// Compare870def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr],871 (instregex "(K|C)(E|D)B$")>;872def : InstRW<[WLat9, FPU, NormalGr], (instregex "(K|C)(E|D)BR$")>;873def : InstRW<[WLat30, FPU2, NormalGr], (instregex "(K|C)XBR$")>;874 875// Test Data Class876def : InstRW<[WLat15, FPU, LSU, NormalGr], (instregex "TC(E|D)B$")>;877def : InstRW<[WLat15, FPU4, LSU, GroupAlone], (instregex "TCXB$")>;878 879//===----------------------------------------------------------------------===//880// FP: Floating-point control register instructions881//===----------------------------------------------------------------------===//882 883def : InstRW<[WLat4, FXU, LSU, GroupAlone], (instregex "EFPC$")>;884def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "STFPC$")>;885def : InstRW<[WLat1, LSU, GroupAlone], (instregex "SFPC$")>;886def : InstRW<[WLat1, LSU2, GroupAlone], (instregex "LFPC$")>;887def : InstRW<[WLat30, MCD], (instregex "SFASR$")>;888def : InstRW<[WLat30, MCD], (instregex "LFAS$")>;889def : InstRW<[WLat2, FXU, GroupAlone], (instregex "SRNM(B|T)?$")>;890 891 892// --------------------- Hexadecimal floating point ------------------------- //893 894//===----------------------------------------------------------------------===//895// HFP: Move instructions896//===----------------------------------------------------------------------===//897 898// Load and Test899def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)R$")>;900def : InstRW<[WLat9, WLat9, FPU4, GroupAlone], (instregex "LTXR$")>;901 902//===----------------------------------------------------------------------===//903// HFP: Conversion instructions904//===----------------------------------------------------------------------===//905 906// Load rounded907def : InstRW<[WLat7, FPU, NormalGr], (instregex "(LEDR|LRER)$")>;908def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEXR$")>;909def : InstRW<[WLat9, FPU, NormalGr], (instregex "(LDXR|LRDR)$")>;910 911// Load lengthened912def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LDE$")>;913def : InstRW<[WLat1, FXU, NormalGr], (instregex "LDER$")>;914def : InstRW<[WLat11LSU, FPU4, LSU, GroupAlone], (instregex "LX(E|D)$")>;915def : InstRW<[WLat9, FPU4, GroupAlone], (instregex "LX(E|D)R$")>;916 917// Convert from fixed918def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)R$")>;919def : InstRW<[WLat10, FXU, FPU4, GroupAlone2], (instregex "CX(F|G)R$")>;920 921// Convert to fixed922def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],923 (instregex "C(F|G)(E|D)R$")>;924def : InstRW<[WLat30, WLat30, FXU, FPU2, GroupAlone], (instregex "C(F|G)XR$")>;925 926// Convert BFP to HFP / HFP to BFP.927def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "THD(E)?R$")>;928def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "TB(E)?DR$")>;929 930//===----------------------------------------------------------------------===//931// HFP: Unary arithmetic932//===----------------------------------------------------------------------===//933 934// Load Complement / Negative / Positive935def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "L(C|N|P)(E|D)R$")>;936def : InstRW<[WLat9, WLat9, FPU4, GroupAlone], (instregex "L(C|N|P)XR$")>;937 938// Halve939def : InstRW<[WLat7, FPU, NormalGr], (instregex "H(E|D)R$")>;940 941// Square root942def : InstRW<[WLat30, FPU, LSU, NormalGr], (instregex "SQ(E|D)$")>;943def : InstRW<[WLat30, FPU, NormalGr], (instregex "SQ(E|D)R$")>;944def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "SQXR$")>;945 946// Load FP integer947def : InstRW<[WLat7, FPU, NormalGr], (instregex "FI(E|D)R$")>;948def : InstRW<[WLat15, FPU4, GroupAlone], (instregex "FIXR$")>;949 950//===----------------------------------------------------------------------===//951// HFP: Binary arithmetic952//===----------------------------------------------------------------------===//953 954// Addition955def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],956 (instregex "A(E|D|U|W)$")>;957def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "A(E|D|U|W)R$")>;958def : InstRW<[WLat15, WLat15, FPU4, GroupAlone], (instregex "AXR$")>;959 960// Subtraction961def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],962 (instregex "S(E|D|U|W)$")>;963def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "S(E|D|U|W)R$")>;964def : InstRW<[WLat15, WLat15, FPU4, GroupAlone], (instregex "SXR$")>;965 966// Multiply967def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "M(D|EE)$")>;968def : InstRW<[WLat8LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "M(DE|E)$")>;969def : InstRW<[WLat7, FPU, NormalGr], (instregex "M(D|EE)R$")>;970def : InstRW<[WLat8, FPU, NormalGr], (instregex "M(DE|E)R$")>;971def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone], (instregex "MXD$")>;972def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MXDR$")>;973def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "MXR$")>;974def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone], (instregex "MY$")>;975def : InstRW<[WLat7LSU, RegReadAdv, FPU2, LSU, GroupAlone],976 (instregex "MY(H|L)$")>;977def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MYR$")>;978def : InstRW<[WLat7, FPU, GroupAlone], (instregex "MY(H|L)R$")>;979 980// Multiply and add / subtract981def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],982 (instregex "M(A|S)(E|D)$")>;983def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)(E|D)R$")>;984def : InstRW<[WLat11LSU, RegReadAdv, RegReadAdv, FPU4, LSU, GroupAlone],985 (instregex "MAY$")>;986def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],987 (instregex "MAY(H|L)$")>;988def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MAYR$")>;989def : InstRW<[WLat7, FPU, GroupAlone], (instregex "MAY(H|L)R$")>;990 991// Division992def : InstRW<[WLat30, RegReadAdv, FPU, LSU, NormalGr], (instregex "D(E|D)$")>;993def : InstRW<[WLat30, FPU, NormalGr], (instregex "D(E|D)R$")>;994def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "DXR$")>;995 996//===----------------------------------------------------------------------===//997// HFP: Comparisons998//===----------------------------------------------------------------------===//999 1000// Compare1001def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "C(E|D)$")>;1002def : InstRW<[WLat9, FPU, NormalGr], (instregex "C(E|D)R$")>;1003def : InstRW<[WLat15, FPU2, NormalGr], (instregex "CXR$")>;1004 1005 1006// ------------------------ Decimal floating point -------------------------- //1007 1008//===----------------------------------------------------------------------===//1009// DFP: Move instructions1010//===----------------------------------------------------------------------===//1011 1012// Load and Test1013def : InstRW<[WLat4, WLat4, DFU, NormalGr], (instregex "LTDTR$")>;1014def : InstRW<[WLat6, WLat6, DFU4, GroupAlone], (instregex "LTXTR$")>;1015 1016//===----------------------------------------------------------------------===//1017// DFP: Conversion instructions1018//===----------------------------------------------------------------------===//1019 1020// Load rounded1021def : InstRW<[WLat30, DFU, NormalGr], (instregex "LEDTR$")>;1022def : InstRW<[WLat30, DFU2, NormalGr], (instregex "LDXTR$")>;1023 1024// Load lengthened1025def : InstRW<[WLat7, DFU, NormalGr], (instregex "LDETR$")>;1026def : InstRW<[WLat6, DFU4, GroupAlone], (instregex "LXDTR$")>;1027 1028// Convert from fixed / logical1029def : InstRW<[WLat9, FXU, DFU, GroupAlone], (instregex "CDFTR$")>;1030def : InstRW<[WLat30, FXU, DFU, GroupAlone], (instregex "CDGTR(A)?$")>;1031def : InstRW<[WLat5, FXU, DFU4, GroupAlone2], (instregex "CXFTR(A)?$")>;1032def : InstRW<[WLat30, FXU, DFU4, GroupAlone2], (instregex "CXGTR(A)?$")>;1033def : InstRW<[WLat9, FXU, DFU, GroupAlone], (instregex "CDL(F|G)TR$")>;1034def : InstRW<[WLat9, FXU, DFU4, GroupAlone2], (instregex "CXLFTR$")>;1035def : InstRW<[WLat5, FXU, DFU4, GroupAlone2], (instregex "CXLGTR$")>;1036 1037// Convert to fixed / logical1038def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "CFDTR(A)?$")>;1039def : InstRW<[WLat30, WLat30, FXU, DFU, GroupAlone], (instregex "CGDTR(A)?$")>;1040def : InstRW<[WLat7, WLat7, FXU, DFU2, GroupAlone], (instregex "CFXTR$")>;1041def : InstRW<[WLat30, WLat30, FXU, DFU2, GroupAlone], (instregex "CGXTR(A)?$")>;1042def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "CL(F|G)DTR$")>;1043def : InstRW<[WLat7, WLat7, FXU, DFU2, GroupAlone], (instregex "CL(F|G)XTR$")>;1044 1045// Convert from / to signed / unsigned packed1046def : InstRW<[WLat5, FXU, DFU, GroupAlone], (instregex "CD(S|U)TR$")>;1047def : InstRW<[WLat8, FXU2, DFU4, GroupAlone2], (instregex "CX(S|U)TR$")>;1048def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "C(S|U)DTR$")>;1049def : InstRW<[WLat12, FXU2, DFU4, GroupAlone2], (instregex "C(S|U)XTR$")>;1050 1051// Convert from / to zoned1052def : InstRW<[WLat4LSU, LSU, DFU2, GroupAlone], (instregex "CDZT$")>;1053def : InstRW<[WLat11LSU, LSU2, DFU4, GroupAlone3], (instregex "CXZT$")>;1054def : InstRW<[WLat1, FXU, LSU, DFU2, GroupAlone], (instregex "CZDT$")>;1055def : InstRW<[WLat1, FXU, LSU, DFU2, GroupAlone], (instregex "CZXT$")>;1056 1057// Perform floating-point operation1058def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "PFPO$")>;1059 1060//===----------------------------------------------------------------------===//1061// DFP: Unary arithmetic1062//===----------------------------------------------------------------------===//1063 1064// Load FP integer1065def : InstRW<[WLat8, DFU, NormalGr], (instregex "FIDTR$")>;1066def : InstRW<[WLat10, DFU4, GroupAlone], (instregex "FIXTR$")>;1067 1068// Extract biased exponent1069def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "EEDTR$")>;1070def : InstRW<[WLat8, FXU, DFU2, GroupAlone], (instregex "EEXTR$")>;1071 1072// Extract significance1073def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "ESDTR$")>;1074def : InstRW<[WLat8, FXU, DFU2, GroupAlone], (instregex "ESXTR$")>;1075 1076//===----------------------------------------------------------------------===//1077// DFP: Binary arithmetic1078//===----------------------------------------------------------------------===//1079 1080// Addition1081def : InstRW<[WLat9, WLat9, DFU, NormalGr], (instregex "ADTR(A)?$")>;1082def : InstRW<[WLat30, WLat30, DFU4, GroupAlone], (instregex "AXTR(A)?$")>;1083 1084// Subtraction1085def : InstRW<[WLat9, WLat9, DFU, NormalGr], (instregex "SDTR(A)?$")>;1086def : InstRW<[WLat30, WLat30, DFU4, GroupAlone], (instregex "SXTR(A)?$")>;1087 1088// Multiply1089def : InstRW<[WLat30, DFU, NormalGr], (instregex "MDTR(A)?$")>;1090def : InstRW<[WLat30, DFU4, GroupAlone], (instregex "MXTR(A)?$")>;1091 1092// Division1093def : InstRW<[WLat30, DFU, NormalGr], (instregex "DDTR(A)?$")>;1094def : InstRW<[WLat30, DFU4, GroupAlone], (instregex "DXTR(A)?$")>;1095 1096// Quantize1097def : InstRW<[WLat8, WLat8, DFU, NormalGr], (instregex "QADTR$")>;1098def : InstRW<[WLat10, WLat10, DFU4, GroupAlone], (instregex "QAXTR$")>;1099 1100// Reround1101def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "RRDTR$")>;1102def : InstRW<[WLat30, WLat30, FXU, DFU4, GroupAlone2], (instregex "RRXTR$")>;1103 1104// Shift significand left/right1105def : InstRW<[WLat7LSU, LSU, DFU, GroupAlone], (instregex "S(L|R)DT$")>;1106def : InstRW<[WLat11LSU, LSU, DFU4, GroupAlone], (instregex "S(L|R)XT$")>;1107 1108// Insert biased exponent1109def : InstRW<[WLat5, FXU, DFU, GroupAlone], (instregex "IEDTR$")>;1110def : InstRW<[WLat7, FXU, DFU4, GroupAlone2], (instregex "IEXTR$")>;1111 1112//===----------------------------------------------------------------------===//1113// DFP: Comparisons1114//===----------------------------------------------------------------------===//1115 1116// Compare1117def : InstRW<[WLat9, DFU, NormalGr], (instregex "(K|C)DTR$")>;1118def : InstRW<[WLat10, DFU2, NormalGr], (instregex "(K|C)XTR$")>;1119 1120// Compare biased exponent1121def : InstRW<[WLat4, DFU, NormalGr], (instregex "CEDTR$")>;1122def : InstRW<[WLat5, DFU2, NormalGr], (instregex "CEXTR$")>;1123 1124// Test Data Class/Group1125def : InstRW<[WLat9, LSU, DFU, NormalGr], (instregex "TD(C|G)DT$")>;1126def : InstRW<[WLat10, LSU, DFU, NormalGr], (instregex "TD(C|G)ET$")>;1127def : InstRW<[WLat10, LSU, DFU2, NormalGr], (instregex "TD(C|G)XT$")>;1128 1129 1130// -------------------------------- System ---------------------------------- //1131 1132//===----------------------------------------------------------------------===//1133// System: Program-Status Word Instructions1134//===----------------------------------------------------------------------===//1135 1136def : InstRW<[WLat30, WLat30, MCD], (instregex "EPSW$")>;1137def : InstRW<[WLat30, MCD], (instregex "LPSW(E)?$")>;1138def : InstRW<[WLat3, FXU, GroupAlone], (instregex "IPK$")>;1139def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;1140def : InstRW<[WLat1, LSU, EndGroup], (instregex "SSM$")>;1141def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "ST(N|O)SM$")>;1142def : InstRW<[WLat3, FXU, NormalGr], (instregex "IAC$")>;1143def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAC(F)?$")>;1144 1145//===----------------------------------------------------------------------===//1146// System: Control Register Instructions1147//===----------------------------------------------------------------------===//1148 1149def : InstRW<[WLat10, WLat10, FXU, LSU, NormalGr], (instregex "LCTL(G)?$")>;1150def : InstRW<[WLat1, FXU5, LSU5, GroupAlone], (instregex "STCT(L|G)$")>;1151def : InstRW<[LSULatency, LSU, NormalGr], (instregex "E(P|S)A(I)?R$")>;1152def : InstRW<[WLat30, MCD], (instregex "SSA(I)?R$")>;1153def : InstRW<[WLat30, MCD], (instregex "ESEA$")>;1154 1155//===----------------------------------------------------------------------===//1156// System: Prefix-Register Instructions1157//===----------------------------------------------------------------------===//1158 1159def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;1160 1161//===----------------------------------------------------------------------===//1162// System: Storage-Key and Real Memory Instructions1163//===----------------------------------------------------------------------===//1164 1165def : InstRW<[WLat30, MCD], (instregex "ISKE$")>;1166def : InstRW<[WLat30, MCD], (instregex "IVSK$")>;1167def : InstRW<[WLat30, MCD], (instregex "SSKE(Opt)?$")>;1168def : InstRW<[WLat30, MCD], (instregex "RRB(E|M)$")>;1169def : InstRW<[WLat30, MCD], (instregex "PFMF$")>;1170def : InstRW<[WLat30, WLat30, MCD], (instregex "TB$")>;1171def : InstRW<[WLat30, MCD], (instregex "PGIN$")>;1172def : InstRW<[WLat30, MCD], (instregex "PGOUT$")>;1173 1174//===----------------------------------------------------------------------===//1175// System: Dynamic-Address-Translation Instructions1176//===----------------------------------------------------------------------===//1177 1178def : InstRW<[WLat30, MCD], (instregex "IPTE(Opt)?(Opt)?$")>;1179def : InstRW<[WLat30, MCD], (instregex "IDTE(Opt)?$")>;1180def : InstRW<[WLat30, MCD], (instregex "CRDTE(Opt)?$")>;1181def : InstRW<[WLat30, MCD], (instregex "PTLB$")>;1182def : InstRW<[WLat30, WLat30, MCD], (instregex "CSP(G)?$")>;1183def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "LPTEA$")>;1184def : InstRW<[WLat30, WLat30, MCD], (instregex "LRA(Y|G)?$")>;1185def : InstRW<[WLat30, MCD], (instregex "STRAG$")>;1186def : InstRW<[WLat30, MCD], (instregex "LURA(G)?$")>;1187def : InstRW<[WLat30, MCD], (instregex "STUR(A|G)$")>;1188def : InstRW<[WLat30, MCD], (instregex "TPROT$")>;1189 1190//===----------------------------------------------------------------------===//1191// System: Memory-move Instructions1192//===----------------------------------------------------------------------===//1193 1194def : InstRW<[WLat30, MCD], (instregex "MVC(K|P|S)$")>;1195def : InstRW<[WLat30, MCD], (instregex "MVC(S|D)K$")>;1196def : InstRW<[WLat30, MCD], (instregex "MVCOS$")>;1197def : InstRW<[WLat30, MCD], (instregex "MVPG$")>;1198 1199//===----------------------------------------------------------------------===//1200// System: Address-Space Instructions1201//===----------------------------------------------------------------------===//1202 1203def : InstRW<[WLat30, MCD], (instregex "LASP$")>;1204def : InstRW<[WLat1, LSU, GroupAlone], (instregex "PALB$")>;1205def : InstRW<[WLat30, MCD], (instregex "PC$")>;1206def : InstRW<[WLat30, MCD], (instregex "PR$")>;1207def : InstRW<[WLat30, MCD], (instregex "PT(I)?$")>;1208def : InstRW<[WLat30, MCD], (instregex "RP$")>;1209def : InstRW<[WLat30, MCD], (instregex "BS(G|A)$")>;1210def : InstRW<[WLat30, MCD], (instregex "TAR$")>;1211 1212//===----------------------------------------------------------------------===//1213// System: Linkage-Stack Instructions1214//===----------------------------------------------------------------------===//1215 1216def : InstRW<[WLat30, MCD], (instregex "BAKR$")>;1217def : InstRW<[WLat30, MCD], (instregex "EREG(G)?$")>;1218def : InstRW<[WLat30, WLat30, MCD], (instregex "(E|M)STA$")>;1219 1220//===----------------------------------------------------------------------===//1221// System: Time-Related Instructions1222//===----------------------------------------------------------------------===//1223 1224def : InstRW<[WLat30, MCD], (instregex "PTFF$")>;1225def : InstRW<[WLat30, MCD], (instregex "SCK$")>;1226def : InstRW<[WLat30, MCD], (instregex "SCKPF$")>;1227def : InstRW<[WLat30, MCD], (instregex "SCKC$")>;1228def : InstRW<[WLat30, MCD], (instregex "SPT$")>;1229def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "STCK(F)?$")>;1230def : InstRW<[WLat20, LSU4, FXU2, GroupAlone2], (instregex "STCKE$")>;1231def : InstRW<[WLat30, MCD], (instregex "STCKC$")>;1232def : InstRW<[WLat30, MCD], (instregex "STPT$")>;1233 1234//===----------------------------------------------------------------------===//1235// System: CPU-Related Instructions1236//===----------------------------------------------------------------------===//1237 1238def : InstRW<[WLat30, MCD], (instregex "STAP$")>;1239def : InstRW<[WLat30, MCD], (instregex "STIDP$")>;1240def : InstRW<[WLat30, WLat30, MCD], (instregex "STSI$")>;1241def : InstRW<[WLat30, WLat30, MCD], (instregex "STFL(E)?$")>;1242def : InstRW<[WLat30, MCD], (instregex "ECAG$")>;1243def : InstRW<[WLat30, WLat30, MCD], (instregex "ECTG$")>;1244def : InstRW<[WLat30, MCD], (instregex "PTF$")>;1245def : InstRW<[WLat30, MCD], (instregex "PCKMO$")>;1246 1247//===----------------------------------------------------------------------===//1248// System: Miscellaneous Instructions1249//===----------------------------------------------------------------------===//1250 1251def : InstRW<[WLat30, MCD], (instregex "SVC$")>;1252def : InstRW<[WLat1, FXU, GroupAlone], (instregex "MC$")>;1253def : InstRW<[WLat30, MCD], (instregex "DIAG$")>;1254def : InstRW<[WLat1, FXU, NormalGr], (instregex "TRAC(E|G)$")>;1255def : InstRW<[WLat30, MCD], (instregex "TRAP(2|4)$")>;1256def : InstRW<[WLat30, MCD], (instregex "SIG(P|A)$")>;1257def : InstRW<[WLat30, MCD], (instregex "SIE$")>;1258 1259//===----------------------------------------------------------------------===//1260// System: CPU-Measurement Facility Instructions1261//===----------------------------------------------------------------------===//1262 1263def : InstRW<[WLat1, FXU, NormalGr], (instregex "LPP$")>;1264def : InstRW<[WLat30, WLat30, MCD], (instregex "ECPGA$")>;1265def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;1266def : InstRW<[WLat30, MCD], (instregex "LCCTL$")>;1267def : InstRW<[WLat30, MCD], (instregex "L(P|S)CTL$")>;1268def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;1269def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;1270 1271//===----------------------------------------------------------------------===//1272// System: I/O Instructions1273//===----------------------------------------------------------------------===//1274 1275def : InstRW<[WLat30, MCD], (instregex "(C|H|R|X)SCH$")>;1276def : InstRW<[WLat30, MCD], (instregex "(M|S|ST|T)SCH$")>;1277def : InstRW<[WLat30, MCD], (instregex "RCHP$")>;1278def : InstRW<[WLat30, MCD], (instregex "SCHM$")>;1279def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;1280def : InstRW<[WLat30, MCD], (instregex "TPI$")>;1281def : InstRW<[WLat30, MCD], (instregex "SAL$")>;1282 1283//===----------------------------------------------------------------------===//1284// NOPs1285//===----------------------------------------------------------------------===//1286 1287def : InstRW<[WLat1, LSU, NormalGr], (instregex "NOP(R)?(Opt)?$")>;1288def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;1289}1290 1291