1571 lines · cpp
1//===-- VEAsmParser.cpp - Parse VE assembly to MCInst instructions --------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "MCTargetDesc/VEMCAsmInfo.h"10#include "MCTargetDesc/VEMCTargetDesc.h"11#include "TargetInfo/VETargetInfo.h"12#include "VE.h"13#include "llvm/ADT/SmallVector.h"14#include "llvm/ADT/StringRef.h"15#include "llvm/ADT/Twine.h"16#include "llvm/MC/MCContext.h"17#include "llvm/MC/MCExpr.h"18#include "llvm/MC/MCInst.h"19#include "llvm/MC/MCInstrInfo.h"20#include "llvm/MC/MCParser/AsmLexer.h"21#include "llvm/MC/MCParser/MCAsmParser.h"22#include "llvm/MC/MCParser/MCParsedAsmOperand.h"23#include "llvm/MC/MCParser/MCTargetAsmParser.h"24#include "llvm/MC/MCStreamer.h"25#include "llvm/MC/MCSubtargetInfo.h"26#include "llvm/MC/MCSymbol.h"27#include "llvm/MC/TargetRegistry.h"28#include "llvm/Support/Compiler.h"29#include "llvm/Support/raw_ostream.h"30#include <memory>31 32using namespace llvm;33 34#define DEBUG_TYPE "ve-asmparser"35 36namespace {37 38class VEOperand;39 40class VEAsmParser : public MCTargetAsmParser {41 MCAsmParser &Parser;42 43 /// @name Auto-generated Match Functions44 /// {45 46#define GET_ASSEMBLER_HEADER47#include "VEGenAsmMatcher.inc"48 49 /// }50 51 // public interface of the MCTargetAsmParser.52 bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,53 OperandVector &Operands, MCStreamer &Out,54 uint64_t &ErrorInfo,55 bool MatchingInlineAsm) override;56 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;57 MCRegister parseRegisterName(MCRegister (*matchFn)(StringRef));58 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,59 SMLoc &EndLoc) override;60 bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,61 SMLoc NameLoc, OperandVector &Operands) override;62 ParseStatus parseDirective(AsmToken DirectiveID) override;63 64 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,65 unsigned Kind) override;66 67 // Custom parse functions for VE specific operands.68 ParseStatus parseMEMOperand(OperandVector &Operands);69 ParseStatus parseMEMAsOperand(OperandVector &Operands);70 ParseStatus parseCCOpOperand(OperandVector &Operands);71 ParseStatus parseRDOpOperand(OperandVector &Operands);72 ParseStatus parseMImmOperand(OperandVector &Operands);73 ParseStatus parseOperand(OperandVector &Operands, StringRef Name);74 ParseStatus parseVEAsmOperand(std::unique_ptr<VEOperand> &Operand);75 76 // Helper function to parse expression with a symbol.77 const MCExpr *extractSpecifier(const MCExpr *E, VE::Specifier &Variant);78 bool parseExpression(const MCExpr *&EVal);79 80 // Split the mnemonic stripping conditional code and quantifiers81 StringRef splitMnemonic(StringRef Name, SMLoc NameLoc,82 OperandVector *Operands);83 84 bool parseLiteralValues(unsigned Size, SMLoc L);85 86public:87 VEAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,88 const MCInstrInfo &MII, const MCTargetOptions &Options)89 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {90 // Initialize the set of available features.91 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));92 }93};94 95} // end anonymous namespace96 97static const MCPhysReg I32Regs[64] = {98 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,99 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,100 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,101 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,102 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,103 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,104 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,105 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,106 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,107 VE::SW63};108 109static const MCPhysReg F32Regs[64] = {110 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,111 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,112 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,113 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,114 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,115 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,116 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,117 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,118 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,119 VE::SF63};120 121static const MCPhysReg F128Regs[32] = {122 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,123 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,124 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,125 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};126 127static const MCPhysReg VM512Regs[8] = {VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3,128 VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7};129 130static const MCPhysReg MISCRegs[31] = {131 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,132 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,133 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,134 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,135 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,136 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,137 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,138 VE::PMC12, VE::PMC13, VE::PMC14};139 140namespace {141 142/// VEOperand - Instances of this class represent a parsed VE machine143/// instruction.144class VEOperand : public MCParsedAsmOperand {145private:146 enum KindTy {147 k_Token,148 k_Register,149 k_Immediate,150 // SX-Aurora ASX form is disp(index, base).151 k_MemoryRegRegImm, // base=reg, index=reg, disp=imm152 k_MemoryRegImmImm, // base=reg, index=imm, disp=imm153 k_MemoryZeroRegImm, // base=0, index=reg, disp=imm154 k_MemoryZeroImmImm, // base=0, index=imm, disp=imm155 // SX-Aurora AS form is disp(base).156 k_MemoryRegImm, // base=reg, disp=imm157 k_MemoryZeroImm, // base=0, disp=imm158 // Other special cases for Aurora VE159 k_CCOp, // condition code160 k_RDOp, // rounding mode161 k_MImmOp, // Special immediate value of sequential bit stream of 0 or 1.162 } Kind;163 164 SMLoc StartLoc, EndLoc;165 166 struct Token {167 const char *Data;168 unsigned Length;169 };170 171 struct RegOp {172 MCRegister Reg;173 };174 175 struct ImmOp {176 const MCExpr *Val;177 };178 179 struct MemOp {180 MCRegister Base;181 MCRegister IndexReg;182 const MCExpr *Index;183 const MCExpr *Offset;184 };185 186 struct CCOp {187 unsigned CCVal;188 };189 190 struct RDOp {191 unsigned RDVal;192 };193 194 struct MImmOp {195 const MCExpr *Val;196 bool M0Flag;197 };198 199 union {200 struct Token Tok;201 struct RegOp Reg;202 struct ImmOp Imm;203 struct MemOp Mem;204 struct CCOp CC;205 struct RDOp RD;206 struct MImmOp MImm;207 };208 209public:210 VEOperand(KindTy K) : Kind(K) {}211 212 bool isToken() const override { return Kind == k_Token; }213 bool isReg() const override { return Kind == k_Register; }214 bool isImm() const override { return Kind == k_Immediate; }215 bool isMem() const override {216 return isMEMrri() || isMEMrii() || isMEMzri() || isMEMzii() || isMEMri() ||217 isMEMzi();218 }219 bool isMEMrri() const { return Kind == k_MemoryRegRegImm; }220 bool isMEMrii() const { return Kind == k_MemoryRegImmImm; }221 bool isMEMzri() const { return Kind == k_MemoryZeroRegImm; }222 bool isMEMzii() const { return Kind == k_MemoryZeroImmImm; }223 bool isMEMri() const { return Kind == k_MemoryRegImm; }224 bool isMEMzi() const { return Kind == k_MemoryZeroImm; }225 bool isCCOp() const { return Kind == k_CCOp; }226 bool isRDOp() const { return Kind == k_RDOp; }227 bool isZero() {228 if (!isImm())229 return false;230 231 // Constant case232 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {233 int64_t Value = ConstExpr->getValue();234 return Value == 0;235 }236 return false;237 }238 bool isUImm0to2() {239 if (!isImm())240 return false;241 242 // Constant case243 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {244 int64_t Value = ConstExpr->getValue();245 return Value >= 0 && Value < 3;246 }247 return false;248 }249 bool isUImm1() {250 if (!isImm())251 return false;252 253 // Constant case254 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {255 int64_t Value = ConstExpr->getValue();256 return isUInt<1>(Value);257 }258 return false;259 }260 bool isUImm2() {261 if (!isImm())262 return false;263 264 // Constant case265 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {266 int64_t Value = ConstExpr->getValue();267 return isUInt<2>(Value);268 }269 return false;270 }271 bool isUImm3() {272 if (!isImm())273 return false;274 275 // Constant case276 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {277 int64_t Value = ConstExpr->getValue();278 return isUInt<3>(Value);279 }280 return false;281 }282 bool isUImm4() {283 if (!isImm())284 return false;285 286 // Constant case287 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {288 int64_t Value = ConstExpr->getValue();289 return isUInt<4>(Value);290 }291 return false;292 }293 bool isUImm6() {294 if (!isImm())295 return false;296 297 // Constant case298 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {299 int64_t Value = ConstExpr->getValue();300 return isUInt<6>(Value);301 }302 return false;303 }304 bool isUImm7() {305 if (!isImm())306 return false;307 308 // Constant case309 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {310 int64_t Value = ConstExpr->getValue();311 return isUInt<7>(Value);312 }313 return false;314 }315 bool isSImm7() {316 if (!isImm())317 return false;318 319 // Constant case320 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {321 int64_t Value = ConstExpr->getValue();322 return isInt<7>(Value);323 }324 return false;325 }326 bool isMImm() const {327 if (Kind != k_MImmOp)328 return false;329 330 // Constant case331 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(MImm.Val)) {332 int64_t Value = ConstExpr->getValue();333 return isUInt<6>(Value);334 }335 return false;336 }337 338 StringRef getToken() const {339 assert(Kind == k_Token && "Invalid access!");340 return StringRef(Tok.Data, Tok.Length);341 }342 343 MCRegister getReg() const override {344 assert((Kind == k_Register) && "Invalid access!");345 return Reg.Reg;346 }347 348 const MCExpr *getImm() const {349 assert((Kind == k_Immediate) && "Invalid access!");350 return Imm.Val;351 }352 353 MCRegister getMemBase() const {354 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||355 Kind == k_MemoryRegImm) &&356 "Invalid access!");357 return Mem.Base;358 }359 360 MCRegister getMemIndexReg() const {361 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryZeroRegImm) &&362 "Invalid access!");363 return Mem.IndexReg;364 }365 366 const MCExpr *getMemIndex() const {367 assert((Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm) &&368 "Invalid access!");369 return Mem.Index;370 }371 372 const MCExpr *getMemOffset() const {373 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||374 Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ||375 Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm) &&376 "Invalid access!");377 return Mem.Offset;378 }379 380 void setMemOffset(const MCExpr *off) {381 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||382 Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ||383 Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm) &&384 "Invalid access!");385 Mem.Offset = off;386 }387 388 unsigned getCCVal() const {389 assert((Kind == k_CCOp) && "Invalid access!");390 return CC.CCVal;391 }392 393 unsigned getRDVal() const {394 assert((Kind == k_RDOp) && "Invalid access!");395 return RD.RDVal;396 }397 398 const MCExpr *getMImmVal() const {399 assert((Kind == k_MImmOp) && "Invalid access!");400 return MImm.Val;401 }402 bool getM0Flag() const {403 assert((Kind == k_MImmOp) && "Invalid access!");404 return MImm.M0Flag;405 }406 407 /// getStartLoc - Get the location of the first token of this operand.408 SMLoc getStartLoc() const override { return StartLoc; }409 /// getEndLoc - Get the location of the last token of this operand.410 SMLoc getEndLoc() const override { return EndLoc; }411 412 void print(raw_ostream &OS, const MCAsmInfo &MAI) const override {413 switch (Kind) {414 case k_Token:415 OS << "Token: " << getToken() << "\n";416 break;417 case k_Register:418 OS << "Reg: #" << getReg().id() << "\n";419 break;420 case k_Immediate:421 OS << "Imm: " << getImm() << "\n";422 break;423 case k_MemoryRegRegImm:424 assert(getMemOffset() != nullptr);425 OS << "Mem: #" << getMemBase().id() << "+#" << getMemIndexReg().id()426 << "+";427 MAI.printExpr(OS, *getMemOffset());428 OS << "\n";429 break;430 case k_MemoryRegImmImm:431 assert(getMemIndex() != nullptr && getMemOffset() != nullptr);432 OS << "Mem: #" << getMemBase().id() << "+";433 MAI.printExpr(OS, *getMemIndex());434 OS << "+";435 MAI.printExpr(OS, *getMemOffset());436 OS << "\n";437 break;438 case k_MemoryZeroRegImm:439 assert(getMemOffset() != nullptr);440 OS << "Mem: 0+#" << getMemIndexReg().id() << "+";441 MAI.printExpr(OS, *getMemOffset());442 OS << "\n";443 break;444 case k_MemoryZeroImmImm:445 assert(getMemIndex() != nullptr && getMemOffset() != nullptr);446 OS << "Mem: 0+";447 MAI.printExpr(OS, *getMemIndex());448 OS << "+";449 MAI.printExpr(OS, *getMemOffset());450 OS << "\n";451 break;452 case k_MemoryRegImm:453 assert(getMemOffset() != nullptr);454 OS << "Mem: #" << getMemBase().id() << "+";455 MAI.printExpr(OS, *getMemOffset());456 OS << "\n";457 break;458 case k_MemoryZeroImm:459 assert(getMemOffset() != nullptr);460 OS << "Mem: 0+";461 MAI.printExpr(OS, *getMemOffset());462 OS << "\n";463 break;464 case k_CCOp:465 OS << "CCOp: " << getCCVal() << "\n";466 break;467 case k_RDOp:468 OS << "RDOp: " << getRDVal() << "\n";469 break;470 case k_MImmOp:471 OS << "MImm: (" << getMImmVal() << (getM0Flag() ? ")0" : ")1") << "\n";472 break;473 }474 }475 476 void addRegOperands(MCInst &Inst, unsigned N) const {477 assert(N == 1 && "Invalid number of operands!");478 Inst.addOperand(MCOperand::createReg(getReg()));479 }480 481 void addImmOperands(MCInst &Inst, unsigned N) const {482 assert(N == 1 && "Invalid number of operands!");483 const MCExpr *Expr = getImm();484 addExpr(Inst, Expr);485 }486 487 void addZeroOperands(MCInst &Inst, unsigned N) const {488 addImmOperands(Inst, N);489 }490 491 void addUImm0to2Operands(MCInst &Inst, unsigned N) const {492 addImmOperands(Inst, N);493 }494 495 void addUImm1Operands(MCInst &Inst, unsigned N) const {496 addImmOperands(Inst, N);497 }498 499 void addUImm2Operands(MCInst &Inst, unsigned N) const {500 addImmOperands(Inst, N);501 }502 503 void addUImm3Operands(MCInst &Inst, unsigned N) const {504 addImmOperands(Inst, N);505 }506 507 void addUImm4Operands(MCInst &Inst, unsigned N) const {508 addImmOperands(Inst, N);509 }510 511 void addUImm6Operands(MCInst &Inst, unsigned N) const {512 addImmOperands(Inst, N);513 }514 515 void addUImm7Operands(MCInst &Inst, unsigned N) const {516 addImmOperands(Inst, N);517 }518 519 void addSImm7Operands(MCInst &Inst, unsigned N) const {520 addImmOperands(Inst, N);521 }522 523 void addExpr(MCInst &Inst, const MCExpr *Expr) const {524 // Add as immediate when possible. Null MCExpr = 0.525 if (!Expr)526 Inst.addOperand(MCOperand::createImm(0));527 else if (const auto *CE = dyn_cast<MCConstantExpr>(Expr))528 Inst.addOperand(MCOperand::createImm(CE->getValue()));529 else530 Inst.addOperand(MCOperand::createExpr(Expr));531 }532 533 void addMEMrriOperands(MCInst &Inst, unsigned N) const {534 assert(N == 3 && "Invalid number of operands!");535 536 Inst.addOperand(MCOperand::createReg(getMemBase()));537 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));538 addExpr(Inst, getMemOffset());539 }540 541 void addMEMriiOperands(MCInst &Inst, unsigned N) const {542 assert(N == 3 && "Invalid number of operands!");543 544 Inst.addOperand(MCOperand::createReg(getMemBase()));545 addExpr(Inst, getMemIndex());546 addExpr(Inst, getMemOffset());547 }548 549 void addMEMzriOperands(MCInst &Inst, unsigned N) const {550 assert(N == 3 && "Invalid number of operands!");551 552 Inst.addOperand(MCOperand::createImm(0));553 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));554 addExpr(Inst, getMemOffset());555 }556 557 void addMEMziiOperands(MCInst &Inst, unsigned N) const {558 assert(N == 3 && "Invalid number of operands!");559 560 Inst.addOperand(MCOperand::createImm(0));561 addExpr(Inst, getMemIndex());562 addExpr(Inst, getMemOffset());563 }564 565 void addMEMriOperands(MCInst &Inst, unsigned N) const {566 assert(N == 2 && "Invalid number of operands!");567 568 Inst.addOperand(MCOperand::createReg(getMemBase()));569 addExpr(Inst, getMemOffset());570 }571 572 void addMEMziOperands(MCInst &Inst, unsigned N) const {573 assert(N == 2 && "Invalid number of operands!");574 575 Inst.addOperand(MCOperand::createImm(0));576 addExpr(Inst, getMemOffset());577 }578 579 void addCCOpOperands(MCInst &Inst, unsigned N) const {580 assert(N == 1 && "Invalid number of operands!");581 582 Inst.addOperand(MCOperand::createImm(getCCVal()));583 }584 585 void addRDOpOperands(MCInst &Inst, unsigned N) const {586 assert(N == 1 && "Invalid number of operands!");587 588 Inst.addOperand(MCOperand::createImm(getRDVal()));589 }590 591 void addMImmOperands(MCInst &Inst, unsigned N) const {592 assert(N == 1 && "Invalid number of operands!");593 const auto *ConstExpr = dyn_cast<MCConstantExpr>(getMImmVal());594 assert(ConstExpr && "Null operands!");595 int64_t Value = ConstExpr->getValue();596 if (getM0Flag())597 Value += 64;598 Inst.addOperand(MCOperand::createImm(Value));599 }600 601 static std::unique_ptr<VEOperand> CreateToken(StringRef Str, SMLoc S) {602 auto Op = std::make_unique<VEOperand>(k_Token);603 Op->Tok.Data = Str.data();604 Op->Tok.Length = Str.size();605 Op->StartLoc = S;606 Op->EndLoc = S;607 return Op;608 }609 610 static std::unique_ptr<VEOperand> CreateReg(MCRegister Reg, SMLoc S,611 SMLoc E) {612 auto Op = std::make_unique<VEOperand>(k_Register);613 Op->Reg.Reg = Reg;614 Op->StartLoc = S;615 Op->EndLoc = E;616 return Op;617 }618 619 static std::unique_ptr<VEOperand> CreateImm(const MCExpr *Val, SMLoc S,620 SMLoc E) {621 auto Op = std::make_unique<VEOperand>(k_Immediate);622 Op->Imm.Val = Val;623 Op->StartLoc = S;624 Op->EndLoc = E;625 return Op;626 }627 628 static std::unique_ptr<VEOperand> CreateCCOp(unsigned CCVal, SMLoc S,629 SMLoc E) {630 auto Op = std::make_unique<VEOperand>(k_CCOp);631 Op->CC.CCVal = CCVal;632 Op->StartLoc = S;633 Op->EndLoc = E;634 return Op;635 }636 637 static std::unique_ptr<VEOperand> CreateRDOp(unsigned RDVal, SMLoc S,638 SMLoc E) {639 auto Op = std::make_unique<VEOperand>(k_RDOp);640 Op->RD.RDVal = RDVal;641 Op->StartLoc = S;642 Op->EndLoc = E;643 return Op;644 }645 646 static std::unique_ptr<VEOperand> CreateMImm(const MCExpr *Val, bool Flag,647 SMLoc S, SMLoc E) {648 auto Op = std::make_unique<VEOperand>(k_MImmOp);649 Op->MImm.Val = Val;650 Op->MImm.M0Flag = Flag;651 Op->StartLoc = S;652 Op->EndLoc = E;653 return Op;654 }655 656 static bool MorphToI32Reg(VEOperand &Op) {657 MCRegister Reg = Op.getReg();658 unsigned regIdx = Reg - VE::SX0;659 if (regIdx > 63)660 return false;661 Op.Reg.Reg = I32Regs[regIdx];662 return true;663 }664 665 static bool MorphToF32Reg(VEOperand &Op) {666 MCRegister Reg = Op.getReg();667 unsigned regIdx = Reg - VE::SX0;668 if (regIdx > 63)669 return false;670 Op.Reg.Reg = F32Regs[regIdx];671 return true;672 }673 674 static bool MorphToF128Reg(VEOperand &Op) {675 MCRegister Reg = Op.getReg();676 unsigned regIdx = Reg - VE::SX0;677 if (regIdx % 2 || regIdx > 63)678 return false;679 Op.Reg.Reg = F128Regs[regIdx / 2];680 return true;681 }682 683 static bool MorphToVM512Reg(VEOperand &Op) {684 MCRegister Reg = Op.getReg();685 unsigned regIdx = Reg - VE::VM0;686 if (regIdx % 2 || regIdx > 15)687 return false;688 Op.Reg.Reg = VM512Regs[regIdx / 2];689 return true;690 }691 692 static bool MorphToMISCReg(VEOperand &Op) {693 const auto *ConstExpr = dyn_cast<MCConstantExpr>(Op.getImm());694 if (!ConstExpr)695 return false;696 unsigned regIdx = ConstExpr->getValue();697 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)698 return false;699 Op.Kind = k_Register;700 Op.Reg.Reg = MISCRegs[regIdx];701 return true;702 }703 704 static std::unique_ptr<VEOperand>705 MorphToMEMri(MCRegister Base, std::unique_ptr<VEOperand> Op) {706 const MCExpr *Imm = Op->getImm();707 Op->Kind = k_MemoryRegImm;708 Op->Mem.Base = Base;709 Op->Mem.IndexReg = MCRegister();710 Op->Mem.Index = nullptr;711 Op->Mem.Offset = Imm;712 return Op;713 }714 715 static std::unique_ptr<VEOperand>716 MorphToMEMzi(std::unique_ptr<VEOperand> Op) {717 const MCExpr *Imm = Op->getImm();718 Op->Kind = k_MemoryZeroImm;719 Op->Mem.Base = MCRegister();720 Op->Mem.IndexReg = MCRegister();721 Op->Mem.Index = nullptr;722 Op->Mem.Offset = Imm;723 return Op;724 }725 726 static std::unique_ptr<VEOperand>727 MorphToMEMrri(MCRegister Base, MCRegister Index,728 std::unique_ptr<VEOperand> Op) {729 const MCExpr *Imm = Op->getImm();730 Op->Kind = k_MemoryRegRegImm;731 Op->Mem.Base = Base;732 Op->Mem.IndexReg = Index;733 Op->Mem.Index = nullptr;734 Op->Mem.Offset = Imm;735 return Op;736 }737 738 static std::unique_ptr<VEOperand>739 MorphToMEMrii(MCRegister Base, const MCExpr *Index,740 std::unique_ptr<VEOperand> Op) {741 const MCExpr *Imm = Op->getImm();742 Op->Kind = k_MemoryRegImmImm;743 Op->Mem.Base = Base;744 Op->Mem.IndexReg = MCRegister();745 Op->Mem.Index = Index;746 Op->Mem.Offset = Imm;747 return Op;748 }749 750 static std::unique_ptr<VEOperand>751 MorphToMEMzri(MCRegister Index, std::unique_ptr<VEOperand> Op) {752 const MCExpr *Imm = Op->getImm();753 Op->Kind = k_MemoryZeroRegImm;754 Op->Mem.Base = MCRegister();755 Op->Mem.IndexReg = Index;756 Op->Mem.Index = nullptr;757 Op->Mem.Offset = Imm;758 return Op;759 }760 761 static std::unique_ptr<VEOperand>762 MorphToMEMzii(const MCExpr *Index, std::unique_ptr<VEOperand> Op) {763 const MCExpr *Imm = Op->getImm();764 Op->Kind = k_MemoryZeroImmImm;765 Op->Mem.Base = MCRegister();766 Op->Mem.IndexReg = MCRegister();767 Op->Mem.Index = Index;768 Op->Mem.Offset = Imm;769 return Op;770 }771};772 773} // end anonymous namespace774 775bool VEAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,776 OperandVector &Operands,777 MCStreamer &Out, uint64_t &ErrorInfo,778 bool MatchingInlineAsm) {779 MCInst Inst;780 unsigned MatchResult =781 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);782 switch (MatchResult) {783 case Match_Success:784 Inst.setLoc(IDLoc);785 Out.emitInstruction(Inst, getSTI());786 return false;787 788 case Match_MissingFeature:789 return Error(IDLoc,790 "instruction requires a CPU feature not currently enabled");791 792 case Match_InvalidOperand: {793 SMLoc ErrorLoc = IDLoc;794 if (ErrorInfo != ~0ULL) {795 if (ErrorInfo >= Operands.size())796 return Error(IDLoc, "too few operands for instruction");797 798 ErrorLoc = ((VEOperand &)*Operands[ErrorInfo]).getStartLoc();799 if (ErrorLoc == SMLoc())800 ErrorLoc = IDLoc;801 }802 803 return Error(ErrorLoc, "invalid operand for instruction");804 }805 case Match_MnemonicFail:806 return Error(IDLoc, "invalid instruction mnemonic");807 }808 llvm_unreachable("Implement any new match types added!");809}810 811bool VEAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,812 SMLoc &EndLoc) {813 if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())814 return Error(StartLoc, "invalid register name");815 return false;816}817 818/// Parses a register name using a given matching function.819/// Checks for lowercase or uppercase if necessary.820MCRegister VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {821 StringRef Name = Parser.getTok().getString();822 823 MCRegister RegNum = matchFn(Name);824 825 // GCC supports case insensitive register names. All of the VE registers826 // are all lower case.827 if (!RegNum) {828 RegNum = matchFn(Name.lower());829 }830 831 return RegNum;832}833 834/// Maps from the set of all register names to a register number.835/// \note Generated by TableGen.836static MCRegister MatchRegisterName(StringRef Name);837 838/// Maps from the set of all alternative registernames to a register number.839/// \note Generated by TableGen.840static MCRegister MatchRegisterAltName(StringRef Name);841 842ParseStatus VEAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,843 SMLoc &EndLoc) {844 const AsmToken Tok = Parser.getTok();845 StartLoc = Tok.getLoc();846 EndLoc = Tok.getEndLoc();847 Reg = VE::NoRegister;848 if (getLexer().getKind() != AsmToken::Percent)849 return ParseStatus::NoMatch;850 Parser.Lex();851 852 Reg = parseRegisterName(&MatchRegisterName);853 if (Reg == VE::NoRegister)854 Reg = parseRegisterName(&MatchRegisterAltName);855 856 if (Reg != VE::NoRegister) {857 Parser.Lex();858 return ParseStatus::Success;859 }860 861 getLexer().UnLex(Tok);862 return ParseStatus::NoMatch;863}864 865static StringRef parseCC(StringRef Name, unsigned Prefix, unsigned Suffix,866 bool IntegerCC, bool OmitCC, SMLoc NameLoc,867 OperandVector *Operands) {868 // Parse instructions with a conditional code. For example, 'bne' is869 // converted into two operands 'b' and 'ne'.870 StringRef Cond = Name.slice(Prefix, Suffix);871 VECC::CondCode CondCode =872 IntegerCC ? stringToVEICondCode(Cond) : stringToVEFCondCode(Cond);873 874 // If OmitCC is enabled, CC_AT and CC_AF is treated as a part of mnemonic.875 if (CondCode != VECC::UNKNOWN &&876 (!OmitCC || (CondCode != VECC::CC_AT && CondCode != VECC::CC_AF))) {877 StringRef SuffixStr = Name.substr(Suffix);878 // Push "b".879 Name = Name.slice(0, Prefix);880 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));881 // Push $cond part.882 SMLoc CondLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Prefix);883 SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Suffix);884 Operands->push_back(VEOperand::CreateCCOp(CondCode, CondLoc, SuffixLoc));885 // push suffix like ".l.t"886 if (!SuffixStr.empty())887 Operands->push_back(VEOperand::CreateToken(SuffixStr, SuffixLoc));888 } else {889 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));890 }891 return Name;892}893 894static StringRef parseRD(StringRef Name, unsigned Prefix, SMLoc NameLoc,895 OperandVector *Operands) {896 // Parse instructions with a conditional code. For example, 'cvt.w.d.sx.rz'897 // is converted into two operands 'cvt.w.d.sx' and '.rz'.898 StringRef RD = Name.substr(Prefix);899 VERD::RoundingMode RoundingMode = stringToVERD(RD);900 901 if (RoundingMode != VERD::UNKNOWN) {902 Name = Name.slice(0, Prefix);903 // push 1st like `cvt.w.d.sx`904 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));905 SMLoc SuffixLoc =906 SMLoc::getFromPointer(NameLoc.getPointer() + (RD.data() - Name.data()));907 SMLoc SuffixEnd =908 SMLoc::getFromPointer(NameLoc.getPointer() + (RD.end() - Name.data()));909 // push $round if it has rounding mode910 Operands->push_back(911 VEOperand::CreateRDOp(RoundingMode, SuffixLoc, SuffixEnd));912 } else {913 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));914 }915 return Name;916}917 918// Split the mnemonic into ASM operand, conditional code and instruction919// qualifier (half-word, byte).920StringRef VEAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,921 OperandVector *Operands) {922 // Create the leading tokens for the mnemonic923 StringRef Mnemonic = Name;924 925 if (Name[0] == 'b') {926 // Match b?? or br??.927 size_t Start = 1;928 size_t Next = Name.find('.');929 // Adjust position of CondCode.930 if (Name.size() > 1 && Name[1] == 'r')931 Start = 2;932 // Check suffix.933 bool ICC = true;934 if (Next + 1 < Name.size() &&935 (Name[Next + 1] == 'd' || Name[Next + 1] == 's'))936 ICC = false;937 Mnemonic = parseCC(Name, Start, Next, ICC, true, NameLoc, Operands);938 } else if (Name.starts_with("cmov.l.") || Name.starts_with("cmov.w.") ||939 Name.starts_with("cmov.d.") || Name.starts_with("cmov.s.")) {940 bool ICC = Name[5] == 'l' || Name[5] == 'w';941 Mnemonic = parseCC(Name, 7, Name.size(), ICC, false, NameLoc, Operands);942 } else if (Name.starts_with("cvt.w.d.sx") || Name.starts_with("cvt.w.d.zx") ||943 Name.starts_with("cvt.w.s.sx") || Name.starts_with("cvt.w.s.zx")) {944 Mnemonic = parseRD(Name, 10, NameLoc, Operands);945 } else if (Name.starts_with("cvt.l.d")) {946 Mnemonic = parseRD(Name, 7, NameLoc, Operands);947 } else if (Name.starts_with("vcvt.w.d.sx") ||948 Name.starts_with("vcvt.w.d.zx") ||949 Name.starts_with("vcvt.w.s.sx") ||950 Name.starts_with("vcvt.w.s.zx")) {951 Mnemonic = parseRD(Name, 11, NameLoc, Operands);952 } else if (Name.starts_with("vcvt.l.d")) {953 Mnemonic = parseRD(Name, 8, NameLoc, Operands);954 } else if (Name.starts_with("pvcvt.w.s.lo") ||955 Name.starts_with("pvcvt.w.s.up")) {956 Mnemonic = parseRD(Name, 12, NameLoc, Operands);957 } else if (Name.starts_with("pvcvt.w.s")) {958 Mnemonic = parseRD(Name, 9, NameLoc, Operands);959 } else if (Name.starts_with("vfmk.l.") || Name.starts_with("vfmk.w.") ||960 Name.starts_with("vfmk.d.") || Name.starts_with("vfmk.s.")) {961 bool ICC = Name[5] == 'l' || Name[5] == 'w' ? true : false;962 Mnemonic = parseCC(Name, 7, Name.size(), ICC, true, NameLoc, Operands);963 } else if (Name.starts_with("pvfmk.w.lo.") ||964 Name.starts_with("pvfmk.w.up.") ||965 Name.starts_with("pvfmk.s.lo.") ||966 Name.starts_with("pvfmk.s.up.")) {967 bool ICC = Name[6] == 'l' || Name[6] == 'w' ? true : false;968 Mnemonic = parseCC(Name, 11, Name.size(), ICC, true, NameLoc, Operands);969 } else {970 Operands->push_back(VEOperand::CreateToken(Mnemonic, NameLoc));971 }972 973 return Mnemonic;974}975 976static void applyMnemonicAliases(StringRef &Mnemonic,977 const FeatureBitset &Features,978 unsigned VariantID);979 980bool VEAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,981 SMLoc NameLoc, OperandVector &Operands) {982 // If the target architecture uses MnemonicAlias, call it here to parse983 // operands correctly.984 applyMnemonicAliases(Name, getAvailableFeatures(), 0);985 986 // Split name to first token and the rest, e.g. "bgt.l.t" to "b", "gt", and987 // ".l.t". We treat "b" as a mnemonic, "gt" as first operand, and ".l.t"988 // as second operand.989 StringRef Mnemonic = splitMnemonic(Name, NameLoc, &Operands);990 991 if (getLexer().isNot(AsmToken::EndOfStatement)) {992 // Read the first operand.993 if (!parseOperand(Operands, Mnemonic).isSuccess()) {994 SMLoc Loc = getLexer().getLoc();995 return Error(Loc, "unexpected token");996 }997 998 while (getLexer().is(AsmToken::Comma)) {999 Parser.Lex(); // Eat the comma.1000 // Parse and remember the operand.1001 if (!parseOperand(Operands, Mnemonic).isSuccess()) {1002 SMLoc Loc = getLexer().getLoc();1003 return Error(Loc, "unexpected token");1004 }1005 }1006 }1007 if (getLexer().isNot(AsmToken::EndOfStatement)) {1008 SMLoc Loc = getLexer().getLoc();1009 return Error(Loc, "unexpected token");1010 }1011 Parser.Lex(); // Consume the EndOfStatement.1012 return false;1013}1014 1015ParseStatus VEAsmParser::parseDirective(AsmToken DirectiveID) {1016 std::string IDVal = DirectiveID.getIdentifier().lower();1017 1018 // Defines VE specific directives. Reference is "Vector Engine Assembly1019 // Language Reference Manual":1020 // https://www.hpc.nec/documents/sdk/pdfs/VectorEngine-as-manual-v1.3.pdf1021 1022 // The .word is 4 bytes long on VE.1023 if (IDVal == ".word")1024 return parseLiteralValues(4, DirectiveID.getLoc());1025 1026 // The .long is 8 bytes long on VE.1027 if (IDVal == ".long")1028 return parseLiteralValues(8, DirectiveID.getLoc());1029 1030 // The .llong is 8 bytes long on VE.1031 if (IDVal == ".llong")1032 return parseLiteralValues(8, DirectiveID.getLoc());1033 1034 // Let the MC layer to handle other directives.1035 return ParseStatus::NoMatch;1036}1037 1038/// parseLiteralValues1039/// ::= .word expression [, expression]*1040/// ::= .long expression [, expression]*1041/// ::= .llong expression [, expression]*1042bool VEAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {1043 auto parseOne = [&]() -> bool {1044 const MCExpr *Value;1045 if (getParser().parseExpression(Value))1046 return true;1047 getParser().getStreamer().emitValue(Value, Size, L);1048 return false;1049 };1050 return (parseMany(parseOne));1051}1052 1053/// Extract \code @lo32/@hi32/etc \endcode specifier from expression.1054/// Recursively scan the expression and check for VK_HI32/LO32/etc1055/// symbol variants. If all symbols with modifier use the same1056/// variant, return the corresponding VE::Specifier,1057/// and a modified expression using the default symbol variant.1058/// Otherwise, return NULL.1059const MCExpr *VEAsmParser::extractSpecifier(const MCExpr *E,1060 VE::Specifier &Variant) {1061 MCContext &Context = getParser().getContext();1062 Variant = VE::S_None;1063 1064 switch (E->getKind()) {1065 case MCExpr::Target:1066 case MCExpr::Constant:1067 return nullptr;1068 case MCExpr::Specifier:1069 llvm_unreachable("unused by this backend");1070 1071 case MCExpr::SymbolRef: {1072 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);1073 1074 switch (SRE->getSpecifier()) {1075 case VE::S_None:1076 // Use VK_REFLONG to a symbol without modifiers.1077 Variant = VE::S_REFLONG;1078 break;1079 case VE::S_HI32:1080 Variant = VE::S_HI32;1081 break;1082 case VE::S_LO32:1083 Variant = VE::S_LO32;1084 break;1085 case VE::S_PC_HI32:1086 Variant = VE::S_PC_HI32;1087 break;1088 case VE::S_PC_LO32:1089 Variant = VE::S_PC_LO32;1090 break;1091 case VE::S_GOT_HI32:1092 Variant = VE::S_GOT_HI32;1093 break;1094 case VE::S_GOT_LO32:1095 Variant = VE::S_GOT_LO32;1096 break;1097 case VE::S_GOTOFF_HI32:1098 Variant = VE::S_GOTOFF_HI32;1099 break;1100 case VE::S_GOTOFF_LO32:1101 Variant = VE::S_GOTOFF_LO32;1102 break;1103 case VE::S_PLT_HI32:1104 Variant = VE::S_PLT_HI32;1105 break;1106 case VE::S_PLT_LO32:1107 Variant = VE::S_PLT_LO32;1108 break;1109 case VE::S_TLS_GD_HI32:1110 Variant = VE::S_TLS_GD_HI32;1111 break;1112 case VE::S_TLS_GD_LO32:1113 Variant = VE::S_TLS_GD_LO32;1114 break;1115 case VE::S_TPOFF_HI32:1116 Variant = VE::S_TPOFF_HI32;1117 break;1118 case VE::S_TPOFF_LO32:1119 Variant = VE::S_TPOFF_LO32;1120 break;1121 default:1122 return nullptr;1123 }1124 1125 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);1126 }1127 1128 case MCExpr::Unary: {1129 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);1130 const MCExpr *Sub = extractSpecifier(UE->getSubExpr(), Variant);1131 if (!Sub)1132 return nullptr;1133 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);1134 }1135 1136 case MCExpr::Binary: {1137 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);1138 VE::Specifier LHSVariant, RHSVariant;1139 const MCExpr *LHS = extractSpecifier(BE->getLHS(), LHSVariant);1140 const MCExpr *RHS = extractSpecifier(BE->getRHS(), RHSVariant);1141 1142 if (!LHS && !RHS)1143 return nullptr;1144 1145 if (!LHS)1146 LHS = BE->getLHS();1147 if (!RHS)1148 RHS = BE->getRHS();1149 1150 if (LHSVariant == VE::S_None)1151 Variant = RHSVariant;1152 else if (RHSVariant == VE::S_None)1153 Variant = LHSVariant;1154 else if (LHSVariant == RHSVariant)1155 Variant = LHSVariant;1156 else1157 return nullptr;1158 1159 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);1160 }1161 }1162 1163 llvm_unreachable("Invalid expression kind!");1164}1165 1166/// This differs from the default "parseExpression" in that it handles1167/// relocation specifiers.1168bool VEAsmParser::parseExpression(const MCExpr *&EVal) {1169 // Handle \code symbol @lo32/@hi32/etc \endcode.1170 if (getParser().parseExpression(EVal))1171 return true;1172 1173 // Convert MCSymbolRefExpr with specifier to MCSpecifierExpr.1174 VE::Specifier Specifier;1175 const MCExpr *E = extractSpecifier(EVal, Specifier);1176 if (E)1177 EVal = MCSpecifierExpr::create(E, Specifier, getParser().getContext());1178 1179 return false;1180}1181 1182ParseStatus VEAsmParser::parseMEMOperand(OperandVector &Operands) {1183 LLVM_DEBUG(dbgs() << "parseMEMOperand\n");1184 const AsmToken &Tok = Parser.getTok();1185 SMLoc S = Tok.getLoc();1186 SMLoc E = Tok.getEndLoc();1187 // Parse ASX format1188 // disp1189 // disp(, base)1190 // disp(index)1191 // disp(index, base)1192 // (, base)1193 // (index)1194 // (index, base)1195 1196 std::unique_ptr<VEOperand> Offset;1197 switch (getLexer().getKind()) {1198 default:1199 return ParseStatus::NoMatch;1200 1201 case AsmToken::Minus:1202 case AsmToken::Integer:1203 case AsmToken::Dot:1204 case AsmToken::Identifier: {1205 const MCExpr *EVal;1206 if (!parseExpression(EVal))1207 Offset = VEOperand::CreateImm(EVal, S, E);1208 else1209 return ParseStatus::NoMatch;1210 break;1211 }1212 1213 case AsmToken::LParen:1214 // empty disp (= 0)1215 Offset =1216 VEOperand::CreateImm(MCConstantExpr::create(0, getContext()), S, E);1217 break;1218 }1219 1220 switch (getLexer().getKind()) {1221 default:1222 return ParseStatus::Failure;1223 1224 case AsmToken::EndOfStatement:1225 Operands.push_back(VEOperand::MorphToMEMzii(1226 MCConstantExpr::create(0, getContext()), std::move(Offset)));1227 return ParseStatus::Success;1228 1229 case AsmToken::LParen:1230 Parser.Lex(); // Eat the (1231 break;1232 }1233 1234 const MCExpr *IndexValue = nullptr;1235 MCRegister IndexReg;1236 1237 switch (getLexer().getKind()) {1238 default:1239 if (parseRegister(IndexReg, S, E))1240 return ParseStatus::Failure;1241 break;1242 1243 case AsmToken::Minus:1244 case AsmToken::Integer:1245 case AsmToken::Dot:1246 if (getParser().parseExpression(IndexValue, E))1247 return ParseStatus::Failure;1248 break;1249 1250 case AsmToken::Comma:1251 // empty index1252 IndexValue = MCConstantExpr::create(0, getContext());1253 break;1254 }1255 1256 switch (getLexer().getKind()) {1257 default:1258 return ParseStatus::Failure;1259 1260 case AsmToken::RParen:1261 Parser.Lex(); // Eat the )1262 Operands.push_back(1263 IndexValue ? VEOperand::MorphToMEMzii(IndexValue, std::move(Offset))1264 : VEOperand::MorphToMEMzri(IndexReg, std::move(Offset)));1265 return ParseStatus::Success;1266 1267 case AsmToken::Comma:1268 Parser.Lex(); // Eat the ,1269 break;1270 }1271 1272 MCRegister BaseReg;1273 if (parseRegister(BaseReg, S, E))1274 return ParseStatus::Failure;1275 1276 if (!Parser.getTok().is(AsmToken::RParen))1277 return ParseStatus::Failure;1278 1279 Parser.Lex(); // Eat the )1280 Operands.push_back(1281 IndexValue1282 ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset))1283 : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset)));1284 1285 return ParseStatus::Success;1286}1287 1288ParseStatus VEAsmParser::parseMEMAsOperand(OperandVector &Operands) {1289 LLVM_DEBUG(dbgs() << "parseMEMAsOperand\n");1290 const AsmToken &Tok = Parser.getTok();1291 SMLoc S = Tok.getLoc();1292 SMLoc E = Tok.getEndLoc();1293 // Parse AS format1294 // disp1295 // disp(, base)1296 // disp(base)1297 // disp()1298 // (, base)1299 // (base)1300 // base1301 1302 MCRegister BaseReg;1303 std::unique_ptr<VEOperand> Offset;1304 switch (getLexer().getKind()) {1305 default:1306 return ParseStatus::NoMatch;1307 1308 case AsmToken::Minus:1309 case AsmToken::Integer:1310 case AsmToken::Dot:1311 case AsmToken::Identifier: {1312 const MCExpr *EVal;1313 if (!parseExpression(EVal))1314 Offset = VEOperand::CreateImm(EVal, S, E);1315 else1316 return ParseStatus::NoMatch;1317 break;1318 }1319 1320 case AsmToken::Percent:1321 if (parseRegister(BaseReg, S, E))1322 return ParseStatus::NoMatch;1323 Offset =1324 VEOperand::CreateImm(MCConstantExpr::create(0, getContext()), S, E);1325 break;1326 1327 case AsmToken::LParen:1328 // empty disp (= 0)1329 Offset =1330 VEOperand::CreateImm(MCConstantExpr::create(0, getContext()), S, E);1331 break;1332 }1333 1334 switch (getLexer().getKind()) {1335 default:1336 return ParseStatus::Failure;1337 1338 case AsmToken::EndOfStatement:1339 case AsmToken::Comma:1340 Operands.push_back(BaseReg != VE::NoRegister1341 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset))1342 : VEOperand::MorphToMEMzi(std::move(Offset)));1343 return ParseStatus::Success;1344 1345 case AsmToken::LParen:1346 if (BaseReg != VE::NoRegister)1347 return ParseStatus::Failure;1348 Parser.Lex(); // Eat the (1349 break;1350 }1351 1352 switch (getLexer().getKind()) {1353 default:1354 if (parseRegister(BaseReg, S, E))1355 return ParseStatus::Failure;1356 break;1357 1358 case AsmToken::Comma:1359 Parser.Lex(); // Eat the ,1360 if (parseRegister(BaseReg, S, E))1361 return ParseStatus::Failure;1362 break;1363 1364 case AsmToken::RParen:1365 break;1366 }1367 1368 if (!Parser.getTok().is(AsmToken::RParen))1369 return ParseStatus::Failure;1370 1371 Parser.Lex(); // Eat the )1372 Operands.push_back(BaseReg != VE::NoRegister1373 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset))1374 : VEOperand::MorphToMEMzi(std::move(Offset)));1375 1376 return ParseStatus::Success;1377}1378 1379ParseStatus VEAsmParser::parseMImmOperand(OperandVector &Operands) {1380 LLVM_DEBUG(dbgs() << "parseMImmOperand\n");1381 1382 // Parsing "(" + number + ")0/1"1383 const AsmToken Tok1 = Parser.getTok();1384 if (!Tok1.is(AsmToken::LParen))1385 return ParseStatus::NoMatch;1386 1387 Parser.Lex(); // Eat the '('.1388 1389 const AsmToken Tok2 = Parser.getTok();1390 SMLoc E;1391 const MCExpr *EVal;1392 if (!Tok2.is(AsmToken::Integer) || getParser().parseExpression(EVal, E)) {1393 getLexer().UnLex(Tok1);1394 return ParseStatus::NoMatch;1395 }1396 1397 const AsmToken Tok3 = Parser.getTok();1398 if (!Tok3.is(AsmToken::RParen)) {1399 getLexer().UnLex(Tok2);1400 getLexer().UnLex(Tok1);1401 return ParseStatus::NoMatch;1402 }1403 Parser.Lex(); // Eat the ')'.1404 1405 const AsmToken &Tok4 = Parser.getTok();1406 StringRef Suffix = Tok4.getString();1407 if (Suffix != "1" && Suffix != "0") {1408 getLexer().UnLex(Tok3);1409 getLexer().UnLex(Tok2);1410 getLexer().UnLex(Tok1);1411 return ParseStatus::NoMatch;1412 }1413 Parser.Lex(); // Eat the value.1414 SMLoc EndLoc = SMLoc::getFromPointer(Suffix.end());1415 Operands.push_back(1416 VEOperand::CreateMImm(EVal, Suffix == "0", Tok1.getLoc(), EndLoc));1417 return ParseStatus::Success;1418}1419 1420ParseStatus VEAsmParser::parseOperand(OperandVector &Operands,1421 StringRef Mnemonic) {1422 LLVM_DEBUG(dbgs() << "parseOperand\n");1423 ParseStatus Res = MatchOperandParserImpl(Operands, Mnemonic);1424 1425 // If there wasn't a custom match, try the generic matcher below. Otherwise,1426 // there was a match, but an error occurred, in which case, just return that1427 // the operand parsing failed.1428 if (Res.isSuccess() || Res.isFailure())1429 return Res;1430 1431 switch (getLexer().getKind()) {1432 case AsmToken::LParen: {1433 // Parsing "(" + %vreg + ", " + %vreg + ")"1434 const AsmToken Tok1 = Parser.getTok();1435 Parser.Lex(); // Eat the '('.1436 1437 MCRegister Reg1;1438 SMLoc S1, E1;1439 if (!tryParseRegister(Reg1, S1, E1).isSuccess()) {1440 getLexer().UnLex(Tok1);1441 return ParseStatus::NoMatch;1442 }1443 1444 if (!Parser.getTok().is(AsmToken::Comma))1445 return ParseStatus::Failure;1446 Parser.Lex(); // Eat the ','.1447 1448 MCRegister Reg2;1449 SMLoc S2, E2;1450 if (!tryParseRegister(Reg2, S2, E2).isSuccess())1451 return ParseStatus::Failure;1452 1453 if (!Parser.getTok().is(AsmToken::RParen))1454 return ParseStatus::Failure;1455 1456 Operands.push_back(VEOperand::CreateToken(Tok1.getString(), Tok1.getLoc()));1457 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1));1458 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2));1459 Operands.push_back(VEOperand::CreateToken(Parser.getTok().getString(),1460 Parser.getTok().getLoc()));1461 Parser.Lex(); // Eat the ')'.1462 break;1463 }1464 default: {1465 std::unique_ptr<VEOperand> Op;1466 Res = parseVEAsmOperand(Op);1467 if (!Res.isSuccess() || !Op)1468 return ParseStatus::Failure;1469 1470 // Push the parsed operand into the list of operands1471 Operands.push_back(std::move(Op));1472 1473 if (!Parser.getTok().is(AsmToken::LParen))1474 break;1475 1476 // Parsing %vec-reg + "(" + %sclar-reg/number + ")"1477 std::unique_ptr<VEOperand> Op1 = VEOperand::CreateToken(1478 Parser.getTok().getString(), Parser.getTok().getLoc());1479 Parser.Lex(); // Eat the '('.1480 1481 std::unique_ptr<VEOperand> Op2;1482 Res = parseVEAsmOperand(Op2);1483 if (!Res.isSuccess() || !Op2)1484 return ParseStatus::Failure;1485 1486 if (!Parser.getTok().is(AsmToken::RParen))1487 return ParseStatus::Failure;1488 1489 Operands.push_back(std::move(Op1));1490 Operands.push_back(std::move(Op2));1491 Operands.push_back(VEOperand::CreateToken(Parser.getTok().getString(),1492 Parser.getTok().getLoc()));1493 Parser.Lex(); // Eat the ')'.1494 break;1495 }1496 }1497 1498 return ParseStatus::Success;1499}1500 1501ParseStatus VEAsmParser::parseVEAsmOperand(std::unique_ptr<VEOperand> &Op) {1502 LLVM_DEBUG(dbgs() << "parseVEAsmOperand\n");1503 SMLoc S = Parser.getTok().getLoc();1504 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);1505 const MCExpr *EVal;1506 1507 Op = nullptr;1508 switch (getLexer().getKind()) {1509 default:1510 break;1511 1512 case AsmToken::Percent: {1513 MCRegister Reg;1514 if (tryParseRegister(Reg, S, E).isSuccess())1515 Op = VEOperand::CreateReg(Reg, S, E);1516 break;1517 }1518 case AsmToken::Minus:1519 case AsmToken::Integer:1520 case AsmToken::Dot:1521 case AsmToken::Identifier:1522 if (!parseExpression(EVal))1523 Op = VEOperand::CreateImm(EVal, S, E);1524 break;1525 }1526 return Op ? ParseStatus::Success : ParseStatus::Failure;1527}1528 1529// Force static initialization.1530extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmParser() {1531 RegisterMCAsmParser<VEAsmParser> A(getTheVETarget());1532}1533 1534#define GET_REGISTER_MATCHER1535#define GET_MATCHER_IMPLEMENTATION1536#include "VEGenAsmMatcher.inc"1537 1538unsigned VEAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,1539 unsigned Kind) {1540 VEOperand &Op = (VEOperand &)GOp;1541 1542 // VE uses identical register name for all registers like both1543 // F32 and I32 uses "%s23". Need to convert the name of them1544 // for validation.1545 switch (Kind) {1546 default:1547 break;1548 case MCK_F32:1549 if (Op.isReg() && VEOperand::MorphToF32Reg(Op))1550 return MCTargetAsmParser::Match_Success;1551 break;1552 case MCK_I32:1553 if (Op.isReg() && VEOperand::MorphToI32Reg(Op))1554 return MCTargetAsmParser::Match_Success;1555 break;1556 case MCK_F128:1557 if (Op.isReg() && VEOperand::MorphToF128Reg(Op))1558 return MCTargetAsmParser::Match_Success;1559 break;1560 case MCK_VM512:1561 if (Op.isReg() && VEOperand::MorphToVM512Reg(Op))1562 return MCTargetAsmParser::Match_Success;1563 break;1564 case MCK_MISC:1565 if (Op.isImm() && VEOperand::MorphToMISCReg(Op))1566 return MCTargetAsmParser::Match_Success;1567 break;1568 }1569 return Match_InvalidOperand;1570}1571