582 lines · cpp
1//===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file is part of the VE Disassembler.10//11//===----------------------------------------------------------------------===//12 13#include "MCTargetDesc/VEMCTargetDesc.h"14#include "TargetInfo/VETargetInfo.h"15#include "VE.h"16#include "llvm/MC/MCAsmInfo.h"17#include "llvm/MC/MCContext.h"18#include "llvm/MC/MCDecoder.h"19#include "llvm/MC/MCDecoderOps.h"20#include "llvm/MC/MCDisassembler/MCDisassembler.h"21#include "llvm/MC/MCInst.h"22#include "llvm/MC/TargetRegistry.h"23#include "llvm/Support/Compiler.h"24 25using namespace llvm;26using namespace llvm::MCD;27 28#define DEBUG_TYPE "ve-disassembler"29 30typedef MCDisassembler::DecodeStatus DecodeStatus;31 32namespace {33 34/// A disassembler class for VE.35class VEDisassembler : public MCDisassembler {36public:37 VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)38 : MCDisassembler(STI, Ctx) {}39 ~VEDisassembler() override = default;40 41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,42 ArrayRef<uint8_t> Bytes, uint64_t Address,43 raw_ostream &CStream) const override;44};45} // namespace46 47static MCDisassembler *createVEDisassembler(const Target &T,48 const MCSubtargetInfo &STI,49 MCContext &Ctx) {50 return new VEDisassembler(STI, Ctx);51}52 53extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void54LLVMInitializeVEDisassembler() {55 // Register the disassembler.56 TargetRegistry::RegisterMCDisassembler(getTheVETarget(),57 createVEDisassembler);58}59 60// clang-format off61static const unsigned I32RegDecoderTable[] = {62 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,63 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,64 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,65 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,66 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,67 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,68 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,69 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,70 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,71 VE::SW63};72 73static const unsigned I64RegDecoderTable[] = {74 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,75 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13,76 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20,77 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27,78 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34,79 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41,80 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48,81 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55,82 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62,83 VE::SX63};84 85static const unsigned F32RegDecoderTable[] = {86 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,87 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,88 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,89 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,90 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,91 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,92 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,93 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,94 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,95 VE::SF63};96 97static const unsigned F128RegDecoderTable[] = {98 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,99 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,100 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,101 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};102 103static const unsigned V64RegDecoderTable[] = {104 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7,105 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,106 VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23,107 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,108 VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39,109 VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47,110 VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55,111 VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63};112 113static const unsigned VMRegDecoderTable[] = {114 VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5,115 VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11,116 VE::VM12, VE::VM13, VE::VM14, VE::VM15};117 118static const unsigned VM512RegDecoderTable[] = {VE::VMP0, VE::VMP1, VE::VMP2,119 VE::VMP3, VE::VMP4, VE::VMP5,120 VE::VMP6, VE::VMP7};121 122static const unsigned MiscRegDecoderTable[] = {123 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,124 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,125 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,126 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,127 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,128 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,129 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,130 VE::PMC12, VE::PMC13, VE::PMC14};131// clang-format on132 133static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo,134 uint64_t Address,135 const MCDisassembler *Decoder) {136 if (RegNo > 63)137 return MCDisassembler::Fail;138 unsigned Reg = I32RegDecoderTable[RegNo];139 Inst.addOperand(MCOperand::createReg(Reg));140 return MCDisassembler::Success;141}142 143static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo,144 uint64_t Address,145 const MCDisassembler *Decoder) {146 if (RegNo > 63)147 return MCDisassembler::Fail;148 unsigned Reg = I64RegDecoderTable[RegNo];149 Inst.addOperand(MCOperand::createReg(Reg));150 return MCDisassembler::Success;151}152 153static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,154 uint64_t Address,155 const MCDisassembler *Decoder) {156 if (RegNo > 63)157 return MCDisassembler::Fail;158 unsigned Reg = F32RegDecoderTable[RegNo];159 Inst.addOperand(MCOperand::createReg(Reg));160 return MCDisassembler::Success;161}162 163static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo,164 uint64_t Address,165 const MCDisassembler *Decoder) {166 if (RegNo % 2 || RegNo > 63)167 return MCDisassembler::Fail;168 unsigned Reg = F128RegDecoderTable[RegNo / 2];169 Inst.addOperand(MCOperand::createReg(Reg));170 return MCDisassembler::Success;171}172 173static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo,174 uint64_t Address,175 const MCDisassembler *Decoder) {176 unsigned Reg = VE::NoRegister;177 if (RegNo == 255)178 Reg = VE::VIX;179 else if (RegNo > 63)180 return MCDisassembler::Fail;181 else182 Reg = V64RegDecoderTable[RegNo];183 Inst.addOperand(MCOperand::createReg(Reg));184 return MCDisassembler::Success;185}186 187static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo,188 uint64_t Address,189 const MCDisassembler *Decoder) {190 if (RegNo > 15)191 return MCDisassembler::Fail;192 unsigned Reg = VMRegDecoderTable[RegNo];193 Inst.addOperand(MCOperand::createReg(Reg));194 return MCDisassembler::Success;195}196 197static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo,198 uint64_t Address,199 const MCDisassembler *Decoder) {200 if (RegNo % 2 || RegNo > 15)201 return MCDisassembler::Fail;202 unsigned Reg = VM512RegDecoderTable[RegNo / 2];203 Inst.addOperand(MCOperand::createReg(Reg));204 return MCDisassembler::Success;205}206 207static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,208 uint64_t Address,209 const MCDisassembler *Decoder) {210 if (RegNo > 30)211 return MCDisassembler::Fail;212 unsigned Reg = MiscRegDecoderTable[RegNo];213 if (Reg == VE::NoRegister)214 return MCDisassembler::Fail;215 Inst.addOperand(MCOperand::createReg(Reg));216 return MCDisassembler::Success;217}218 219typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address,220 const MCDisassembler *Decoder);221 222static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,223 const MCDisassembler *Decoder) {224 unsigned sy = fieldFromInstruction(insn, 40, 7);225 bool cy = fieldFromInstruction(insn, 47, 1);226 unsigned sz = fieldFromInstruction(insn, 32, 7);227 bool cz = fieldFromInstruction(insn, 39, 1);228 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));229 DecodeStatus status;230 231 // Decode sz.232 if (cz) {233 status = DecodeI64RegisterClass(MI, sz, Address, Decoder);234 if (status != MCDisassembler::Success)235 return status;236 } else {237 MI.addOperand(MCOperand::createImm(0));238 }239 240 // Decode sy.241 if (cy) {242 status = DecodeI64RegisterClass(MI, sy, Address, Decoder);243 if (status != MCDisassembler::Success)244 return status;245 } else {246 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));247 }248 249 // Decode simm32.250 MI.addOperand(MCOperand::createImm(simm32));251 252 return MCDisassembler::Success;253}254 255static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address,256 const MCDisassembler *Decoder) {257 unsigned sz = fieldFromInstruction(insn, 32, 7);258 bool cz = fieldFromInstruction(insn, 39, 1);259 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));260 DecodeStatus status;261 262 // Decode sz.263 if (cz) {264 status = DecodeI64RegisterClass(MI, sz, Address, Decoder);265 if (status != MCDisassembler::Success)266 return status;267 } else {268 MI.addOperand(MCOperand::createImm(0));269 }270 271 // Decode simm32.272 MI.addOperand(MCOperand::createImm(simm32));273 274 return MCDisassembler::Success;275}276 277static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,278 const MCDisassembler *Decoder, bool isLoad,279 DecodeFunc DecodeSX) {280 unsigned sx = fieldFromInstruction(insn, 48, 7);281 282 DecodeStatus status;283 if (isLoad) {284 status = DecodeSX(MI, sx, Address, Decoder);285 if (status != MCDisassembler::Success)286 return status;287 }288 289 status = DecodeASX(MI, insn, Address, Decoder);290 if (status != MCDisassembler::Success)291 return status;292 293 if (!isLoad) {294 status = DecodeSX(MI, sx, Address, Decoder);295 if (status != MCDisassembler::Success)296 return status;297 }298 return MCDisassembler::Success;299}300 301static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address,302 const MCDisassembler *Decoder, bool isLoad,303 DecodeFunc DecodeSX) {304 unsigned sx = fieldFromInstruction(insn, 48, 7);305 306 DecodeStatus status;307 if (isLoad) {308 status = DecodeSX(MI, sx, Address, Decoder);309 if (status != MCDisassembler::Success)310 return status;311 }312 313 status = DecodeAS(MI, insn, Address, Decoder);314 if (status != MCDisassembler::Success)315 return status;316 317 if (!isLoad) {318 status = DecodeSX(MI, sx, Address, Decoder);319 if (status != MCDisassembler::Success)320 return status;321 }322 return MCDisassembler::Success;323}324 325static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,326 const MCDisassembler *Decoder) {327 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);328}329 330static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,331 uint64_t Address,332 const MCDisassembler *Decoder) {333 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass);334}335 336static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,337 const MCDisassembler *Decoder) {338 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);339}340 341static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,342 uint64_t Address,343 const MCDisassembler *Decoder) {344 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass);345}346 347static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,348 const MCDisassembler *Decoder) {349 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass);350}351 352static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,353 uint64_t Address,354 const MCDisassembler *Decoder) {355 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);356}357 358static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,359 uint64_t Address,360 const MCDisassembler *Decoder) {361 return DecodeMemAS(Inst, insn, Address, Decoder, true,362 DecodeI64RegisterClass);363}364 365static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,366 uint64_t Address,367 const MCDisassembler *Decoder) {368 return DecodeMemAS(Inst, insn, Address, Decoder, false,369 DecodeI64RegisterClass);370}371 372static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,373 const MCDisassembler *Decoder, bool isImmOnly,374 bool isUImm, DecodeFunc DecodeSX) {375 unsigned sx = fieldFromInstruction(insn, 48, 7);376 bool cy = fieldFromInstruction(insn, 47, 1);377 unsigned sy = fieldFromInstruction(insn, 40, 7);378 379 // Add $sx.380 DecodeStatus status;381 status = DecodeSX(MI, sx, Address, Decoder);382 if (status != MCDisassembler::Success)383 return status;384 385 // Add $disp($sz).386 status = DecodeAS(MI, insn, Address, Decoder);387 if (status != MCDisassembler::Success)388 return status;389 390 // Add $sy.391 if (cy && !isImmOnly) {392 status = DecodeSX(MI, sy, Address, Decoder);393 if (status != MCDisassembler::Success)394 return status;395 } else {396 if (isUImm)397 MI.addOperand(MCOperand::createImm(sy));398 else399 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));400 }401 402 // Add $sd.403 status = DecodeSX(MI, sx, Address, Decoder);404 if (status != MCDisassembler::Success)405 return status;406 407 return MCDisassembler::Success;408}409 410static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address,411 const MCDisassembler *Decoder) {412 return DecodeCAS(MI, insn, Address, Decoder, false, true,413 DecodeI64RegisterClass);414}415 416static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address,417 const MCDisassembler *Decoder) {418 return DecodeCAS(MI, insn, Address, Decoder, false, true,419 DecodeI32RegisterClass);420}421 422static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address,423 const MCDisassembler *Decoder) {424 return DecodeCAS(MI, insn, Address, Decoder, false, false,425 DecodeI64RegisterClass);426}427 428static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address,429 const MCDisassembler *Decoder) {430 return DecodeCAS(MI, insn, Address, Decoder, false, false,431 DecodeI32RegisterClass);432}433 434static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,435 const MCDisassembler *Decoder) {436 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);437}438 439static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address,440 const MCDisassembler *Decoder) {441 uint64_t tgt = SignExtend64<7>(insn);442 MI.addOperand(MCOperand::createImm(tgt));443 return MCDisassembler::Success;444}445 446static DecodeStatus DecodeSIMM32(MCInst &MI, uint64_t insn, uint64_t Address,447 const MCDisassembler *Decoder) {448 uint64_t tgt = SignExtend64<32>(insn);449 MI.addOperand(MCOperand::createImm(tgt));450 return MCDisassembler::Success;451}452 453static bool isIntegerBCKind(MCInst &MI) {454 455#define BCm_kind(NAME) \456 case NAME##rri: \457 case NAME##rzi: \458 case NAME##iri: \459 case NAME##izi: \460 case NAME##rri_nt: \461 case NAME##rzi_nt: \462 case NAME##iri_nt: \463 case NAME##izi_nt: \464 case NAME##rri_t: \465 case NAME##rzi_t: \466 case NAME##iri_t: \467 case NAME##izi_t:468 469#define BCRm_kind(NAME) \470 case NAME##rr: \471 case NAME##ir: \472 case NAME##rr_nt: \473 case NAME##ir_nt: \474 case NAME##rr_t: \475 case NAME##ir_t:476 477 {478 using namespace llvm::VE;479 switch (MI.getOpcode()) {480 BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL)481 BCRm_kind(BRCFW) return true;482 }483 }484#undef BCm_kind485 486 return false;487}488 489// Decode CC Operand field.490static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address,491 const MCDisassembler *Decoder) {492 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));493 return MCDisassembler::Success;494}495 496// Decode RD Operand field.497static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address,498 const MCDisassembler *Decoder) {499 MI.addOperand(MCOperand::createImm(VEValToRD(cf)));500 return MCDisassembler::Success;501}502 503// Decode branch condition instruction and CCOperand field in it.504static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn,505 uint64_t Address,506 const MCDisassembler *Decoder) {507 unsigned cf = fieldFromInstruction(insn, 48, 4);508 bool cy = fieldFromInstruction(insn, 47, 1);509 unsigned sy = fieldFromInstruction(insn, 40, 7);510 511 // Decode cf.512 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));513 514 // Decode sy.515 DecodeStatus status;516 if (cy) {517 status = DecodeI64RegisterClass(MI, sy, Address, Decoder);518 if (status != MCDisassembler::Success)519 return status;520 } else {521 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));522 }523 524 // Decode MEMri.525 return DecodeAS(MI, insn, Address, Decoder);526}527 528static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn,529 uint64_t Address,530 const MCDisassembler *Decoder) {531 // Decode MEMri.532 return DecodeAS(MI, insn, Address, Decoder);533}534 535#include "VEGenDisassemblerTables.inc"536 537/// Read four bytes from the ArrayRef and return 32 bit word.538static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,539 uint64_t &Size, uint64_t &Insn,540 bool IsLittleEndian) {541 // We want to read exactly 8 Bytes of data.542 if (Bytes.size() < 8) {543 Size = 0;544 return MCDisassembler::Fail;545 }546 547 Insn = IsLittleEndian548 ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |549 ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) |550 ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) |551 ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56)552 : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) |553 ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) |554 ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) |555 ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56);556 557 return MCDisassembler::Success;558}559 560DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,561 ArrayRef<uint8_t> Bytes,562 uint64_t Address,563 raw_ostream &CStream) const {564 uint64_t Insn;565 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();566 DecodeStatus Result =567 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian);568 if (Result == MCDisassembler::Fail)569 return MCDisassembler::Fail;570 571 // Calling the auto-generated decoder function.572 573 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI);574 575 if (Result != MCDisassembler::Fail) {576 Size = 8;577 return Result;578 }579 580 return MCDisassembler::Fail;581}582