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1//===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12//===----------------------------------------------------------------------===//13// Target-independent interfaces which we are implementing14//===----------------------------------------------------------------------===//15 16include "llvm/Target/Target.td"17 18//===----------------------------------------------------------------------===//19// VE Subtarget features.20//21def FeatureEnableVPU22 : SubtargetFeature<"vpu", "EnableVPU", "true",23 "Enable the VPU">;24 25//===----------------------------------------------------------------------===//26// Register File, Calling Conv, Instruction Descriptions27//===----------------------------------------------------------------------===//28 29include "VERegisterInfo.td"30include "VECallingConv.td"31include "VEInstrInfo.td"32 33defm : RemapAllTargetPseudoPointerOperands<ve_ptr_rc>;34def VEInstrInfo : InstrInfo {}35 36def VEAsmParser : AsmParser {37 // Use both VE register name matcher to accept "S0~S63" register names38 // and default register matcher to accept other registeres.39 let AllowDuplicateRegisterNames = 1;40 let ShouldEmitMatchRegisterAltName = 1;41}42 43//===----------------------------------------------------------------------===//44// VE processors supported.45//===----------------------------------------------------------------------===//46 47class Proc<string Name, list<SubtargetFeature> Features>48 : Processor<Name, NoItineraries, Features>;49 50def : Proc<"generic", [FeatureEnableVPU]>;51 52//===----------------------------------------------------------------------===//53// Declare the target which we are implementing54//===----------------------------------------------------------------------===//55 56def VEAsmWriter : AsmWriter {57 string AsmWriterClassName = "InstPrinter";58 int PassSubtarget = 1;59 int Variant = 0;60}61 62def VE : Target {63 // Pull in Instruction Info:64 let InstructionSet = VEInstrInfo;65 let AssemblyParsers = [VEAsmParser];66 let AssemblyWriters = [VEAsmWriter];67 let AllowRegisterRenaming = 1;68}69