495 lines · cpp
1//===-- VEFrameLowering.cpp - VE Frame Information ------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the VE implementation of TargetFrameLowering class.10//11// On VE, stack frames are structured as follows:12//13// The stack grows downward.14//15// All of the individual frame areas on the frame below are optional, i.e. it's16// possible to create a function so that the particular area isn't present17// in the frame.18//19// At function entry, the "frame" looks as follows:20//21// | | Higher address22// |----------------------------------------------|23// | Parameter area for this function |24// |----------------------------------------------|25// | Register save area (RSA) for this function |26// |----------------------------------------------|27// | Return address for this function |28// |----------------------------------------------|29// | Frame pointer for this function |30// |----------------------------------------------| <- sp31// | | Lower address32//33// VE doesn't use on demand stack allocation, so user code generated by LLVM34// needs to call VEOS to allocate stack frame. VE's ABI want to reduce the35// number of VEOS calls, so ABI requires to allocate not only RSA (in general36// CSR, callee saved register) area but also call frame at the prologue of37// caller function.38//39// After the prologue has run, the frame has the following general structure.40// Note that technically the last frame area (VLAs) doesn't get created until41// in the main function body, after the prologue is run. However, it's depicted42// here for completeness.43//44// | | Higher address45// |----------------------------------------------|46// | Parameter area for this function |47// |----------------------------------------------|48// | Register save area (RSA) for this function |49// |----------------------------------------------|50// | Return address for this function |51// |----------------------------------------------|52// | Frame pointer for this function |53// |----------------------------------------------| <- fp(=old sp)54// |.empty.space.to.make.part.below.aligned.in....|55// |.case.it.needs.more.than.the.standard.16-byte.| (size of this area is56// |.alignment....................................| unknown at compile time)57// |----------------------------------------------|58// | Local variables of fixed size including spill|59// | slots |60// |----------------------------------------------| <- bp(not defined by ABI,61// |.variable-sized.local.variables.(VLAs)........| LLVM chooses SX17)62// |..............................................| (size of this area is63// |..............................................| unknown at compile time)64// |----------------------------------------------| <- stack top (returned by65// | Parameter area for callee | alloca)66// |----------------------------------------------|67// | Register save area (RSA) for callee |68// |----------------------------------------------|69// | Return address for callee |70// |----------------------------------------------|71// | Frame pointer for callee |72// |----------------------------------------------| <- sp73// | | Lower address74//75// To access the data in a frame, at-compile time, a constant offset must be76// computable from one of the pointers (fp, bp, sp) to access it. The size77// of the areas with a dotted background cannot be computed at compile-time78// if they are present, making it required to have all three of fp, bp and79// sp to be set up to be able to access all contents in the frame areas,80// assuming all of the frame areas are non-empty.81//82// For most functions, some of the frame areas are empty. For those functions,83// it may not be necessary to set up fp or bp:84// * A base pointer is definitely needed when there are both VLAs and local85// variables with more-than-default alignment requirements.86// * A frame pointer is definitely needed when there are local variables with87// more-than-default alignment requirements.88//89// In addition, VE ABI defines RSA frame, return address, and frame pointer90// as follows:91//92// |----------------------------------------------| <- sp+17693// | %s18...%s33 |94// |----------------------------------------------| <- sp+4895// | Linkage area register (%s17) |96// |----------------------------------------------| <- sp+4097// | Procedure linkage table register (%plt=%s16) |98// |----------------------------------------------| <- sp+3299// | Global offset table register (%got=%s15) |100// |----------------------------------------------| <- sp+24101// | Thread pointer register (%tp=%s14) |102// |----------------------------------------------| <- sp+16103// | Return address |104// |----------------------------------------------| <- sp+8105// | Frame pointer |106// |----------------------------------------------| <- sp+0107//108// NOTE: This description is based on VE ABI and description in109// AArch64FrameLowering.cpp. Thanks a lot.110//===----------------------------------------------------------------------===//111 112#include "VEFrameLowering.h"113#include "VEInstrInfo.h"114#include "VEMachineFunctionInfo.h"115#include "VESubtarget.h"116#include "llvm/CodeGen/MachineFrameInfo.h"117#include "llvm/CodeGen/MachineFunction.h"118#include "llvm/CodeGen/MachineInstrBuilder.h"119#include "llvm/CodeGen/MachineModuleInfo.h"120#include "llvm/CodeGen/MachineRegisterInfo.h"121#include "llvm/CodeGen/RegisterScavenging.h"122#include "llvm/Support/MathExtras.h"123#include "llvm/Target/TargetOptions.h"124 125using namespace llvm;126 127VEFrameLowering::VEFrameLowering(const VESubtarget &ST)128 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(16), 0,129 Align(16)),130 STI(ST) {}131 132void VEFrameLowering::emitPrologueInsns(MachineFunction &MF,133 MachineBasicBlock &MBB,134 MachineBasicBlock::iterator MBBI,135 uint64_t NumBytes,136 bool RequireFPUpdate) const {137 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();138 DebugLoc DL;139 const VEInstrInfo &TII = *STI.getInstrInfo();140 141 // Insert following codes here as prologue142 //143 // st %fp, 0(, %sp) iff !isLeafProc144 // st %lr, 8(, %sp) iff !isLeafProc145 // st %got, 24(, %sp) iff hasGOT146 // st %plt, 32(, %sp) iff hasGOT147 // st %s17, 40(, %sp) iff hasBP148 if (!FuncInfo->isLeafProc()) {149 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))150 .addReg(VE::SX11)151 .addImm(0)152 .addImm(0)153 .addReg(VE::SX9);154 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))155 .addReg(VE::SX11)156 .addImm(0)157 .addImm(8)158 .addReg(VE::SX10);159 }160 if (hasGOT(MF)) {161 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))162 .addReg(VE::SX11)163 .addImm(0)164 .addImm(24)165 .addReg(VE::SX15);166 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))167 .addReg(VE::SX11)168 .addImm(0)169 .addImm(32)170 .addReg(VE::SX16);171 }172 if (hasBP(MF))173 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))174 .addReg(VE::SX11)175 .addImm(0)176 .addImm(40)177 .addReg(VE::SX17);178}179 180void VEFrameLowering::emitEpilogueInsns(MachineFunction &MF,181 MachineBasicBlock &MBB,182 MachineBasicBlock::iterator MBBI,183 uint64_t NumBytes,184 bool RequireFPUpdate) const {185 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();186 DebugLoc DL;187 const VEInstrInfo &TII = *STI.getInstrInfo();188 189 // Insert following codes here as epilogue190 //191 // ld %s17, 40(, %sp) iff hasBP192 // ld %plt, 32(, %sp) iff hasGOT193 // ld %got, 24(, %sp) iff hasGOT194 // ld %lr, 8(, %sp) iff !isLeafProc195 // ld %fp, 0(, %sp) iff !isLeafProc196 if (hasBP(MF))197 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17)198 .addReg(VE::SX11)199 .addImm(0)200 .addImm(40);201 if (hasGOT(MF)) {202 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16)203 .addReg(VE::SX11)204 .addImm(0)205 .addImm(32);206 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15)207 .addReg(VE::SX11)208 .addImm(0)209 .addImm(24);210 }211 if (!FuncInfo->isLeafProc()) {212 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10)213 .addReg(VE::SX11)214 .addImm(0)215 .addImm(8);216 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9)217 .addReg(VE::SX11)218 .addImm(0)219 .addImm(0);220 }221}222 223void VEFrameLowering::emitSPAdjustment(MachineFunction &MF,224 MachineBasicBlock &MBB,225 MachineBasicBlock::iterator MBBI,226 int64_t NumBytes,227 MaybeAlign MaybeAlign) const {228 DebugLoc DL;229 const VEInstrInfo &TII = *STI.getInstrInfo();230 231 if (NumBytes == 0) {232 // Nothing to do here.233 } else if (isInt<7>(NumBytes)) {234 // adds.l %s11, NumBytes@lo, %s11235 BuildMI(MBB, MBBI, DL, TII.get(VE::ADDSLri), VE::SX11)236 .addReg(VE::SX11)237 .addImm(NumBytes);238 } else if (isInt<32>(NumBytes)) {239 // lea %s11, NumBytes@lo(, %s11)240 BuildMI(MBB, MBBI, DL, TII.get(VE::LEArii), VE::SX11)241 .addReg(VE::SX11)242 .addImm(0)243 .addImm(Lo_32(NumBytes));244 } else {245 // Emit following codes. This clobbers SX13 which we always know is246 // available here.247 // lea %s13, NumBytes@lo248 // and %s13, %s13, (32)0249 // lea.sl %sp, NumBytes@hi(%s13, %sp)250 BuildMI(MBB, MBBI, DL, TII.get(VE::LEAzii), VE::SX13)251 .addImm(0)252 .addImm(0)253 .addImm(Lo_32(NumBytes));254 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13)255 .addReg(VE::SX13)256 .addImm(M0(32));257 BuildMI(MBB, MBBI, DL, TII.get(VE::LEASLrri), VE::SX11)258 .addReg(VE::SX11)259 .addReg(VE::SX13)260 .addImm(Hi_32(NumBytes));261 }262 263 if (MaybeAlign) {264 // and %sp, %sp, Align-1265 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX11)266 .addReg(VE::SX11)267 .addImm(M1(64 - Log2_64(MaybeAlign.valueOrOne().value())));268 }269}270 271void VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB,272 MachineBasicBlock::iterator MBBI) const {273 DebugLoc DL;274 const VEInstrInfo &TII = *STI.getInstrInfo();275 276 // Emit following codes. It is not possible to insert multiple277 // BasicBlocks in PEI pass, so we emit two pseudo instructions here.278 //279 // EXTEND_STACK // pseudo instrcution280 // EXTEND_STACK_GUARD // pseudo instrcution281 //282 // EXTEND_STACK pseudo will be converted by ExpandPostRA pass into283 // following instructions with multiple basic blocks later.284 //285 // thisBB:286 // brge.l.t %sp, %sl, sinkBB287 // syscallBB:288 // ld %s61, 0x18(, %tp) // load param area289 // or %s62, 0, %s0 // spill the value of %s0290 // lea %s63, 0x13b // syscall # of grow291 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0292 // shm.l %sl, 0x8(%s61) // store old limit at addr:8293 // shm.l %sp, 0x10(%s61) // store new limit at addr:16294 // monc // call monitor295 // or %s0, 0, %s62 // restore the value of %s0296 // sinkBB:297 //298 // EXTEND_STACK_GUARD pseudo will be simply eliminated by ExpandPostRA299 // pass. This pseudo is required to be at the next of EXTEND_STACK300 // pseudo in order to protect iteration loop in ExpandPostRA.301 BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK));302 BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK_GUARD));303}304 305void VEFrameLowering::emitPrologue(MachineFunction &MF,306 MachineBasicBlock &MBB) const {307 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();308 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");309 MachineFrameInfo &MFI = MF.getFrameInfo();310 const VEInstrInfo &TII = *STI.getInstrInfo();311 const VERegisterInfo &RegInfo = *STI.getRegisterInfo();312 MachineBasicBlock::iterator MBBI = MBB.begin();313 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF);314 315 // Debug location must be unknown since the first debug location is used316 // to determine the end of the prologue.317 DebugLoc DL;318 319 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF))320 report_fatal_error("Function \"" + Twine(MF.getName()) +321 "\" required "322 "stack re-alignment, but LLVM couldn't handle it "323 "(probably because it has a dynamic alloca).");324 325 // Get the number of bytes to allocate from the FrameInfo.326 // This number of bytes is already aligned to ABI stack alignment.327 uint64_t NumBytes = MFI.getStackSize();328 329 // Adjust stack size if this function is not a leaf function since the330 // VE ABI requires a reserved area at the top of stack as described in331 // VEFrameLowering.cpp.332 if (!FuncInfo->isLeafProc()) {333 // NOTE: The number is aligned to ABI stack alignment after adjustment.334 NumBytes = STI.getAdjustedFrameSize(NumBytes);335 }336 337 // Finally, ensure that the size is sufficiently aligned for the338 // data on the stack.339 NumBytes = alignTo(NumBytes, MFI.getMaxAlign());340 341 // Update stack size with corrected value.342 MFI.setStackSize(NumBytes);343 344 // Emit Prologue instructions to save multiple registers.345 emitPrologueInsns(MF, MBB, MBBI, NumBytes, true);346 347 // Emit instructions to save SP in FP as follows if this is not a leaf348 // function:349 // or %fp, 0, %sp350 if (!FuncInfo->isLeafProc())351 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX9)352 .addReg(VE::SX11)353 .addImm(0);354 355 // Emit stack adjust instructions356 MaybeAlign RuntimeAlign =357 NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : std::nullopt;358 assert((RuntimeAlign == std::nullopt || !FuncInfo->isLeafProc()) &&359 "SP has to be saved in order to align variable sized stack object!");360 emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign);361 362 if (hasBP(MF)) {363 // Copy SP to BP.364 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX17)365 .addReg(VE::SX11)366 .addImm(0);367 }368 369 // Emit stack extend instructions370 if (NumBytes != 0)371 emitSPExtend(MF, MBB, MBBI);372}373 374MachineBasicBlock::iterator VEFrameLowering::eliminateCallFramePseudoInstr(375 MachineFunction &MF, MachineBasicBlock &MBB,376 MachineBasicBlock::iterator I) const {377 if (!hasReservedCallFrame(MF)) {378 MachineInstr &MI = *I;379 int64_t Size = MI.getOperand(0).getImm();380 if (MI.getOpcode() == VE::ADJCALLSTACKDOWN)381 Size = -Size;382 383 if (Size)384 emitSPAdjustment(MF, MBB, I, Size);385 }386 return MBB.erase(I);387}388 389void VEFrameLowering::emitEpilogue(MachineFunction &MF,390 MachineBasicBlock &MBB) const {391 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();392 DebugLoc DL;393 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();394 MachineFrameInfo &MFI = MF.getFrameInfo();395 const VEInstrInfo &TII = *STI.getInstrInfo();396 397 uint64_t NumBytes = MFI.getStackSize();398 399 // Emit instructions to retrieve original SP.400 if (!FuncInfo->isLeafProc()) {401 // If SP is saved in FP, retrieve it as follows:402 // or %sp, 0, %fp iff !isLeafProc403 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX11)404 .addReg(VE::SX9)405 .addImm(0);406 } else {407 // Emit stack adjust instructions.408 emitSPAdjustment(MF, MBB, MBBI, NumBytes, std::nullopt);409 }410 411 // Emit Epilogue instructions to restore multiple registers.412 emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true);413}414 415// hasFPImpl - Return true if the specified function should have a dedicated416// frame pointer register. This is true if the function has variable sized417// allocas or if frame pointer elimination is disabled.418bool VEFrameLowering::hasFPImpl(const MachineFunction &MF) const {419 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();420 421 const MachineFrameInfo &MFI = MF.getFrameInfo();422 return MF.getTarget().Options.DisableFramePointerElim(MF) ||423 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||424 MFI.isFrameAddressTaken();425}426 427bool VEFrameLowering::hasBP(const MachineFunction &MF) const {428 const MachineFrameInfo &MFI = MF.getFrameInfo();429 const TargetRegisterInfo *TRI = STI.getRegisterInfo();430 431 return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF);432}433 434bool VEFrameLowering::hasGOT(const MachineFunction &MF) const {435 const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();436 437 // If a global base register is assigned (!= 0), GOT is used.438 return FuncInfo->getGlobalBaseReg() != 0;439}440 441StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF,442 int FI,443 Register &FrameReg) const {444 const MachineFrameInfo &MFI = MF.getFrameInfo();445 const VERegisterInfo *RegInfo = STI.getRegisterInfo();446 bool isFixed = MFI.isFixedObjectIndex(FI);447 448 int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);449 450 if (!hasFP(MF)) {451 // If FP is not used, frame indexies are based on a %sp regiter.452 FrameReg = VE::SX11; // %sp453 return StackOffset::getFixed(FrameOffset +454 MF.getFrameInfo().getStackSize());455 }456 if (RegInfo->hasStackRealignment(MF) && !isFixed) {457 // If data on stack require realignemnt, frame indexies are based on a %sp458 // or %s17 (bp) register. If there is a variable sized object, bp is used.459 if (hasBP(MF))460 FrameReg = VE::SX17; // %bp461 else462 FrameReg = VE::SX11; // %sp463 return StackOffset::getFixed(FrameOffset +464 MF.getFrameInfo().getStackSize());465 }466 // Use %fp by default.467 FrameReg = RegInfo->getFrameRegister(MF);468 return StackOffset::getFixed(FrameOffset);469}470 471bool VEFrameLowering::isLeafProc(MachineFunction &MF) const {472 473 MachineRegisterInfo &MRI = MF.getRegInfo();474 MachineFrameInfo &MFI = MF.getFrameInfo();475 476 return !MFI.hasCalls() // No calls477 && !MRI.isPhysRegUsed(VE::SX18) // Registers within limits478 // (s18 is first CSR)479 && !MRI.isPhysRegUsed(VE::SX11) // %sp un-used480 && !hasFP(MF); // Don't need %fp481}482 483void VEFrameLowering::determineCalleeSaves(MachineFunction &MF,484 BitVector &SavedRegs,485 RegScavenger *RS) const {486 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);487 488 // Functions having BP need to emit prologue and epilogue to allocate local489 // buffer on the stack even if the function is a leaf function.490 if (isLeafProc(MF) && !hasBP(MF)) {491 VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();492 FuncInfo->setLeafProc(true);493 }494}495