282 lines · plain
1//===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9// SX-Aurora uses little endian, but instructions are encoded little bit10// different manner. Therefore, we need to tranlate the address of each11// bitfield described in ISA documentation like below.12//13// ISA | InstrFormats.td14// ---------------------------15// 0-7 => 63-5616// 8 => 5517// 32-63 => 31-018 19//===----------------------------------------------------------------------===//20// Instruction Format21//===----------------------------------------------------------------------===//22 23class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>24 : Instruction {25 field bits<64> Inst;26 27 let Namespace = "VE";28 let Size = 8;29 30 bits<8> op;31 let Inst{63-56} = op;32 33 dag OutOperandList = outs;34 dag InOperandList = ins;35 let AsmString = asmstr;36 let Pattern = pattern;37 38 bits<1> VE_Vector = 0;39 bits<1> VE_VLInUse = 0;40 bits<3> VE_VLIndex = 0;41 bits<1> VE_VLWithMask = 0;42 43 /// These fields correspond to the fields in VEInstrInfo.h. Any changes to44 /// these must be reflected there! See comments there for what these are.45 ///46 /// VLIndex is the index of VL register in MI's operands. The HW instruction47 /// doesn't have that field, but we add is in MI for the ease of optimization.48 /// For example, the index of VL of (VST $sy, $sz, $sx, $vl) is 3 (beginning49 /// from 0), and the index of VL of (VST $sy, $sz, $sx, $vm, $vl) is 4. We50 /// define vector instructions hierarchically, so use VE_VLIndex which is51 /// defined by the type of instruction and VE_VLWithMask which is defined52 /// whether the insturction use mask or not.53 let TSFlags{0} = VE_Vector;54 let TSFlags{1} = VE_VLInUse;55 let TSFlags{4-2} = !add(VE_VLIndex, VE_VLWithMask);56 57 let DecoderNamespace = "VE";58}59 60//-----------------------------------------------------------------------------61// Section 5.1 RM Type62//63// RM type has sx, sy, sz, and imm32.64// The effective address is generated by sz + sy + imm32.65//-----------------------------------------------------------------------------66 67class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>68 : InstVE<outs, ins, asmstr, pattern> {69 bits<1> cx = 0;70 bits<7> sx;71 bits<1> cy = 1;72 bits<7> sz; // defines sz prior to sy to assign from sz73 bits<7> sy;74 bits<1> cz = 1;75 bits<32> imm32;76 let op = opVal;77 let Inst{55} = cx;78 let Inst{54-48} = sx;79 let Inst{47} = cy;80 let Inst{46-40} = sy;81 let Inst{39} = cz;82 let Inst{38-32} = sz;83 let Inst{31-0} = imm32;84}85 86//-----------------------------------------------------------------------------87// Section 5.2 RRM Type88//89// RRM type is identical to RM, but the effective address is generated90// by sz + imm32. The sy field is used by other purposes.91//-----------------------------------------------------------------------------92 93class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,94 list<dag> pattern = []>95 : RM<opVal, outs, ins, asmstr, pattern>;96 97// RRMHM type is to load/store host memory98// It is similar to RRM and not use sy.99class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,100 list<dag> pattern = []>101 : RRM<opVal, outs, ins, asmstr, pattern> {102 bits<2> ry = 0;103 let cy = 0;104 let sy{6-2} = 0;105 let sy{1-0} = ry;106}107 108//-----------------------------------------------------------------------------109// Section 5.3 CF Type110//111// CF type is used for control flow.112//-----------------------------------------------------------------------------113 114class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>115 : InstVE<outs, ins, asmstr, pattern> {116 bits<1> cx = 0;117 bits<1> cx2 = 0;118 bits<2> bpf = 0;119 bits<4> cond;120 bits<1> cy = 1;121 bits<7> sy;122 bits<1> cz = 1;123 bits<7> sz;124 bits<32> imm32;125 let op = opVal;126 let Inst{55} = cx;127 let Inst{54} = cx2;128 let Inst{53-52} = bpf;129 let Inst{51-48} = cond;130 let Inst{47} = cy;131 let Inst{46-40} = sy;132 let Inst{39} = cz;133 let Inst{38-32} = sz;134 let Inst{31-0} = imm32;135}136 137//-----------------------------------------------------------------------------138// Section 5.4 RR Type139//140// RR type is for generic arithmetic instructions.141//-----------------------------------------------------------------------------142 143class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>144 : InstVE<outs, ins, asmstr, pattern> {145 bits<1> cx = 0;146 bits<7> sx;147 bits<1> cy = 1;148 bits<7> sy;149 bits<1> cz = 1;150 bits<7> sz; // m field places at the top sz field151 bits<8> vx = 0;152 bits<8> vz = 0;153 bits<1> cw = 0;154 bits<1> cw2 = 0;155 bits<4> cfw = 0;156 let op = opVal;157 let Inst{55} = cx;158 let Inst{54-48} = sx;159 let Inst{47} = cy;160 let Inst{46-40} = sy;161 let Inst{39} = cz;162 let Inst{38-32} = sz;163 let Inst{31-24} = vx;164 let Inst{23-16} = 0;165 let Inst{15-8} = vz;166 let Inst{7} = cw;167 let Inst{6} = cw2;168 let Inst{5-4} = 0;169 let Inst{3-0} = cfw;170}171 172// RRFENCE type is special RR type for a FENCE instruction.173class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr,174 list<dag> pattern = []>175 : InstVE<outs, ins, asmstr, pattern> {176 bits<1> avo = 0;177 bits<1> lf = 0;178 bits<1> sf = 0;179 bits<1> c2 = 0;180 bits<1> c1 = 0;181 bits<1> c0 = 0;182 let op = opVal;183 let Inst{55} = avo;184 let Inst{54-50} = 0;185 let Inst{49} = lf;186 let Inst{48} = sf;187 let Inst{47-43} = 0;188 let Inst{42} = c2;189 let Inst{41} = c1;190 let Inst{40} = c0;191 let Inst{39-0} = 0;192}193 194//-----------------------------------------------------------------------------195// Section 5.5 RW Type196//-----------------------------------------------------------------------------197 198//-----------------------------------------------------------------------------199// Section 5.6 RVM Type200//201// RVM type is for vector transfer instructions.202//-----------------------------------------------------------------------------203 204class RVM<bits<8>opVal, dag outs, dag ins, string asmstr,205 list<dag> pattern = []>206 : InstVE<outs, ins, asmstr, pattern> {207 bits<1> cx = 0;208 bits<1> vc = 0;209 bits<1> cs = 0;210 bits<4> m = 0;211 bits<1> cy = 1;212 bits<7> sy;213 bits<1> cz = 1;214 bits<7> sz;215 bits<8> vx;216 bits<8> vy = 0;217 bits<7> sw = 0;218 let op = opVal;219 let Inst{55} = cx;220 let Inst{54} = vc;221 let Inst{53} = cs;222 let Inst{52} = 0;223 let Inst{51-48} = m;224 let Inst{47} = cy;225 let Inst{46-40} = sy;226 let Inst{39} = cz;227 let Inst{38-32} = sz;228 let Inst{31-24} = vx;229 let Inst{23-16} = vy;230 let Inst{15-8} = 0;231 let Inst{7} = 0;232 let Inst{6-0} = sw;233 234 let VE_Vector = 1;235}236 237//-----------------------------------------------------------------------------238// Section 5.7 RV Type239//240// RV type is for vector instructions.241//-----------------------------------------------------------------------------242 243class RV<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>244 : InstVE<outs, ins, asmstr, pattern> {245 bits<1> cx = 0;246 bits<1> cx2 = 0;247 bits<1> cs = 0;248 bits<1> cs2 = 0;249 bits<4> m = 0;250 bits<1> cy = 1;251 bits<7> sy;252 bits<1> cz = 0;253 bits<7> sz = 0;254 bits<8> vx = 0;255 bits<8> vy = 0;256 bits<8> vz = 0;257 bits<8> vw = 0;258 let op = opVal;259 let Inst{55} = cx;260 let Inst{54} = cx2;261 let Inst{53} = cs;262 let Inst{52} = cs2;263 let Inst{51-48} = m;264 let Inst{47} = cy;265 let Inst{46-40} = sy;266 let Inst{39} = cz;267 let Inst{38-32} = sz;268 let Inst{31-24} = vx;269 let Inst{23-16} = vy;270 let Inst{15-8} = vz;271 let Inst{7-0} = vw;272 273 let VE_Vector = 1;274}275 276// Pseudo instructions.277class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []>278 : InstVE<outs, ins, asmstr, pattern> {279 let isCodeGenOnly = 1;280 let isPseudo = 1;281}282