126 lines · c
1//===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the VE implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H14#define LLVM_LIB_TARGET_VE_VEINSTRINFO_H15 16#include "VERegisterInfo.h"17#include "llvm/CodeGen/TargetInstrInfo.h"18 19#define GET_INSTRINFO_HEADER20#include "VEGenInstrInfo.inc"21 22namespace llvm {23 24class VESubtarget;25 26/// VEII - This namespace holds all of the Aurora VE target-specific27/// per-instruction flags. These must match the corresponding definitions in28/// VEInstrFormats.td.29namespace VEII {30enum {31 // Aurora VE Instruction Flags. These flags describe the characteristics of32 // the Aurora VE instructions for vector handling.33 34 /// VE_Vector - This instruction is Vector Instruction.35 VE_Vector = 0x1,36 37 /// VE_VLInUse - This instruction has a vector register in its operands.38 VE_VLInUse = 0x2,39 40 /// VE_VLMask/Shift - This is a bitmask that selects the index number where41 /// an instruction holds vector length informatio (0 to 6, 7 means undef).n42 VE_VLShift = 2,43 VE_VLMask = 0x07 << VE_VLShift,44};45 46#define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse)47#define GET_VLINDEX(TSF) \48 (HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1)49} // end namespace VEII50 51class VEInstrInfo : public VEGenInstrInfo {52 const VERegisterInfo RI;53 virtual void anchor();54 55public:56 explicit VEInstrInfo(const VESubtarget &ST);57 58 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As59 /// such, whenever a client has an instance of instruction info, it should60 /// always be able to get register info as well (through this method).61 ///62 const VERegisterInfo &getRegisterInfo() const { return RI; }63 64 /// Branch Analysis & Modification {65 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,66 MachineBasicBlock *&FBB,67 SmallVectorImpl<MachineOperand> &Cond,68 bool AllowModify = false) const override;69 70 unsigned removeBranch(MachineBasicBlock &MBB,71 int *BytesRemoved = nullptr) const override;72 73 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,74 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,75 const DebugLoc &DL,76 int *BytesAdded = nullptr) const override;77 78 bool79 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;80 /// } Branch Analysis & Modification81 82 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,83 const DebugLoc &DL, Register DestReg, Register SrcReg,84 bool KillSrc, bool RenamableDest = false,85 bool RenamableSrc = false) const override;86 87 /// Stack Spill & Reload {88 Register isLoadFromStackSlot(const MachineInstr &MI,89 int &FrameIndex) const override;90 Register isStoreToStackSlot(const MachineInstr &MI,91 int &FrameIndex) const override;92 void storeRegToStackSlot(93 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,94 bool isKill, int FrameIndex, const TargetRegisterClass *RC,95 96 Register VReg,97 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;98 99 void loadRegFromStackSlot(100 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,101 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,102 103 Register VReg,104 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;105 /// } Stack Spill & Reload106 107 /// Optimization {108 109 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,110 MachineRegisterInfo *MRI) const override;111 112 /// } Optimization113 114 Register getGlobalBaseReg(MachineFunction *MF) const;115 116 // Lower pseudo instructions after register allocation.117 bool expandPostRAPseudo(MachineInstr &MI) const override;118 119 bool expandExtendStackPseudo(MachineInstr &MI) const;120 bool expandGetStackTopPseudo(MachineInstr &MI) const;121};122 123} // namespace llvm124 125#endif126