brintos / llvm-project-archived public Read only

1//===-- VEInstrInfo.td - Target Description for VE Target -----------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the VE instructions in TableGen format.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Instruction format superclass15//===----------------------------------------------------------------------===//16 17include "VEInstrFormats.td"18 19//===----------------------------------------------------------------------===//20// Helper functions to retrieve target constants.21//22// VE instructions have a space to hold following immediates23//   $sy has 7 bits to represent simm7, uimm7, simm7fp, or uimm7fp.24//   $sz also has 7 bits to represent mimm or mimmfp.25//   $disp has 32 bits to represent simm32.26//27// The mimm is a special immediate value of sequential bit stream of 0 or 1.28//     `(m)0`: Represents 0 sequence then 1 sequence like 0b00...0011...11,29//             where `m` is equal to the number of leading zeros.30//     `(m)1`: Represents 1 sequence then 0 sequence like 0b11...1100...00,31//             where `m` is equal to the number of leading ones.32// Each bit of mimm's 7 bits is used like below:33//     bit 6  : If `(m)0`, this bit is 1.  Otherwise, this bit is 0.34//     bit 5-0: Represents the m (0-63).35// Use `!add(m, 64)` to generates an immediate value in pattern matchings.36//37// The floating point immediate value is not something like compacted value.38// It is simple integer representation, so it works rarely.39//     e.g. 0.0 (0x00000000) or -2.0 (0xC0000000=(2)1).40//===----------------------------------------------------------------------===//41 42defvar ve_ptr_rc = I64;43 44def ULO7 : SDNodeXForm<imm, [{45  return CurDAG->getTargetConstant(N->getZExtValue() & 0x7f,46                                   SDLoc(N), MVT::i32);47}]>;48def LO7 : SDNodeXForm<imm, [{49  return CurDAG->getSignedTargetConstant(SignExtend64(N->getSExtValue(), 7),50                                         SDLoc(N), MVT::i32);51}]>;52def MIMM : SDNodeXForm<imm, [{53  return CurDAG->getTargetConstant(val2MImm(getImmVal(N)),54                                   SDLoc(N), MVT::i32);55}]>;56def LO32 : SDNodeXForm<imm, [{57  return CurDAG->getTargetConstant(Lo_32(N->getZExtValue()),58                                   SDLoc(N), MVT::i32);59}]>;60def HI32 : SDNodeXForm<imm, [{61  // Transformation function: shift the immediate value down into the low bits.62  return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),63                                   SDLoc(N), MVT::i32);64}]>;65 66def LO7FP : SDNodeXForm<fpimm, [{67  uint64_t Val = getFpImmVal(N);68  return CurDAG->getTargetConstant(SignExtend32(Val, 7), SDLoc(N), MVT::i32);69}]>;70def MIMMFP : SDNodeXForm<fpimm, [{71  return CurDAG->getTargetConstant(val2MImm(getFpImmVal(N)),72                                   SDLoc(N), MVT::i32);73}]>;74def LOFP32 : SDNodeXForm<fpimm, [{75  return CurDAG->getTargetConstant(Lo_32(getFpImmVal(N) & 0xffffffff),76                                   SDLoc(N), MVT::i32);77}]>;78def HIFP32 : SDNodeXForm<fpimm, [{79  return CurDAG->getTargetConstant(Hi_32(getFpImmVal(N)), SDLoc(N), MVT::i32);80}]>;81 82def icond2cc : SDNodeXForm<cond, [{83  VECC::CondCode VECC = intCondCode2Icc(N->get());84  return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);85}]>;86 87def icond2ccSwap : SDNodeXForm<cond, [{88  ISD::CondCode CC = getSetCCSwappedOperands(N->get());89  VECC::CondCode VECC = intCondCode2Icc(CC);90  return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);91}]>;92 93def fcond2cc : SDNodeXForm<cond, [{94  VECC::CondCode VECC = fpCondCode2Fcc(N->get());95  return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);96}]>;97 98def fcond2ccSwap : SDNodeXForm<cond, [{99  ISD::CondCode CC = getSetCCSwappedOperands(N->get());100  VECC::CondCode VECC = fpCondCode2Fcc(CC);101  return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);102}]>;103 104def CCOP : SDNodeXForm<imm, [{105  return CurDAG->getTargetConstant(N->getZExtValue(),106                                   SDLoc(N), MVT::i32);107}]>;108 109//===----------------------------------------------------------------------===//110// Feature predicates.111//===----------------------------------------------------------------------===//112 113//===----------------------------------------------------------------------===//114// Instruction Pattern Stuff115//===----------------------------------------------------------------------===//116 117// zero118def ZeroAsmOperand : AsmOperandClass {119  let Name = "Zero";120}121def zero : Operand<i32>, PatLeaf<(imm), [{122    return N->getSExtValue() == 0; }]> {123  let ParserMatchClass = ZeroAsmOperand;124}125 126// uimm0to2 - Special immediate value represents 0, 1, and 2.127def UImm0to2AsmOperand : AsmOperandClass {128  let Name = "UImm0to2";129}130def uimm0to2 : Operand<i32>, PatLeaf<(imm), [{131    return N->getZExtValue() < 3; }], ULO7> {132  let ParserMatchClass = UImm0to2AsmOperand;133}134 135// uimm1 - Generic immediate value.136def UImm1AsmOperand : AsmOperandClass {137  let Name = "UImm1";138}139def uimm1 : Operand<i32>, PatLeaf<(imm), [{140    return isUInt<1>(N->getZExtValue()); }], ULO7> {141  let ParserMatchClass = UImm1AsmOperand;142}143 144// uimm2 - Generic immediate value.145def UImm2AsmOperand : AsmOperandClass {146  let Name = "UImm2";147}148def uimm2 : Operand<i32>, PatLeaf<(imm), [{149    return isUInt<2>(N->getZExtValue()); }], ULO7> {150  let ParserMatchClass = UImm2AsmOperand;151}152 153// uimm3 - Generic immediate value.154def UImm3AsmOperand : AsmOperandClass {155  let Name = "UImm3";156}157def uimm3 : Operand<i32>, PatLeaf<(imm), [{158    return isUInt<3>(N->getZExtValue()); }], ULO7> {159  let ParserMatchClass = UImm3AsmOperand;160}161 162// uimm4 - Generic immediate value.163def UImm4AsmOperand : AsmOperandClass {164  let Name = "UImm4";165}166def uimm4 : Operand<i32>, PatLeaf<(imm), [{167    return isUInt<4>(N->getZExtValue()); }], ULO7> {168  let ParserMatchClass = UImm4AsmOperand;169}170 171// uimm6 - Generic immediate value.172def UImm6AsmOperand : AsmOperandClass {173  let Name = "UImm6";174}175def uimm6 : Operand<i32>, PatLeaf<(imm), [{176    return isUInt<6>(N->getZExtValue()); }], ULO7> {177  let ParserMatchClass = UImm6AsmOperand;178}179 180// uimm7 - Generic immediate value.181def UImm7AsmOperand : AsmOperandClass {182  let Name = "UImm7";183}184def uimm7 : Operand<i32>, PatLeaf<(imm), [{185    return isUInt<7>(N->getZExtValue()); }], ULO7> {186  let ParserMatchClass = UImm7AsmOperand;187}188 189// simm7 - Generic immediate value.190def SImm7AsmOperand : AsmOperandClass {191  let Name = "SImm7";192}193def simm7 : Operand<i32>, PatLeaf<(imm), [{194    return isInt<7>(N->getSExtValue()); }], LO7> {195  let ParserMatchClass = SImm7AsmOperand;196  let DecoderMethod = "DecodeSIMM7";197}198 199// mimm - Special immediate value of sequential bit stream of 0 or 1.200def MImmAsmOperand : AsmOperandClass {201  let Name = "MImm";202  let ParserMethod = "parseMImmOperand";203}204def mimm : Operand<i32>, PatLeaf<(imm), [{205    return isMImmVal(getImmVal(N)); }], MIMM> {206  let ParserMatchClass = MImmAsmOperand;207  let PrintMethod = "printMImmOperand";208}209 210// zerofp - Generic fp immediate zero value.211def zerofp : Operand<i32>, PatLeaf<(fpimm), [{212    return getFpImmVal(N) == 0; }]> {213  let ParserMatchClass = ZeroAsmOperand;214}215 216// simm7fp - Generic fp immediate value.217def simm7fp : Operand<i32>, PatLeaf<(fpimm), [{218    return isInt<7>(getFpImmVal(N));219  }], LO7FP> {220  let ParserMatchClass = SImm7AsmOperand;221  let DecoderMethod = "DecodeSIMM7";222}223 224// mimmfp - Special fp immediate value of sequential bit stream of 0 or 1.225def mimmfp : Operand<i32>, PatLeaf<(fpimm), [{226    return isMImmVal(getFpImmVal(N)); }], MIMMFP> {227  let ParserMatchClass = MImmAsmOperand;228  let PrintMethod = "printMImmOperand";229}230 231// mimmfp32 - 32 bit width mimmfp232//   Float value places at higher bits, so ignore lower 32 bits.233def mimmfp32 : Operand<i32>, PatLeaf<(fpimm), [{234    return isMImm32Val(getFpImmVal(N) >> 32); }], MIMMFP> {235  let ParserMatchClass = MImmAsmOperand;236  let PrintMethod = "printMImmOperand";237}238 239// other generic patterns to use in pattern matchings240def simm32      : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;241def uimm32      : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;242def lomsbzero   : PatLeaf<(imm), [{ return (N->getZExtValue() & 0x80000000)243                                      == 0; }]>;244def lozero      : PatLeaf<(imm), [{ return (N->getZExtValue() & 0xffffffff)245                                      == 0; }]>;246def fplomsbzero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0x80000000)247                                        == 0; }]>;248def fplozero    : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0xffffffff)249                                        == 0; }]>;250def nonzero     : PatLeaf<(imm), [{ return N->getSExtValue() !=0 ; }]>;251 252def CCSIOp : PatLeaf<(cond), [{253  switch (N->get()) {254  default:          return true;255  case ISD::SETULT:256  case ISD::SETULE:257  case ISD::SETUGT:258  case ISD::SETUGE: return false;259  }260}]>;261 262def CCUIOp : PatLeaf<(cond), [{263  switch (N->get()) {264  default:         return true;265  case ISD::SETLT:266  case ISD::SETLE:267  case ISD::SETGT:268  case ISD::SETGE: return false;269  }270}]>;271 272//===----------------------------------------------------------------------===//273// Addressing modes.274// SX-Aurora has following fields.275//    sz: register or 0276//    sy: register or immediate (-64 to 63)277//    disp: immediate (-2147483648 to 2147483647)278//279// There are two kinds of instruction.280//    ASX format uses sz + sy + disp.281//    AS format uses sz + disp.282//283// Moreover, there are four kinds of assembly instruction format.284//    ASX format uses "disp", "disp(, sz)", "disp(sy)", "disp(sy, sz)",285//    "(, sz)", "(sy)", or "(sy, sz)".286//    AS format uses "disp", "disp(, sz)", or "(, sz)" in general.287//    AS format in RRM format uses "disp", "disp(sz)", or "(sz)".288//    AS format in RRM format for host memory access uses "sz", "(sz)",289//    or "disp(sz)".290//291// We defined them below.292//293// ASX format:294//    MEMrri, MEMrii, MEMzri, MEMzii295// AS format:296//    MEMriASX, MEMziASX    : simple AS format297//    MEMriRRM, MEMziRRM    : AS format in RRM format298//    MEMriHM, MEMziHM      : AS format in RRM format for host memory access299//===----------------------------------------------------------------------===//300 301// DAG selections for both ASX and AS formats.302def ADDRrri : ComplexPattern<iPTR, 3, "selectADDRrri", [frameindex], []>;303def ADDRrii : ComplexPattern<iPTR, 3, "selectADDRrii", [frameindex], []>;304def ADDRzri : ComplexPattern<iPTR, 3, "selectADDRzri", [], []>;305def ADDRzii : ComplexPattern<iPTR, 3, "selectADDRzii", [], []>;306def ADDRri : ComplexPattern<iPTR, 2, "selectADDRri", [frameindex], []>;307def ADDRzi : ComplexPattern<iPTR, 2, "selectADDRzi", [], []>;308 309// ASX format.310def VEMEMrriAsmOperand : AsmOperandClass {311  let Name = "MEMrri";312  let ParserMethod = "parseMEMOperand";313}314def VEMEMriiAsmOperand : AsmOperandClass {315  let Name = "MEMrii";316  let ParserMethod = "parseMEMOperand";317}318def VEMEMzriAsmOperand : AsmOperandClass {319  let Name = "MEMzri";320  let ParserMethod = "parseMEMOperand";321}322def VEMEMziiAsmOperand : AsmOperandClass {323  let Name = "MEMzii";324  let ParserMethod = "parseMEMOperand";325}326 327// ASX format uses single assembly instruction format.328def MEMrri : Operand<iPTR> {329  let PrintMethod = "printMemASXOperand";330  let MIOperandInfo = (ops ve_ptr_rc, ve_ptr_rc, i64imm);331  let ParserMatchClass = VEMEMrriAsmOperand;332}333def MEMrii : Operand<iPTR> {334  let PrintMethod = "printMemASXOperand";335  let MIOperandInfo = (ops ve_ptr_rc, i32imm, i64imm);336  let ParserMatchClass = VEMEMriiAsmOperand;337}338def MEMzri : Operand<iPTR> {339  let PrintMethod = "printMemASXOperand";340  let MIOperandInfo = (ops i32imm /* = 0 */, ve_ptr_rc, i64imm);341  let ParserMatchClass = VEMEMzriAsmOperand;342}343def MEMzii : Operand<iPTR> {344  let PrintMethod = "printMemASXOperand";345  let MIOperandInfo = (ops i32imm /* = 0 */, i32imm, i64imm);346  let ParserMatchClass = VEMEMziiAsmOperand;347}348 349// AS format.350def VEMEMriAsmOperand : AsmOperandClass {351  let Name = "MEMri";352  let ParserMethod = "parseMEMAsOperand";353}354def VEMEMziAsmOperand : AsmOperandClass {355  let Name = "MEMzi";356  let ParserMethod = "parseMEMAsOperand";357}358 359// AS format uses multiple assembly instruction formats360//   1. AS generic assembly instruction format:361def MEMriASX : Operand<iPTR> {362  let PrintMethod = "printMemASOperandASX";363  let MIOperandInfo = (ops ve_ptr_rc, i32imm);364  let ParserMatchClass = VEMEMriAsmOperand;365}366def MEMziASX : Operand<iPTR> {367  let PrintMethod = "printMemASOperandASX";368  let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);369  let ParserMatchClass = VEMEMziAsmOperand;370}371 372//   2. AS RRM style assembly instruction format:373def MEMriRRM : Operand<iPTR> {374  let PrintMethod = "printMemASOperandRRM";375  let MIOperandInfo = (ops ve_ptr_rc, i32imm);376  let ParserMatchClass = VEMEMriAsmOperand;377}378def MEMziRRM : Operand<iPTR> {379  let PrintMethod = "printMemASOperandRRM";380  let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);381  let ParserMatchClass = VEMEMziAsmOperand;382}383 384//   3. AS HM style assembly instruction format:385def MEMriHM : Operand<iPTR> {386  let PrintMethod = "printMemASOperandHM";387  let MIOperandInfo = (ops ve_ptr_rc, i32imm);388  let ParserMatchClass = VEMEMriAsmOperand;389}390def MEMziHM : Operand<iPTR> {391  let PrintMethod = "printMemASOperandHM";392  let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);393  let ParserMatchClass = VEMEMziAsmOperand;394}395 396//===----------------------------------------------------------------------===//397// Other operands.398//===----------------------------------------------------------------------===//399 400// Branch targets have OtherVT type.401def brtarget32 : Operand<OtherVT> {402  let EncoderMethod = "getBranchTargetOpValue";403  let DecoderMethod = "DecodeSIMM32";404}405 406// Operand for printing out a condition code.407def CCOpAsmOperand : AsmOperandClass { let Name = "CCOp"; }408def CCOp : Operand<i32>, ImmLeaf<i32, [{409    return Imm >= 0 && Imm < 22; }], CCOP> {410  let PrintMethod = "printCCOperand";411  let DecoderMethod = "DecodeCCOperand";412  let EncoderMethod = "getCCOpValue";413  let ParserMatchClass = CCOpAsmOperand;414}415 416// Operand for a rounding mode code.417def RDOpAsmOperand : AsmOperandClass {418  let Name = "RDOp";419}420def RDOp : Operand<i32> {421  let PrintMethod = "printRDOperand";422  let DecoderMethod = "DecodeRDOperand";423  let EncoderMethod = "getRDOpValue";424  let ParserMatchClass = RDOpAsmOperand;425}426 427def VEhi    : SDNode<"VEISD::Hi", SDTIntUnaryOp>;428def VElo    : SDNode<"VEISD::Lo", SDTIntUnaryOp>;429 430//  These are target-independent nodes, but have target-specific formats.431def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64>,432                                          SDTCisVT<1, i64> ]>;433def SDT_SPCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i64>,434                                        SDTCisVT<1, i64> ]>;435 436def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,437                           [SDNPHasChain, SDNPOutGlue]>;438def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_SPCallSeqEnd,439                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;440 441def SDT_SPCall    : SDTypeProfile<0, -1, [SDTCisVT<0, i64>]>;442def call          : SDNode<"VEISD::CALL", SDT_SPCall,443                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,444                            SDNPVariadic]>;445 446def retglue       : SDNode<"VEISD::RET_GLUE", SDTNone,447                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;448 449def getGOT        : Operand<iPTR>;450 451// Comparisons452def cmpi          : SDNode<"VEISD::CMPI", SDTIntBinOp>;453def cmpu          : SDNode<"VEISD::CMPU", SDTIntBinOp>;454def cmpf          : SDNode<"VEISD::CMPF", SDTFPBinOp>;455def SDT_Cmpq      : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisFP<0>,456                                  SDTCisFP<2>]>;457def cmpq          : SDNode<"VEISD::CMPQ", SDT_Cmpq>;458 459// res = cmov cmp, t, f, cond460def SDT_Cmov      : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>,461                                  SDTCisVT<4, i32>]>;462def cmov          : SDNode<"VEISD::CMOV", SDT_Cmov>;463 464def VEeh_sjlj_setjmp: SDNode<"VEISD::EH_SJLJ_SETJMP",465                             SDTypeProfile<1, 1, [SDTCisInt<0>,466                                                  SDTCisPtrTy<1>]>,467                             [SDNPHasChain, SDNPSideEffect]>;468def VEeh_sjlj_longjmp: SDNode<"VEISD::EH_SJLJ_LONGJMP",469                              SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,470                              [SDNPHasChain, SDNPSideEffect]>;471def VEeh_sjlj_setup_dispatch: SDNode<"VEISD::EH_SJLJ_SETUP_DISPATCH",472                                     SDTypeProfile<0, 0, []>,473                                     [SDNPHasChain, SDNPSideEffect]>;474 475// GETFUNPLT for PIC476def GetFunPLT : SDNode<"VEISD::GETFUNPLT", SDTIntUnaryOp>;477 478// GETTLSADDR for TLS479def GetTLSAddr : SDNode<"VEISD::GETTLSADDR", SDT_SPCall,480                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,481                         SDNPVariadic]>;482 483// GETSTACKTOP484def GetStackTop : SDNode<"VEISD::GETSTACKTOP", SDTNone,485                        [SDNPHasChain, SDNPSideEffect]>;486 487// TS1AM488def SDT_TS1AM : SDTypeProfile<1, 3, [SDTCisSameAs<0, 3>, SDTCisPtrTy<1>,489                                     SDTCisVT<2, i32>, SDTCisInt<3>]>;490def ts1am     : SDNode<"VEISD::TS1AM", SDT_TS1AM,491                       [SDNPHasChain, SDNPMayStore, SDNPMayLoad,492                        SDNPMemOperand]>;493 494//===----------------------------------------------------------------------===//495// VE Flag Conditions496//===----------------------------------------------------------------------===//497 498// Note that these values must be kept in sync with the CCOp::CondCode enum499// values.500class CC_VAL<int N> : PatLeaf<(i32 N)>;501def CC_IG    : CC_VAL< 0>;  // Greater502def CC_IL    : CC_VAL< 1>;  // Less503def CC_INE   : CC_VAL< 2>;  // Not Equal504def CC_IEQ   : CC_VAL< 3>;  // Equal505def CC_IGE   : CC_VAL< 4>;  // Greater or Equal506def CC_ILE   : CC_VAL< 5>;  // Less or Equal507def CC_AF    : CC_VAL< 6>;  // Always false508def CC_G     : CC_VAL< 7>;  // Greater509def CC_L     : CC_VAL< 8>;  // Less510def CC_NE    : CC_VAL< 9>;  // Not Equal511def CC_EQ    : CC_VAL<10>;  // Equal512def CC_GE    : CC_VAL<11>;  // Greater or Equal513def CC_LE    : CC_VAL<12>;  // Less or Equal514def CC_NUM   : CC_VAL<13>;  // Number515def CC_NAN   : CC_VAL<14>;  // NaN516def CC_GNAN  : CC_VAL<15>;  // Greater or NaN517def CC_LNAN  : CC_VAL<16>;  // Less or NaN518def CC_NENAN : CC_VAL<17>;  // Not Equal or NaN519def CC_EQNAN : CC_VAL<18>;  // Equal or NaN520def CC_GENAN : CC_VAL<19>;  // Greater or Equal or NaN521def CC_LENAN : CC_VAL<20>;  // Less or Equal or NaN522def CC_AT    : CC_VAL<21>;  // Always true523 524//===----------------------------------------------------------------------===//525// VE Rounding Mode526//===----------------------------------------------------------------------===//527 528// Note that these values must be kept in sync with the VERD::RoundingMode enum529// values.530class RD_VAL<int N> : PatLeaf<(i32 N)>;531def RD_NONE  : RD_VAL< 0>;  // According to PSW532def RD_RZ    : RD_VAL< 8>;  // Round toward Zero533def RD_RP    : RD_VAL< 9>;  // Round toward Plus infinity534def RD_RM    : RD_VAL<10>;  // Round toward Minus infinity535def RD_RN    : RD_VAL<11>;  // Round to Nearest (ties to Even)536def RD_RA    : RD_VAL<12>;  // Round to Nearest (ties to Away)537 538//===----------------------------------------------------------------------===//539// VE Multiclasses for common instruction formats540//===----------------------------------------------------------------------===//541 542// Multiclass for generic RR type instructions543let hasSideEffects = 0 in544multiclass RRbm<string opcStr, bits<8>opc,545                RegisterClass RCo, ValueType Tyo,546                RegisterClass RCi, ValueType Tyi,547                SDPatternOperator OpNode = null_frag,548                Operand immOp = simm7, Operand mOp = mimm,549                bit MoveImm = 0> {550  def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),551              !strconcat(opcStr, " $sx, $sy, $sz"),552              [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;553  // VE calculates (OpNode $sy, $sz), but llvm requires to have immediate554  // in RHS, so we use following definition.555  let cy = 0 in556  def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy),557              !strconcat(opcStr, " $sx, $sy, $sz"),558              [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi immOp:$sy)))]>;559  let cz = 0 in560  def rm : RR<opc, (outs RCo:$sx), (ins RCi:$sy, mOp:$sz),561              !strconcat(opcStr, " $sx, $sy, $sz"),562              [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;563  let cy = 0, cz = 0 in564  def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz),565              !strconcat(opcStr, " $sx, $sy, $sz"),566              [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]> {567    // VE uses ORim as a move immediate instruction, so declare it here.568    // An instruction declared as MoveImm will be optimized in FoldImmediate569    // later.570    let isMoveImm = MoveImm;571  }572}573 574// Multiclass for non-commutative RR type instructions575let hasSideEffects = 0 in576multiclass RRNCbm<string opcStr, bits<8>opc,577                RegisterClass RCo, ValueType Tyo,578                RegisterClass RCi, ValueType Tyi,579                SDPatternOperator OpNode = null_frag,580                Operand immOp = simm7, Operand mOp = mimm> {581  def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),582              !strconcat(opcStr, " $sx, $sy, $sz"),583              [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;584  let cy = 0 in585  def ir : RR<opc, (outs RCo:$sx), (ins immOp:$sy, RCi:$sz),586              !strconcat(opcStr, " $sx, $sy, $sz"),587              [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), Tyi:$sz))]>;588  let cz = 0 in589  def rm : RR<opc, (outs RCo:$sx), (ins RCi:$sy, mOp:$sz),590              !strconcat(opcStr, " $sx, $sy, $sz"),591              [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;592  let cy = 0, cz = 0 in593  def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz),594              !strconcat(opcStr, " $sx, $sy, $sz"),595              [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]>;596}597 598// Generic RR multiclass with 2 arguments.599//   e.g. ADDUL, ADDSWSX, ADDSWZX, and etc.600multiclass RRm<string opcStr, bits<8>opc,601               RegisterClass RC, ValueType Ty,602               SDPatternOperator OpNode = null_frag,603               Operand immOp = simm7, Operand mOp = mimm, bit MoveImm = 0> :604  RRbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp, MoveImm>;605 606// Generic RR multiclass for non-commutative instructions with 2 arguments.607//   e.g. SUBUL, SUBUW, SUBSWSX, and etc.608multiclass RRNCm<string opcStr, bits<8>opc,609                 RegisterClass RC, ValueType Ty,610                 SDPatternOperator OpNode = null_frag,611                 Operand immOp = simm7, Operand mOp = mimm> :612  RRNCbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp>;613 614// Generic RR multiclass for floating point instructions with 2 arguments.615//   e.g. FADDD, FADDS, FSUBD, and etc.616multiclass RRFm<string opcStr, bits<8>opc,617                RegisterClass RC, ValueType Ty,618                SDPatternOperator OpNode = null_frag,619                Operand immOp = simm7fp, Operand mOp = mimmfp> :620  RRNCbm<opcStr, opc, RC, Ty, RC, Ty, OpNode, immOp, mOp>;621 622// Generic RR multiclass for shift instructions with 2 arguments.623//   e.g. SLL, SRL, SLAWSX, and etc.624let hasSideEffects = 0 in625multiclass RRIm<string opcStr, bits<8>opc,626                RegisterClass RC, ValueType Ty,627                SDPatternOperator OpNode = null_frag> {628  def rr : RR<opc, (outs RC:$sx), (ins RC:$sz, I32:$sy),629              !strconcat(opcStr, " $sx, $sz, $sy"),630              [(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]>;631  let cz = 0 in632  def mr : RR<opc, (outs RC:$sx), (ins mimm:$sz, I32:$sy),633              !strconcat(opcStr, " $sx, $sz, $sy"),634              [(set Ty:$sx, (OpNode (Ty mimm:$sz), i32:$sy))]>;635  let cy = 0 in636  def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm7:$sy),637              !strconcat(opcStr, " $sx, $sz, $sy"),638              [(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm7:$sy)))]>;639  let cy = 0, cz = 0 in640  def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm7:$sy),641              !strconcat(opcStr, " $sx, $sz, $sy"),642              [(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>;643}644 645// Special RR multiclass for 128 bits shift left instruction.646//   e.g. SLD647let Constraints = "$hi = $sx", hasSideEffects = 0 in648multiclass RRILDm<string opcStr, bits<8>opc, RegisterClass RC> {649  def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy),650              !strconcat(opcStr, " $sx, $sz, $sy")>;651  let cz = 0 in652  def rmr : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, I32:$sy),653              !strconcat(opcStr, " $sx, $sz, $sy")>;654  let cy = 0 in655  def rri : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, uimm7:$sy),656              !strconcat(opcStr, " $sx, $sz, $sy")>;657  let cy = 0, cz = 0 in658  def rmi : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, uimm7:$sy),659              !strconcat(opcStr, " $sx, $sz, $sy")>;660}661 662// Special RR multiclass for 128 bits shift right instruction.663//   e.g. SRD664let Constraints = "$low = $sx", hasSideEffects = 0 in665multiclass RRIRDm<string opcStr, bits<8>opc, RegisterClass RC> {666  def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy),667              !strconcat(opcStr, " $sx, $sz, $sy")>;668  let cz = 0 in669  def mrr : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, I32:$sy),670              !strconcat(opcStr, " $sx, $sz, $sy")>;671  let cy = 0 in672  def rri : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, uimm7:$sy),673              !strconcat(opcStr, " $sx, $sz, $sy")>;674  let cy = 0, cz = 0 in675  def mri : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, uimm7:$sy),676              !strconcat(opcStr, " $sx, $sz, $sy")>;677}678 679// Generic RR multiclass with an argument.680//   e.g. LDZ, PCNT, and  BRV681let cy = 0, sy = 0, hasSideEffects = 0 in682multiclass RRI1m<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,683                 SDPatternOperator OpNode = null_frag> {684  def r : RR<opc, (outs RC:$sx), (ins RC:$sz), !strconcat(opcStr, " $sx, $sz"),685             [(set Ty:$sx, (OpNode Ty:$sz))]>;686  let cz = 0 in687  def m : RR<opc, (outs RC:$sx), (ins mimm:$sz),688             !strconcat(opcStr, " $sx, $sz"),689             [(set Ty:$sx, (OpNode (Ty mimm:$sz)))]>;690}691 692// Special RR multiclass for MRG instruction.693//   e.g. MRG694let Constraints = "$sx = $sd", hasSideEffects = 0 in695multiclass RRMRGm<string opcStr, bits<8>opc, RegisterClass RC> {696  def rr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, RC:$sd),697              !strconcat(opcStr, " $sx, $sy, $sz")>;698  let cy = 0 in699  def ir : RR<opc, (outs RC:$sx), (ins simm7:$sy, RC:$sz, RC:$sd),700              !strconcat(opcStr, " $sx, $sy, $sz")>;701  let cz = 0 in702  def rm : RR<opc, (outs RC:$sx), (ins RC:$sy, mimm:$sz, RC:$sd),703              !strconcat(opcStr, " $sx, $sy, $sz")>;704  let cy = 0, cz = 0 in705  def im : RR<opc, (outs RC:$sx), (ins simm7:$sy, mimm:$sz, RC:$sd),706              !strconcat(opcStr, " $sx, $sy, $sz")>;707}708 709// Special RR multiclass for BSWP instruction.710//   e.g. BSWP711let hasSideEffects = 0 in712multiclass RRSWPm<string opcStr, bits<8>opc,713                  RegisterClass RC, ValueType Ty,714                  SDPatternOperator OpNode = null_frag> {715  let cy = 0 in716  def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm1:$sy),717              !strconcat(opcStr, " $sx, $sz, $sy"),718              [(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm1:$sy)))]>;719  let cy = 0, cz = 0 in720  def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm1:$sy),721              !strconcat(opcStr, " $sx, $sz, $sy"),722              [(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm1:$sy)))]>;723}724 725// Multiclass for CMOV instructions.726//   e.g. CMOVL, CMOVW, CMOVD, and etc.727let Constraints = "$sx = $sd", hasSideEffects = 0,728    cfw = ? in729multiclass RRCMOVm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,730                   SDPatternOperator OpNode = null_frag,731                   Operand immOp = simm7> {732  def rr : RR<opc, (outs I64:$sx), (ins CCOp:$cfw, RC:$sy, I64:$sz, I64:$sd),733              !strconcat(opcStr, " $sx, $sz, $sy"),734              [(set i64:$sx, (OpNode Ty:$sy, i64:$sz, i64:$sd,735                                     (i32 CCOp:$cfw)))]>;736  let cy = 0 in737  def ir : RR<opc, (outs I64:$sx),738              (ins CCOp:$cfw, immOp:$sy, I64:$sz, I64:$sd),739              !strconcat(opcStr, " $sx, $sz, $sy"),740              [(set i64:$sx, (OpNode (Ty immOp:$sy), i64:$sz, i64:$sd,741                                     (i32 CCOp:$cfw)))]>;742  let cz = 0 in743  def rm : RR<opc, (outs I64:$sx),744              (ins CCOp:$cfw, RC:$sy, mimm:$sz, I64:$sd),745              !strconcat(opcStr, " $sx, $sz, $sy"),746              [(set i64:$sx, (OpNode Ty:$sy, (i64 mimm:$sz), i64:$sd,747                                     (i32 CCOp:$cfw)))]>;748  let cy = 0, cz = 0 in749  def im : RR<opc, (outs I64:$sx),750              (ins CCOp:$cfw, immOp:$sy, mimm:$sz, I64:$sd),751              !strconcat(opcStr, " $sx, $sz, $sy"),752              [(set i64:$sx, (OpNode (Ty immOp:$sy), (i64 mimm:$sz), i64:$sd,753                                     (i32 CCOp:$cfw)))]>;754}755 756// Multiclass for floating point conversion instructions.757//   e.g. CVTWDSX, CVTWDZX, CVTWSSX, and etc.758// sz{3-0} = rounding mode759let cz = 0, hasSideEffects = 0 in760multiclass CVTRDm<string opcStr, bits<8> opc, RegisterClass RCo,761                  RegisterClass RCi> {762  def r : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, RCi:$sy),763             !strconcat(opcStr, "${rd} $sx, $sy")> {764    bits<4> rd;765    let sz{6-4} = 0;766    let sz{3-0} = rd;767  }768  let cy = 0 in769  def i : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, simm7:$sy),770             !strconcat(opcStr, "${rd} $sx, $sy")> {771    bits<4> rd;772    let sz{6-4} = 0;773    let sz{3-0} = rd;774  }775}776 777// Multiclass for floating point conversion instructions.778//   e.g. CVTDW, CVTSW, CVTDL, and etc.779let cz = 0, sz = 0, hasSideEffects = 0 in780multiclass CVTm<string opcStr, bits<8> opc, RegisterClass RCo, ValueType Tyo,781                RegisterClass RCi, ValueType Tyi,782                SDPatternOperator OpNode = null_frag> {783  def r : RR<opc, (outs RCo:$sx), (ins RCi:$sy),784             !strconcat(opcStr, " $sx, $sy"),785             [(set Tyo:$sx, (OpNode Tyi:$sy))]>;786  let cy = 0 in787  def i : RR<opc, (outs RCo:$sx), (ins simm7:$sy),788             !strconcat(opcStr, " $sx, $sy")>;789}790 791// Multiclass for PFCH instructions.792//   e.g. PFCH793let sx = 0, hasSideEffects = 0 in794multiclass PFCHm<string opcStr, bits<8>opc> {795  def rri : RM<opc, (outs), (ins (MEMrri $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),796               [(prefetch ADDRrri:$addr, imm, imm, (i32 1))]>;797  let cy = 0 in798  def rii : RM<opc, (outs), (ins (MEMrii $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),799               [(prefetch ADDRrii:$addr, imm, imm, (i32 1))]>;800  let cz = 0 in801  def zri : RM<opc, (outs), (ins (MEMzri $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),802               [(prefetch ADDRzri:$addr, imm, imm, (i32 1))]>;803  let cy = 0, cz = 0 in804  def zii : RM<opc, (outs), (ins (MEMzii $sz, $sy, $imm32):$addr), !strconcat(opcStr, " $addr"),805               [(prefetch ADDRzii:$addr, imm, imm, (i32 1))]>;806}807 808// Multiclass for CAS instructions.809//   e.g. TS1AML, TS1AMW, TS2AM, and etc.810let Constraints = "$sx = $sd",811    mayStore=1, mayLoad = 1, hasSideEffects = 0 in812multiclass RRCAStgm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,813                    Operand immOp, Operand MEM, ComplexPattern ADDR,814                    SDPatternOperator OpNode = null_frag> {815  def r : RRM<opc, (outs RC:$sx), (ins (MEM $sz, $imm32):$addr, RC:$sy, RC:$sd),816              !strconcat(opcStr, " $sx, $addr, $sy"),817              [(set Ty:$sx, (OpNode ADDR:$addr, Ty:$sy, Ty:$sd))]>;818  let cy = 0 in819  def i : RRM<opc, (outs RC:$sx), (ins (MEM $sz, $imm32):$addr, immOp:$sy, RC:$sd),820              !strconcat(opcStr, " $sx, $addr, $sy"),821              [(set Ty:$sx, (OpNode ADDR:$addr, (Ty immOp:$sy), Ty:$sd))]>;822}823multiclass RRCASm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,824                  Operand immOp, SDPatternOperator OpNode = null_frag> {825  defm ri : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMriRRM, ADDRri, OpNode>;826  let cz = 0 in827  defm zi : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMziRRM, ADDRzi, OpNode>;828}829 830// Multiclass for branch instructions831//   e.g. BCFL, BCFW, BCFD, and etc.832let isBranch = 1, isTerminator = 1, isIndirectBranch = 1, hasSideEffects = 0 in833multiclass BCbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond,834                  Operand ADDR> {835  let bpf = 0 /* NONE */ in836  def "" : CF<opc, (outs), !con(cond, (ins (ADDR $sz, $imm32):$addr)),837              !strconcat(opcStr, " ", cmpStr, "$addr")>;838  let bpf = 2 /* NOT TAKEN */ in839  def _nt : CF<opc, (outs), !con(cond, (ins (ADDR $sz, $imm32):$addr)),840               !strconcat(opcStr, ".nt ", cmpStr, "$addr")>;841  let bpf = 3 /* TAKEN */ in842  def _t : CF<opc, (outs), !con(cond, (ins (ADDR $sz, $imm32):$addr)),843              !strconcat(opcStr, ".t ", cmpStr, "$addr")>;844}845multiclass BCtgm<string opcStr, string cmpStr, bits<8> opc, dag cond> {846  defm ri : BCbpfm<opcStr, cmpStr, opc, cond, MEMriASX>;847  let cz = 0 in defm zi : BCbpfm<opcStr, cmpStr, opc, cond, MEMziASX>;848}849multiclass BCm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc,850               RegisterClass RC, Operand immOp> {851  let DecoderMethod = "DecodeBranchCondition" in852  defm r : BCtgm<opcStr, "$sy, ", opc, (ins CCOp:$cond, RC:$sy)>;853  let DecoderMethod = "DecodeBranchCondition", cy = 0 in854  defm i : BCtgm<opcStr, "$sy, ", opc, (ins CCOp:$cond, immOp:$sy)>;855  let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0,856      cond = 15 /* AT */, isBarrier = 1 in857  defm a : BCtgm<opcStrAt, "", opc, (ins)>;858  let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0,859      cond = 0 /* AF */ in860  defm na : BCtgm<opcStrAf, "", opc, (ins)>;861}862 863// Multiclass for relative branch instructions864//   e.g. BRCFL, BRCFW, BRCFD, and etc.865let isBranch = 1, isTerminator = 1, hasSideEffects = 0 in866multiclass BCRbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond> {867  let bpf = 0 /* NONE */ in868  def "" : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)),869              !strconcat(opcStr, " ", cmpStr, "$imm32")>;870  let bpf = 2 /* NOT TAKEN */ in871  def _nt : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)),872               !strconcat(opcStr, ".nt ", cmpStr, "$imm32")>;873  let bpf = 3 /* TAKEN */ in874  def _t : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)),875              !strconcat(opcStr, ".t ", cmpStr, "$imm32")>;876}877multiclass BCRm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc,878               RegisterClass RC, Operand immOp, Operand zeroOp> {879  defm rr : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cond, RC:$sy, RC:$sz)>;880  let cy = 0 in881  defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cond, immOp:$sy,882                                                    RC:$sz)>;883  let cz = 0 in884  defm rz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cond, RC:$sy,885                                                    zeroOp:$sz)>;886  let cy = 0, cz = 0 in887  defm iz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cond, immOp:$sy,888                                                    zeroOp:$sz)>;889  let cy = 0, sy = 0, cz = 0, sz = 0, cond = 15 /* AT */, isBarrier = 1 in890  defm a : BCRbpfm<opcStrAt, "", opc, (ins)>;891  let cy = 0, sy = 0, cz = 0, sz = 0, cond = 0 /* AF */ in892  defm na : BCRbpfm<opcStrAf, "", opc, (ins)>;893}894 895// Multiclass for communication register instructions.896//   e.g. LCR897let hasSideEffects = 1 in898multiclass LOADCRm<string opcStr, bits<8>opc, RegisterClass RC> {899  def rr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz),900              !strconcat(opcStr, " $sx, $sy, $sz")>;901  let cy = 0 in def ir : RR<opc, (outs RC:$sx), (ins simm7:$sy, RC:$sz),902                            !strconcat(opcStr, " $sx, $sy, $sz")>;903  let cz = 0 in def rz : RR<opc, (outs RC:$sx), (ins RC:$sy, zero:$sz),904                            !strconcat(opcStr, " $sx, $sy, $sz")>;905  let cy = 0, cz = 0 in906  def iz : RR<opc, (outs RC:$sx), (ins simm7:$sy, zero:$sz),907              !strconcat(opcStr, " $sx, $sy, $sz")>;908}909 910// Multiclass for communication register instructions.911//   e.g. SCR912let hasSideEffects = 1 in913multiclass STORECRm<string opcStr, bits<8>opc, RegisterClass RC> {914  def rrr : RR<opc, (outs), (ins RC:$sy, RC:$sz, RC:$sx),915              !strconcat(opcStr, " $sx, $sy, $sz")>;916  let cy = 0 in def irr : RR<opc, (outs), (ins simm7:$sy, RC:$sz, RC:$sx),917                             !strconcat(opcStr, " $sx, $sy, $sz")>;918  let cz = 0 in def rzr : RR<opc, (outs), (ins RC:$sy, zero:$sz, RC:$sx),919                             !strconcat(opcStr, " $sx, $sy, $sz")>;920  let cy = 0, cz = 0 in921  def izr : RR<opc, (outs), (ins simm7:$sy, zero:$sz, RC:$sx),922               !strconcat(opcStr, " $sx, $sy, $sz")>;923}924 925let hasSideEffects = 1, Constraints = "$sx = $sx_in" in926multiclass TSCRm<string opcStr, bits<8>opc, RegisterClass RC> {927  def rrr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, RC:$sx_in),928               !strconcat(opcStr, " $sx, $sy, $sz")>;929  let cy = 0 in def irr : RR<opc, (outs RC:$sx), (ins simm7:$sy, RC:$sz, RC:$sx_in),930                             !strconcat(opcStr, " $sx, $sy, $sz")>;931  let cz = 0 in def rzr : RR<opc, (outs RC:$sx), (ins RC:$sy, zero:$sz, RC:$sx_in),932                             !strconcat(opcStr, " $sx, $sy, $sz")>;933  let cy = 0, cz = 0 in934  def izr : RR<opc, (outs RC:$sx), (ins simm7:$sy, zero:$sz, RC:$sx_in),935               !strconcat(opcStr, " $sx, $sy, $sz")>;936}937 938 939// Multiclass for communication register instructions.940//   e.g. FIDCR941let cz = 0, hasSideEffects = 1 in942multiclass FIDCRm<string opcStr, bits<8>opc, RegisterClass RC> {943  def ri : RR<opc, (outs RC:$sx), (ins RC:$sy, uimm3:$sz),944              !strconcat(opcStr, " $sx, $sy, $sz")>;945  let cy = 0 in def ii : RR<opc, (outs RC:$sx), (ins simm7:$sy, uimm3:$sz),946                            !strconcat(opcStr, " $sx, $sy, $sz")>;947}948 949// Multiclass for LHM instruction.950let mayLoad = 1, hasSideEffects = 0 in951multiclass LHMm<string opcStr, bits<8> opc, RegisterClass RC> {952  def ri : RRMHM<opc, (outs RC:$sx), (ins (MEMriHM $sz, $imm32):$addr),953                 !strconcat(opcStr, " $sx, $addr")>;954  let cz = 0 in955  def zi : RRMHM<opc, (outs RC:$sx), (ins (MEMziHM $sz, $imm32):$addr),956                 !strconcat(opcStr, " $sx, $addr")>;957}958 959// Multiclass for SHM instruction.960let mayStore = 1, hasSideEffects = 0 in961multiclass SHMm<string opcStr, bits<8> opc, RegisterClass RC> {962  def ri : RRMHM<opc, (outs), (ins (MEMriHM $sz, $imm32):$addr, RC:$sx),963                 !strconcat(opcStr, " $sx, $addr")>;964  let cz = 0 in965  def zi : RRMHM<opc, (outs), (ins (MEMziHM $sz, $imm32):$addr, RC:$sx),966                 !strconcat(opcStr, " $sx, $addr")>;967}968 969//===----------------------------------------------------------------------===//970// Instructions971//972// Define all scalar instructions defined in SX-Aurora TSUBASA Architecture973// Guide here.  As those mnemonics, we use mnemonics defined in Vector Engine974// Assembly Language Reference Manual.975//===----------------------------------------------------------------------===//976 977//-----------------------------------------------------------------------------978// Section 8.2 - Load/Store instructions979//-----------------------------------------------------------------------------980 981// Multiclass for generic RM instructions982multiclass RMm<string opcStr, bits<8>opc, RegisterClass RC, bit MoveImm = 0> {983  def rri : RM<opc, (outs RC:$sx), (ins (MEMrri $sz, $sy, $imm32):$addr),984               !strconcat(opcStr, " $sx, $addr"), []>;985  let cy = 0 in986  def rii : RM<opc, (outs RC:$sx), (ins (MEMrii $sz, $sy, $imm32):$addr),987               !strconcat(opcStr, " $sx, $addr"), []>;988  let cz = 0 in989  def zri : RM<opc, (outs RC:$sx), (ins (MEMzri $sz, $sy, $imm32):$addr),990               !strconcat(opcStr, " $sx, $addr"), []>;991  let cy = 0, cz = 0 in992  def zii : RM<opc, (outs RC:$sx), (ins (MEMzii $sz, $sy, $imm32):$addr),993               !strconcat(opcStr, " $sx, $addr"), []> {994    // VE uses LEAzii and LEASLzii as a move immediate instruction, so declare995    // it here.  An instruction declared as MoveImm will be optimized in996    // FoldImmediate later.997    let isMoveImm = MoveImm;998  }999}1000 1001// Section 8.2.1 - LEA1002let isReMaterializable = 1, isAsCheapAsAMove = 1,1003    DecoderMethod = "DecodeLoadI64" in {1004  let cx = 0 in defm LEA : RMm<"lea", 0x06, I64, /* MoveImm */ 1>;1005  let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64, /* MoveImm */ 1>;1006}1007 1008// LEA basic patterns.1009//   Need to be defined here to prioritize LEA over ADX.1010def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;1011def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;1012def : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>;1013def : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>;1014 1015// Multiclass for load instructions.1016let mayLoad = 1, hasSideEffects = 0 in1017multiclass LOADm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty,1018                 SDPatternOperator OpNode = null_frag> {1019  def rri : RM<opc, (outs RC:$sx), (ins (MEMrri $sz, $sy, $imm32):$addr),1020               !strconcat(opcStr, " $sx, $addr"),1021               [(set Ty:$sx, (OpNode ADDRrri:$addr))]>;1022  let cy = 0 in1023  def rii : RM<opc, (outs RC:$sx), (ins (MEMrii $sz, $sy, $imm32):$addr),1024               !strconcat(opcStr, " $sx, $addr"),1025               [(set Ty:$sx, (OpNode ADDRrii:$addr))]>;1026  let cz = 0 in1027  def zri : RM<opc, (outs RC:$sx), (ins (MEMzri $sz, $sy, $imm32):$addr),1028               !strconcat(opcStr, " $sx, $addr"),1029               [(set Ty:$sx, (OpNode ADDRzri:$addr))]>;1030  let cy = 0, cz = 0 in1031  def zii : RM<opc, (outs RC:$sx), (ins (MEMzii $sz, $sy, $imm32):$addr),1032               !strconcat(opcStr, " $sx, $addr"),1033               [(set Ty:$sx, (OpNode ADDRzii:$addr))]>;1034}1035 1036// Section 8.2.2 - LDS1037let DecoderMethod = "DecodeLoadI64" in1038defm LD : LOADm<"ld", 0x01, I64, i64, load>;1039def : Pat<(f64 (load ADDRrri:$addr)), (LDrri MEMrri:$addr)>;1040def : Pat<(f64 (load ADDRrii:$addr)), (LDrii MEMrii:$addr)>;1041def : Pat<(f64 (load ADDRzri:$addr)), (LDzri MEMzri:$addr)>;1042def : Pat<(f64 (load ADDRzii:$addr)), (LDzii MEMzii:$addr)>;1043 1044// Section 8.2.3 - LDU1045let DecoderMethod = "DecodeLoadF32" in1046defm LDU : LOADm<"ldu", 0x02, F32, f32, load>;1047 1048// Section 8.2.4 - LDL1049let DecoderMethod = "DecodeLoadI32" in1050defm LDLSX : LOADm<"ldl.sx", 0x03, I32, i32, load>;1051let cx = 1, DecoderMethod = "DecodeLoadI32" in1052defm LDLZX : LOADm<"ldl.zx", 0x03, I32, i32, load>;1053 1054// Section 8.2.5 - LD2B1055let DecoderMethod = "DecodeLoadI32" in1056defm LD2BSX : LOADm<"ld2b.sx", 0x04, I32, i32, sextloadi16>;1057let cx = 1, DecoderMethod = "DecodeLoadI32" in1058defm LD2BZX : LOADm<"ld2b.zx", 0x04, I32, i32, zextloadi16>;1059 1060// Section 8.2.6 - LD1B1061let DecoderMethod = "DecodeLoadI32" in1062defm LD1BSX : LOADm<"ld1b.sx", 0x05, I32, i32, sextloadi8>;1063let cx = 1, DecoderMethod = "DecodeLoadI32" in1064defm LD1BZX : LOADm<"ld1b.zx", 0x05, I32, i32, zextloadi8>;1065 1066// LDQ pseudo instructions1067let mayLoad = 1, hasSideEffects = 0 in {1068  def LDQrii : Pseudo<(outs F128:$dest), (ins MEMrii:$addr),1069                      "# pseudo ldq $dest, $addr",1070                      [(set f128:$dest, (load ADDRrii:$addr))]>;1071}1072 1073// Multiclass for store instructions.1074let mayStore = 1 in1075multiclass STOREm<string opcStr, bits<8> opc, RegisterClass RC, ValueType Ty,1076                  SDPatternOperator OpNode = null_frag> {1077  def rri : RM<opc, (outs), (ins (MEMrri $sz, $sy, $imm32):$addr, RC:$sx),1078               !strconcat(opcStr, " $sx, $addr"),1079               [(OpNode Ty:$sx, ADDRrri:$addr)]>;1080  let cy = 0 in1081  def rii : RM<opc, (outs), (ins (MEMrii $sz, $sy, $imm32):$addr, RC:$sx),1082               !strconcat(opcStr, " $sx, $addr"),1083               [(OpNode Ty:$sx, ADDRrii:$addr)]>;1084  let cz = 0 in1085  def zri : RM<opc, (outs), (ins (MEMzri $sz, $sy, $imm32):$addr, RC:$sx),1086               !strconcat(opcStr, " $sx, $addr"),1087               [(OpNode Ty:$sx, ADDRzri:$addr)]>;1088  let cy = 0, cz = 0 in1089  def zii : RM<opc, (outs), (ins (MEMzii $sz, $sy, $imm32):$addr, RC:$sx),1090               !strconcat(opcStr, " $sx, $addr"),1091               [(OpNode Ty:$sx, ADDRzii:$addr)]>;1092}1093 1094// Section 8.2.7 - STS1095let DecoderMethod = "DecodeStoreI64" in1096defm ST : STOREm<"st", 0x11, I64, i64, store>;1097def : Pat<(store f64:$src, ADDRrri:$addr), (STrri MEMrri:$addr, $src)>;1098def : Pat<(store f64:$src, ADDRrii:$addr), (STrii MEMrii:$addr, $src)>;1099def : Pat<(store f64:$src, ADDRzri:$addr), (STzri MEMzri:$addr, $src)>;1100def : Pat<(store f64:$src, ADDRzii:$addr), (STzii MEMzii:$addr, $src)>;1101 1102// Section 8.2.8 - STU1103let DecoderMethod = "DecodeStoreF32" in1104defm STU : STOREm<"stu", 0x12, F32, f32, store>;1105 1106// Section 8.2.9 - STL1107let DecoderMethod = "DecodeStoreI32" in1108defm STL : STOREm<"stl", 0x13, I32, i32, store>;1109 1110// Section 8.2.10 - ST2B1111let DecoderMethod = "DecodeStoreI32" in1112defm ST2B : STOREm<"st2b", 0x14, I32, i32, truncstorei16>;1113 1114// Section 8.2.11 - ST1B1115let DecoderMethod = "DecodeStoreI32" in1116defm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>;1117 1118// STQ pseudo instructions1119let mayStore = 1, hasSideEffects = 0 in {1120  def STQrii : Pseudo<(outs), (ins MEMrii:$addr, F128:$sx),1121                      "# pseudo stq $sx, $addr",1122                      [(store f128:$sx, ADDRrii:$addr)]>;1123}1124 1125// Section 8.2.12 - DLDS1126let DecoderMethod = "DecodeLoadI64" in1127defm DLD : LOADm<"dld", 0x09, I64, i64, load>;1128 1129// Section 8.2.13 - DLDU1130let DecoderMethod = "DecodeLoadF32" in1131defm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>;1132 1133// Section 8.2.14 - DLDL1134let DecoderMethod = "DecodeLoadI32" in1135defm DLDLSX : LOADm<"dldl.sx", 0x0b, I32, i32, load>;1136let cx = 1, DecoderMethod = "DecodeLoadI32" in1137defm DLDLZX : LOADm<"dldl.zx", 0x0b, I32, i32, load>;1138 1139// Section 8.2.15 - PFCH1140let DecoderMethod = "DecodeASX" in1141defm PFCH : PFCHm<"pfch", 0x0c>;1142 1143// Section 8.2.16 - TS1AM (Test and Set 1 AM)1144let DecoderMethod = "DecodeTS1AMI64" in1145defm TS1AML : RRCASm<"ts1am.l", 0x42, I64, i64, uimm7>;1146let DecoderMethod = "DecodeTS1AMI32", cx = 1 in1147defm TS1AMW : RRCASm<"ts1am.w", 0x42, I32, i32, uimm7>;1148 1149// Section 8.2.17 - TS2AM (Test and Set 2 AM)1150let DecoderMethod = "DecodeTS1AMI64" in1151defm TS2AM : RRCASm<"ts2am", 0x43, I64, i64, uimm7>;1152 1153// Section 8.2.18 - TS3AM (Test and Set 3 AM)1154let DecoderMethod = "DecodeTS1AMI64" in1155defm TS3AM : RRCASm<"ts3am", 0x52, I64, i64, uimm1>;1156 1157// Section 8.2.19 - ATMAM (Atomic AM)1158let DecoderMethod = "DecodeTS1AMI64" in1159defm ATMAM : RRCASm<"atmam", 0x53, I64, i64, uimm0to2>;1160 1161// Section 8.2.20 - CAS (Compare and Swap)1162let DecoderMethod = "DecodeCASI64" in1163defm CASL : RRCASm<"cas.l", 0x62, I64, i64, simm7, atomic_cmp_swap_i64>;1164let DecoderMethod = "DecodeCASI32", cx = 1 in1165defm CASW : RRCASm<"cas.w", 0x62, I32, i32, simm7, atomic_cmp_swap_i32>;1166 1167//-----------------------------------------------------------------------------1168// Section 8.3 - Transfer Control Instructions1169//-----------------------------------------------------------------------------1170 1171// Section 8.3.1 - FENCE (Fence)1172let hasSideEffects = 1 in {1173  let avo = 1 in def FENCEI : RRFENCE<0x20, (outs), (ins), "fencei">;1174  def FENCEM : RRFENCE<0x20, (outs), (ins uimm2:$kind), "fencem $kind"> {1175    bits<2> kind;1176    let lf = kind{1};1177    let sf = kind{0};1178  }1179  def FENCEC : RRFENCE<0x20, (outs), (ins uimm3:$kind), "fencec $kind"> {1180    bits<3> kind;1181    let c2 = kind{2};1182    let c1 = kind{1};1183    let c0 = kind{0};1184  }1185}1186 1187// Section 8.3.2 - SVOB (Set Vector Out-of-order memory access Boundary)1188let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in1189def SVOB : RR<0x30, (outs), (ins), "svob">;1190 1191//-----------------------------------------------------------------------------1192// Section 8.4 - Fixed-point Operation Instructions1193//-----------------------------------------------------------------------------1194 1195// Section 8.4.1 - ADD (Add)1196defm ADDUL : RRm<"addu.l", 0x48, I64, i64>;1197let cx = 1 in defm ADDUW : RRm<"addu.w", 0x48, I32, i32>;1198 1199// Section 8.4.2 - ADS (Add Single)1200defm ADDSWSX : RRm<"adds.w.sx", 0x4A, I32, i32, add>;1201let cx = 1 in defm ADDSWZX : RRm<"adds.w.zx", 0x4A, I32, i32>;1202 1203// Section 8.4.3 - ADX (Add)1204defm ADDSL : RRm<"adds.l", 0x59, I64, i64, add>;1205 1206// Section 8.4.4 - SUB (Subtract)1207defm SUBUL : RRNCm<"subu.l", 0x58, I64, i64>;1208let cx = 1 in defm SUBUW : RRNCm<"subu.w", 0x58, I32, i32>;1209 1210// Section 8.4.5 - SBS (Subtract Single)1211defm SUBSWSX : RRNCm<"subs.w.sx", 0x5A, I32, i32, sub>;1212let cx = 1 in defm SUBSWZX : RRNCm<"subs.w.zx", 0x5A, I32, i32>;1213 1214// Section 8.4.6 - SBX (Subtract)1215defm SUBSL : RRNCm<"subs.l", 0x5B, I64, i64, sub>;1216 1217// Section 8.4.7 - MPY (Multiply)1218defm MULUL : RRm<"mulu.l", 0x49, I64, i64>;1219let cx = 1 in defm MULUW : RRm<"mulu.w", 0x49, I32, i32>;1220 1221// Section 8.4.8 - MPS (Multiply Single)1222defm MULSWSX : RRm<"muls.w.sx", 0x4B, I32, i32, mul>;1223let cx = 1 in defm MULSWZX : RRm<"muls.w.zx", 0x4B, I32, i32>;1224 1225// Section 8.4.9 - MPX (Multiply)1226defm MULSL : RRm<"muls.l", 0x6E, I64, i64, mul>;1227 1228// Section 8.4.10 - MPD (Multiply)1229defm MULSLW : RRbm<"muls.l.w", 0x6B, I64, i64, I32, i32>;1230 1231// Section 8.4.11 - DIV (Divide)1232defm DIVUL : RRNCm<"divu.l", 0x6F, I64, i64, udiv>;1233let cx = 1 in defm DIVUW : RRNCm<"divu.w", 0x6F, I32, i32, udiv>;1234 1235// Section 8.4.12 - DVS (Divide Single)1236defm DIVSWSX : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>;1237let cx = 1 in defm DIVSWZX : RRNCm<"divs.w.zx", 0x7B, I32, i32>;1238 1239// Section 8.4.13 - DVX (Divide)1240defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>;1241 1242// Section 8.4.14 - CMP (Compare)1243defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64, cmpu>;1244let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32, cmpu>;1245 1246// Section 8.4.15 - CPS (Compare Single)1247defm CMPSWSX : RRNCm<"cmps.w.sx", 0x7A, I32, i32>;1248let cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32, cmpi>;1249 1250// Section 8.4.16 - CPX (Compare)1251defm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64, cmpi>;1252 1253// Section 8.4.17 - CMS (Compare and Select Maximum/Minimum Single)1254// cx: sx/zx, cw: max/min1255defm MAXSWSX : RRm<"maxs.w.sx", 0x78, I32, i32, smax>;1256let cx = 1 in defm MAXSWZX : RRm<"maxs.w.zx", 0x78, I32, i32>;1257let cw = 1 in defm MINSWSX : RRm<"mins.w.sx", 0x78, I32, i32, smin>;1258let cx = 1, cw = 1 in defm MINSWZX : RRm<"mins.w.zx", 0x78, I32, i32>;1259 1260// Section 8.4.18 - CMX (Compare and Select Maximum/Minimum)1261defm MAXSL : RRm<"maxs.l", 0x68, I64, i64, smax>;1262let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64, smin>;1263 1264//-----------------------------------------------------------------------------1265// Section 8.5 - Logical Operation Instructions1266//-----------------------------------------------------------------------------1267 1268// Section 8.5.1 - AND (AND)1269defm AND : RRm<"and", 0x44, I64, i64, and>;1270 1271// Section 8.5.2 - OR (OR)1272let isReMaterializable = 1, isAsCheapAsAMove = 1 in1273defm OR : RRm<"or", 0x45, I64, i64, or, simm7, mimm, /* MoveImm */ 1>;1274 1275// Section 8.5.3 - XOR (Exclusive OR)1276defm XOR : RRm<"xor", 0x46, I64, i64, xor>;1277 1278// Section 8.5.4 - EQV (Equivalence)1279defm EQV : RRm<"eqv", 0x47, I64, i64>;1280 1281// Section 8.5.5 - NND (Negate AND)1282def and_not : PatFrags<(ops node:$x, node:$y),1283                       [(and (not node:$x), node:$y)]>;1284defm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>;1285 1286// Section 8.5.6 - MRG (Merge)1287defm MRG : RRMRGm<"mrg", 0x56, I64>;1288 1289// Section 8.5.7 - LDZ (Leading Zero Count)1290def ctlz_pat : PatFrags<(ops node:$src),1291                        [(ctlz node:$src),1292                         (ctlz_zero_undef node:$src)]>;1293defm LDZ : RRI1m<"ldz", 0x67, I64, i64, ctlz_pat>;1294 1295// Section 8.5.8 - PCNT (Population Count)1296defm PCNT : RRI1m<"pcnt", 0x38, I64, i64, ctpop>;1297 1298// Section 8.5.9 - BRV (Bit Reverse)1299defm BRV : RRI1m<"brv", 0x39, I64, i64, bitreverse>;1300 1301// Section 8.5.10 - BSWP (Byte Swap)1302defm BSWP : RRSWPm<"bswp", 0x2B, I64, i64>;1303 1304def : Pat<(i64 (bswap i64:$src)),1305          (BSWPri $src, 0)>;1306def : Pat<(i64 (bswap (i64 mimm:$src))),1307          (BSWPmi (MIMM $src), 0)>;1308def : Pat<(i32 (bswap i32:$src)),1309          (EXTRACT_SUBREG1310              (BSWPri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub_i32), 1),1311              sub_i32)>;1312def : Pat<(i32 (bswap (i32 mimm:$src))),1313          (EXTRACT_SUBREG (BSWPmi (MIMM $src), 1), sub_i32)>;1314 1315// Section 8.5.11 - CMOV (Conditional Move)1316let cw = 0, cw2 = 0 in1317defm CMOVL : RRCMOVm<"cmov.l.${cfw}", 0x3B, I64, i64, cmov>;1318let cw = 1, cw2 = 0 in1319defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32, i32, cmov>;1320let cw = 0, cw2 = 1 in1321defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64, cmov, simm7fp>;1322let cw = 1, cw2 = 1 in1323defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32, cmov, simm7fp>;1324def : MnemonicAlias<"cmov.l", "cmov.l.at">;1325def : MnemonicAlias<"cmov.w", "cmov.w.at">;1326def : MnemonicAlias<"cmov.d", "cmov.d.at">;1327def : MnemonicAlias<"cmov.s", "cmov.s.at">;1328 1329//-----------------------------------------------------------------------------1330// Section 8.6 - Shift Operation Instructions1331//-----------------------------------------------------------------------------1332 1333// Section 8.6.1 - SLL (Shift Left Logical)1334defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;1335 1336// Section 8.6.2 - SLD (Shift Left Double)1337defm SLD : RRILDm<"sld", 0x64, I64>;1338 1339// Section 8.6.3 - SRL (Shift Right Logical)1340defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;1341 1342// Section 8.6.4 - SRD (Shift Right Double)1343defm SRD : RRIRDm<"srd", 0x74, I64>;1344 1345// Section 8.6.5 - SLA (Shift Left Arithmetic)1346defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;1347let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;1348 1349// Section 8.6.6 - SLAX (Shift Left Arithmetic)1350defm SLAL : RRIm<"sla.l", 0x57, I64, i64>;1351 1352// Section 8.6.7 - SRA (Shift Right Arithmetic)1353defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;1354let cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>;1355 1356// Section 8.6.8 - SRAX (Shift Right Arithmetic)1357defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>;1358 1359def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))),1360          (EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),1361            $src, sub_i32), !add(32, 64)), imm:$val), sub_i32)>;1362def : Pat<(i32 (srl i32:$src, i32:$val)),1363          (EXTRACT_SUBREG (SRLrr (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),1364            $src, sub_i32), !add(32, 64)), $val), sub_i32)>;1365 1366//-----------------------------------------------------------------------------1367// Section 8.7 - Floating-point Arithmetic Instructions1368//-----------------------------------------------------------------------------1369 1370// Section 8.7.1 - FAD (Floating Add)1371defm FADDD : RRFm<"fadd.d", 0x4C, I64, f64, fadd>;1372let cx = 1 in1373defm FADDS : RRFm<"fadd.s", 0x4C, F32, f32, fadd, simm7fp, mimmfp32>;1374 1375// Section 8.7.2 - FSB (Floating Subtract)1376defm FSUBD : RRFm<"fsub.d", 0x5C, I64, f64, fsub>;1377let cx = 1 in1378defm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub, simm7fp, mimmfp32>;1379 1380// Section 8.7.3 - FMP (Floating Multiply)1381defm FMULD : RRFm<"fmul.d", 0x4D, I64, f64, fmul>;1382let cx = 1 in1383defm FMULS : RRFm<"fmul.s", 0x4D, F32, f32, fmul, simm7fp, mimmfp32>;1384 1385// Section 8.7.4 - FDV (Floating Divide)1386defm FDIVD : RRFm<"fdiv.d", 0x5D, I64, f64, fdiv>;1387let cx = 1 in1388defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;1389 1390// Section 8.7.5 - FCP (Floating Compare)1391defm FCMPD : RRFm<"fcmp.d", 0x7E, I64, f64, cmpf>;1392let cx = 1 in1393defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, cmpf, simm7fp, mimmfp32>;1394 1395// Section 8.7.6 - CMS (Compare and Select Maximum/Minimum Single)1396// cx: double/float, cw: max/min1397let cw = 0, cx = 0 in1398defm FMAXD : RRFm<"fmax.d", 0x3E, I64, f64, fmaxnum>;1399let cw = 0, cx = 1 in1400defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>;1401let cw = 1, cx = 0 in1402defm FMIND : RRFm<"fmin.d", 0x3E, I64, f64, fminnum>;1403let cw = 1, cx = 1 in1404defm FMINS : RRFm<"fmin.s", 0x3E, F32, f32, fminnum, simm7fp, mimmfp32>;1405 1406// Section 8.7.7 - FAQ (Floating Add Quadruple)1407defm FADDQ : RRFm<"fadd.q", 0x6C, F128, f128, fadd>;1408 1409// Section 8.7.8 - FSQ (Floating Subtract Quadruple)1410defm FSUBQ : RRFm<"fsub.q", 0x7C, F128, f128, fsub>;1411 1412// Section 8.7.9 - FMQ (Floating Subtract Quadruple)1413defm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128, fmul>;1414 1415// Section 8.7.10 - FCQ (Floating Compare Quadruple)1416defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, cmpq, simm7fp,1417                    mimmfp>;1418 1419// Section 8.7.11 - FIX (Convert to Fixed Point)1420// cx: double/float, cw: sx/zx, sz{0-3} = round1421let cx = 0, cw = 0 /* sign extend */ in1422defm CVTWDSX : CVTRDm<"cvt.w.d.sx", 0x4E, I32, I64>;1423let cx = 0, cw = 1 /* zero extend */ in1424defm CVTWDZX : CVTRDm<"cvt.w.d.zx", 0x4E, I32, I64>;1425let cx = 1, cw = 0 /* sign extend */ in1426defm CVTWSSX : CVTRDm<"cvt.w.s.sx", 0x4E, I32, F32>;1427let cx = 1, cw = 1 /* zero extend */ in1428defm CVTWSZX : CVTRDm<"cvt.w.s.zx", 0x4E, I32, F32>;1429 1430// Section 8.7.12 - FIXX (Convert to Fixed Point)1431defm CVTLD : CVTRDm<"cvt.l.d", 0x4F, I64, I64>;1432 1433// Section 8.7.13 - FLT (Convert to Floating Point)1434defm CVTDW : CVTm<"cvt.d.w", 0x5E, I64, f64, I32, i32, sint_to_fp>;1435let cx = 1 in1436defm CVTSW : CVTm<"cvt.s.w", 0x5E, F32, f32, I32, i32, sint_to_fp>;1437 1438// Section 8.7.14 - FLTX (Convert to Floating Point)1439defm CVTDL : CVTm<"cvt.d.l", 0x5F, I64, f64, I64, i64, sint_to_fp>;1440 1441// Section 8.7.15 - CVS (Convert to Single-format)1442defm CVTSD : CVTm<"cvt.s.d", 0x1F, F32, f32, I64, f64, fpround>;1443let cx = 1 in1444defm CVTSQ : CVTm<"cvt.s.q", 0x1F, F32, f32, F128, f128, fpround>;1445 1446// Section 8.7.16 - CVD (Convert to Double-format)1447defm CVTDS : CVTm<"cvt.d.s", 0x0F, I64, f64, F32, f32, fpextend>;1448let cx = 1 in1449defm CVTDQ : CVTm<"cvt.d.q", 0x0F, I64, f64, F128, f128, fpround>;1450 1451// Section 8.7.17 - CVQ (Convert to Single-format)1452defm CVTQD : CVTm<"cvt.q.d", 0x2D, F128, f128, I64, f64, fpextend>;1453let cx = 1 in1454defm CVTQS : CVTm<"cvt.q.s", 0x2D, F128, f128, F32, f32, fpextend>;1455 1456//-----------------------------------------------------------------------------1457// Section 8.8 - Branch instructions1458//-----------------------------------------------------------------------------1459 1460// Section 8.8.1 - BC (Branch on Codition)1461defm BCFL : BCm<"b${cond}.l", "b.l", "baf.l", 0x19, I64, simm7>;1462 1463// Indirect branch aliases1464def : Pat<(brind I64:$reg), (BCFLari_t $reg, 0)>;1465def : Pat<(brind tblockaddress:$imm), (BCFLazi_t 0, $imm)>;1466 1467// Return instruction is a special case of jump.1468let Uses = [SX10], bpf = 3 /* TAKEN */, cond = 15 /* AT */, cy = 0, sy = 0,1469    sz = 10 /* SX10 */, imm32 = 0, isReturn = 1, isTerminator = 1,1470    isBarrier = 1, isCodeGenOnly = 1, hasSideEffects = 0 in1471def RET : CF<0x19, (outs), (ins), "b.l.t (, %s10)", [(retglue)]>;1472 1473// Section 8.8.2 - BCS (Branch on Condition Single)1474defm BCFW : BCm<"b${cond}.w", "b.w", "baf.w", 0x1B, I32, simm7>;1475 1476// Section 8.8.3 - BCF (Branch on Condition Floating Point)1477defm BCFD : BCm<"b${cond}.d", "b.d", "baf.d", 0x1C, I64, simm7fp>;1478let cx = 1 in1479defm BCFS : BCm<"b${cond}.s", "b.s", "baf.s", 0x1C, F32, simm7fp>;1480 1481// Section 8.8.4 - BCR (Branch on Condition Relative)1482let cx = 0, cx2 = 0 in1483defm BRCFL : BCRm<"br${cond}.l", "br.l", "braf.l", 0x18, I64, simm7, zero>;1484let cx = 1, cx2 = 0 in1485defm BRCFW : BCRm<"br${cond}.w", "br.w", "braf.w", 0x18, I32, simm7, zero>;1486let cx = 0, cx2 = 1 in1487defm BRCFD : BCRm<"br${cond}.d", "br.d", "braf.d", 0x18, I64, simm7fp, zerofp>;1488let cx = 1, cx2 = 1 in1489defm BRCFS : BCRm<"br${cond}.s", "br.s", "braf.s", 0x18, F32, simm7fp, zerofp>;1490 1491// Section 8.8.5 - BSIC (Branch and Save IC)1492let isCall = 1, hasSideEffects = 0, DecoderMethod = "DecodeCall" in1493defm BSIC : RMm<"bsic", 0x08, I64>;1494 1495// Call instruction is a special case of BSIC.1496let Defs = [SX10], sx = 10 /* SX10 */, cy = 0, sy = 0, imm32 = 0,1497    isCall = 1, isCodeGenOnly = 1, hasSideEffects = 0 in1498def CALLr : RM<0x08, (outs), (ins I64:$sz, variable_ops),1499               "bsic %s10, (, $sz)", [(call i64:$sz)]>;1500 1501//-----------------------------------------------------------------------------1502// Section 8.19 - Control Instructions1503//-----------------------------------------------------------------------------1504 1505// Section 8.19.1 - SIC (Save Instruction Counter)1506let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [IC] in1507def SIC : RR<0x28, (outs I32:$sx), (ins), "sic $sx">;1508 1509// Section 8.19.2 - LPM (Load Program Mode Flags)1510let sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in1511def LPM : RR<0x3a, (outs), (ins I64:$sy), "lpm $sy">;1512 1513// Section 8.19.3 - SPM (Save Program Mode Flags)1514let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [PSW] in1515def SPM : RR<0x2a, (outs I64:$sx), (ins), "spm $sx">;1516 1517// Section 8.19.4 - LFR (Load Flag Register)1518let sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in {1519  def LFRr : RR<0x69, (outs), (ins I64:$sy), "lfr $sy">;1520  let cy = 0 in def LFRi : RR<0x69, (outs), (ins uimm6:$sy), "lfr $sy">;1521}1522 1523// Section 8.19.5 - SFR (Save Flag Register)1524let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [PSW] in1525def SFR : RR<0x29, (outs I64:$sx), (ins), "sfr $sx">;1526 1527// Section 8.19.6 - SMIR (Save Miscellaneous Register)1528let cy = 0, cz = 0, sz = 0, hasSideEffects = 1 in {1529  def SMIR : RR<0x22, (outs I64:$sx), (ins MISC:$sy), "smir $sx, $sy">;1530}1531 1532// Section 8.19.7 - NOP (No Operation)1533let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in1534def NOP : RR<0x79, (outs), (ins), "nop">;1535 1536// Section 8.19.8 - MONC (Monitor Call)1537let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in {1538  def MONC : RR<0x3F, (outs), (ins), "monc">;1539  let cx = 1, isTrap = 1 in def MONCHDB : RR<0x3F, (outs), (ins), "monc.hdb">;1540}1541 1542// Section 8.19.9 - LCR (Load Communication Register)1543defm LCR : LOADCRm<"lcr", 0x40, I64>;1544 1545// Section 8.19.10 - SCR (Save Communication Register)1546defm SCR : STORECRm<"scr", 0x50, I64>;1547 1548// Section 8.19.11 - TSCR (Test & Set Communication Register)1549defm TSCR : TSCRm<"tscr", 0x41, I64>;1550 1551// Section 8.19.12 - FIDCR (Fetch & Increment/Decrement CR)1552defm FIDCR : FIDCRm<"fidcr", 0x51, I64>;1553 1554//-----------------------------------------------------------------------------1555// Section 8.20 - Host Memory Access Instructions1556//-----------------------------------------------------------------------------1557 1558// Section 8.20.1 - LHM (Load Host Memory)1559let ry = 3, DecoderMethod = "DecodeLoadASI64" in1560defm LHML : LHMm<"lhm.l", 0x21, I64>;1561let ry = 2, DecoderMethod = "DecodeLoadASI64" in1562defm LHMW : LHMm<"lhm.w", 0x21, I64>;1563let ry = 1, DecoderMethod = "DecodeLoadASI64" in1564defm LHMH : LHMm<"lhm.h", 0x21, I64>;1565let ry = 0, DecoderMethod = "DecodeLoadASI64" in1566defm LHMB : LHMm<"lhm.b", 0x21, I64>;1567 1568// Section 8.20.2 - SHM (Store Host Memory)1569let ry = 3, DecoderMethod = "DecodeStoreASI64" in1570defm SHML : SHMm<"shm.l", 0x31, I64>;1571let ry = 2, DecoderMethod = "DecodeStoreASI64" in1572defm SHMW : SHMm<"shm.w", 0x31, I64>;1573let ry = 1, DecoderMethod = "DecodeStoreASI64" in1574defm SHMH : SHMm<"shm.h", 0x31, I64>;1575let ry = 0, DecoderMethod = "DecodeStoreASI64" in1576defm SHMB : SHMm<"shm.b", 0x31, I64>;1577 1578//===----------------------------------------------------------------------===//1579// Instructions for CodeGenOnly1580//===----------------------------------------------------------------------===//1581 1582//===----------------------------------------------------------------------===//1583// Pattern Matchings1584//===----------------------------------------------------------------------===//1585 1586// Basic cast between registers.  This is often used in ISel patterns, so make1587// them as OutPatFrag.1588def i2l : OutPatFrag<(ops node:$exp),1589                     (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $exp, sub_i32)>;1590def l2i : OutPatFrag<(ops node:$exp),1591                     (EXTRACT_SUBREG $exp, sub_i32)>;1592def f2l : OutPatFrag<(ops node:$exp),1593                     (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $exp, sub_f32)>;1594def l2f : OutPatFrag<(ops node:$exp),1595                     (EXTRACT_SUBREG $exp, sub_f32)>;1596 1597// Zero out subregisters.1598def zero_i32 : OutPatFrag<(ops node:$expr),1599                          (ANDrm $expr, 32)>;1600def zero_f32 : OutPatFrag<(ops node:$expr),1601                          (ANDrm $expr, !add(32, 64))>;1602 1603// Small immediates.1604def : Pat<(i32 simm7:$val), (l2i (ORim (LO7 $val), 0))>;1605def : Pat<(i64 simm7:$val), (ORim (LO7 $val), 0)>;1606// Medium immediates.1607def : Pat<(i32 simm32:$val), (l2i (LEAzii 0, 0, (LO32 $val)))>;1608def : Pat<(i64 simm32:$val), (LEAzii 0, 0, (LO32 $val))>;1609def : Pat<(i64 uimm32:$val), (zero_f32 (LEAzii 0, 0, (LO32 $val)))>;1610// Arbitrary immediates.1611def : Pat<(i64 lozero:$val),1612          (LEASLzii 0, 0, (HI32 imm:$val))>;1613def : Pat<(i64 lomsbzero:$val),1614          (LEASLrii (LEAzii 0, 0, (LO32 imm:$val)), 0, (HI32 imm:$val))>;1615def : Pat<(i64 imm:$val),1616          (LEASLrii (ANDrm (LEAzii 0, 0, (LO32 imm:$val)), !add(32, 64)), 0,1617                    (HI32 imm:$val))>;1618 1619// LEA patterns1620def lea_add : PatFrags<(ops node:$base, node:$idx, node:$disp),1621                       [(add (add node:$base, node:$idx), node:$disp),1622                        (add (add node:$base, node:$disp), node:$idx),1623                        (add node:$base, (add $idx, $disp))]>;1624def : Pat<(lea_add I64:$base, simm7:$idx, simm32:$disp),1625          (LEArii $base, (LO7 $idx), (LO32 $disp))>;1626def : Pat<(lea_add I64:$base, I64:$idx, simm32:$disp),1627          (LEArri $base, $idx, (LO32 $disp))>;1628def : Pat<(lea_add I64:$base, simm7:$idx, lozero:$disp),1629          (LEASLrii $base, (LO7 $idx), (HI32 $disp))>;1630def : Pat<(lea_add I64:$base, I64:$idx, lozero:$disp),1631          (LEASLrri $base, $idx, (HI32 $disp))>;1632 1633// Address calculation patterns and optimizations1634//1635// Generate following instructions:1636//   1. LEA %reg, label@LO321637//      AND %reg, %reg, (32)01638//   2. LEASL %reg, label@HI321639//   3. (LEA %reg, label@LO32)1640//      (AND %reg, %reg, (32)0)1641//      LEASL %reg, label@HI32(, %reg)1642//   4. (LEA %reg, label@LO32)1643//      (AND %reg, %reg, (32)0)1644//      LEASL %reg, label@HI32(%reg, %got)1645//1646def velo_only : OutPatFrag<(ops node:$lo),1647                           (ANDrm (LEAzii 0, 0, $lo), !add(32, 64))>;1648def vehi_only : OutPatFrag<(ops node:$hi),1649                           (LEASLzii 0, 0, $hi)>;1650def vehi_lo : OutPatFrag<(ops node:$hi, node:$lo),1651                         (LEASLrii $lo, 0, $hi)>;1652def vehi_lo_imm : OutPatFrag<(ops node:$hi, node:$lo, node:$idx),1653                             (LEASLrii $lo, $idx, $hi)>;1654def vehi_baselo : OutPatFrag<(ops node:$base, node:$hi, node:$lo),1655                             (LEASLrri $base, $lo, $hi)>;1656foreach type = [ "tblockaddress", "tconstpool", "texternalsym", "tglobaladdr",1657                 "tglobaltlsaddr", "tjumptable" ] in {1658  def : Pat<(VElo !cast<SDNode>(type):$lo), (velo_only $lo)>;1659  def : Pat<(VEhi !cast<SDNode>(type):$hi), (vehi_only $hi)>;1660  def : Pat<(add (VEhi !cast<SDNode>(type):$hi), I64:$lo), (vehi_lo $hi, $lo)>;1661  def : Pat<(add (add (VEhi !cast<SDNode>(type):$hi), I64:$lo), simm7:$val),1662            (vehi_lo_imm $hi, $lo, (LO7 $val))>;1663  def : Pat<(add I64:$base, (add (VEhi !cast<SDNode>(type):$hi), I64:$lo)),1664            (vehi_baselo $base, $hi, $lo)>;1665}1666 1667// floating point1668def : Pat<(f32 fpimm:$val),1669          (EXTRACT_SUBREG (LEASLzii 0, 0, (HIFP32 $val)), sub_f32)>;1670def : Pat<(f64 fplozero:$val),1671          (LEASLzii 0, 0, (HIFP32 $val))>;1672def : Pat<(f64 fplomsbzero:$val),1673          (LEASLrii (LEAzii 0, 0, (LOFP32 $val)), 0, (HIFP32 $val))>;1674def : Pat<(f64 fpimm:$val),1675          (LEASLrii (ANDrm (LEAzii 0, 0, (LOFP32 $val)), !add(32, 64)), 0,1676                    (HIFP32 $val))>;1677 1678// The same integer registers are used for i32 and i64 values.1679// When registers hold i32 values, the high bits are unused.1680 1681// TODO Use standard expansion for shift-based lowering of sext_inreg1682 1683// Cast to i11684def : Pat<(sext_inreg I32:$src, i1),1685          (SRAWSXri (SLAWSXri $src, 31), 31)>;1686def : Pat<(sext_inreg I64:$src, i1),1687          (SRALri (SLLri $src, 63), 63)>;1688 1689// Cast to i81690def : Pat<(sext_inreg I32:$src, i8),1691          (SRAWSXri (SLAWSXri $src, 24), 24)>;1692def : Pat<(sext_inreg I64:$src, i8),1693          (SRALri (SLLri $src, 56), 56)>;1694def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8),1695          (EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>;1696def : Pat<(i32 (and (trunc i64:$src), 0xff)),1697          (EXTRACT_SUBREG (ANDrm $src, !add(56, 64)), sub_i32)>;1698 1699// Cast to i161700def : Pat<(sext_inreg I32:$src, i16),1701          (SRAWSXri (SLAWSXri $src, 16), 16)>;1702def : Pat<(sext_inreg I64:$src, i16),1703          (SRALri (SLLri $src, 48), 48)>;1704def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16),1705          (EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>;1706def : Pat<(i32 (and (trunc i64:$src), 0xffff)),1707          (EXTRACT_SUBREG (ANDrm $src, !add(48, 64)), sub_i32)>;1708 1709// Cast to i321710def : Pat<(i32 (trunc i64:$src)), (l2i (zero_f32 $src))>;1711def : Pat<(i32 (fp_to_sint f32:$src)), (CVTWSSXr RD_RZ, $src)>;1712def : Pat<(i32 (fp_to_sint f64:$src)), (CVTWDSXr RD_RZ, $src)>;1713def : Pat<(i32 (fp_to_sint f128:$src)), (CVTWDSXr RD_RZ, (CVTDQr $src))>;1714 1715// Cast to i641716def : Pat<(sext_inreg i64:$src, i32), (i2l (ADDSWSXrm (l2i $src), 0))>;1717def : Pat<(i64 (sext i32:$src)), (i2l (ADDSWSXrm $src, 0))>;1718def : Pat<(i64 (zext i32:$src)), (i2l (ADDSWZXrm $src, 0))>;1719def : Pat<(i64 (anyext i32:$sy)), (i2l $sy)>;1720def : Pat<(i64 (fp_to_sint f32:$src)), (CVTLDr RD_RZ, (CVTDSr $src))>;1721def : Pat<(i64 (fp_to_sint f64:$src)), (CVTLDr RD_RZ, $src)>;1722def : Pat<(i64 (fp_to_sint f128:$src)), (CVTLDr RD_RZ, (CVTDQr $src))>;1723 1724// Cast to f321725def : Pat<(f32 (sint_to_fp i64:$src)), (CVTSDr (CVTDLr i64:$src))>;1726 1727// Cast to f1281728def : Pat<(f128 (sint_to_fp i32:$src)), (CVTQDr (CVTDWr $src))>;1729def : Pat<(f128 (sint_to_fp i64:$src)), (CVTQDr (CVTDLr $src))>;1730 1731 1732// extload, sextload and zextload stuff1733multiclass EXT64m<SDPatternOperator from,1734                  RM torri,1735                  RM torii,1736                  RM tozri,1737                  RM tozii> {1738  def : Pat<(i64 (from ADDRrri:$addr)),1739            (i2l (torri MEMrri:$addr))>;1740  def : Pat<(i64 (from ADDRrii:$addr)),1741            (i2l (torii MEMrii:$addr))>;1742  def : Pat<(i64 (from ADDRzri:$addr)),1743            (i2l (tozri MEMzri:$addr))>;1744  def : Pat<(i64 (from ADDRzii:$addr)),1745            (i2l (tozii MEMzii:$addr))>;1746}1747defm : EXT64m<sextloadi8, LD1BSXrri, LD1BSXrii, LD1BSXzri, LD1BSXzii>;1748defm : EXT64m<zextloadi8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>;1749defm : EXT64m<extloadi8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>;1750defm : EXT64m<sextloadi16, LD2BSXrri, LD2BSXrii, LD2BSXzri, LD2BSXzii>;1751defm : EXT64m<zextloadi16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>;1752defm : EXT64m<extloadi16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>;1753defm : EXT64m<sextloadi32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>;1754defm : EXT64m<zextloadi32, LDLZXrri, LDLZXrii, LDLZXzri, LDLZXzii>;1755defm : EXT64m<extloadi32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>;1756 1757// anyextload1758multiclass EXT32m<SDPatternOperator from,1759                  RM torri,1760                  RM torii,1761                  RM tozri,1762                  RM tozii> {1763  def : Pat<(from ADDRrri:$addr), (torri MEMrri:$addr)>;1764  def : Pat<(from ADDRrii:$addr), (torii MEMrii:$addr)>;1765  def : Pat<(from ADDRzri:$addr), (tozri MEMzri:$addr)>;1766  def : Pat<(from ADDRzii:$addr), (tozii MEMzii:$addr)>;1767}1768defm : EXT32m<extloadi8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>;1769defm : EXT32m<extloadi16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>;1770 1771// truncstore1772multiclass TRUNC64m<SDPatternOperator from,1773                    RM torri,1774                    RM torii,1775                    RM tozri,1776                    RM tozii> {1777  def : Pat<(from i64:$src, ADDRrri:$addr),1778            (torri MEMrri:$addr, (l2i $src))>;1779  def : Pat<(from i64:$src, ADDRrii:$addr),1780            (torii MEMrii:$addr, (l2i $src))>;1781  def : Pat<(from i64:$src, ADDRzri:$addr),1782            (tozri MEMzri:$addr, (l2i $src))>;1783  def : Pat<(from i64:$src, ADDRzii:$addr),1784            (tozii MEMzii:$addr, (l2i $src))>;1785}1786defm : TRUNC64m<truncstorei8, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>;1787defm : TRUNC64m<truncstorei16, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>;1788defm : TRUNC64m<truncstorei32, STLrri, STLrii, STLzri, ST1Bzii>;1789 1790// Atomic loads (FIXME: replace iAny with the correct integer VT:)1791multiclass ATMLDm<SDPatternOperator from,1792                  RM torri, RM torii,1793                  RM tozri, RM tozii> {1794  def : Pat<(iAny (from ADDRrri:$addr)), (torri MEMrri:$addr)>;1795  def : Pat<(iAny (from ADDRrii:$addr)), (torii MEMrii:$addr)>;1796  def : Pat<(iAny (from ADDRzri:$addr)), (tozri MEMzri:$addr)>;1797  def : Pat<(iAny (from ADDRzii:$addr)), (tozii MEMzii:$addr)>;1798}1799defm : ATMLDm<atomic_load_aext_8, LD1BZXrri, LD1BZXrii, LD1BZXzri, LD1BZXzii>;1800defm : ATMLDm<atomic_load_aext_16, LD2BZXrri, LD2BZXrii, LD2BZXzri, LD2BZXzii>;1801defm : ATMLDm<atomic_load_nonext_32, LDLZXrri, LDLZXrii, LDLZXzri, LDLZXzii>;1802defm : ATMLDm<atomic_load_nonext_64, LDrri, LDrii, LDzri, LDzii>;1803 1804// Optimized atomic loads with sext1805multiclass SXATMLDm<SDPatternOperator from, ValueType TY,1806                    RM torri, RM torii,1807                    RM tozri, RM tozii> {1808  def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrri:$addr))), TY)),1809            (i2l (torri MEMrri:$addr))>;1810  def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRrii:$addr))), TY)),1811            (i2l (torii MEMrii:$addr))>;1812  def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRzri:$addr))), TY)),1813            (i2l (tozri MEMzri:$addr))>;1814  def : Pat<(i64 (sext_inreg (i64 (anyext (from ADDRzii:$addr))), TY)),1815            (i2l (tozii MEMzii:$addr))>;1816}1817multiclass SXATMLD32m<SDPatternOperator from,1818                      RM torri, RM torii,1819                      RM tozri, RM tozii> {1820  def : Pat<(i64 (sext (from ADDRrri:$addr))),1821            (i2l (torri MEMrri:$addr))>;1822  def : Pat<(i64 (sext (from ADDRrii:$addr))),1823            (i2l (torii MEMrii:$addr))>;1824  def : Pat<(i64 (sext (from ADDRzri:$addr))),1825            (i2l (tozri MEMzri:$addr))>;1826  def : Pat<(i64 (sext (from ADDRzii:$addr))),1827            (i2l (tozii MEMzii:$addr))>;1828}1829defm : SXATMLDm<atomic_load_aext_8, i8, LD1BSXrri, LD1BSXrii, LD1BSXzri, LD1BSXzii>;1830defm : SXATMLDm<atomic_load_aext_16, i16, LD2BSXrri, LD2BSXrii, LD2BSXzri,1831                LD2BSXzii>;1832defm : SXATMLD32m<atomic_load_nonext_32, LDLSXrri, LDLSXrii, LDLSXzri, LDLSXzii>;1833 1834// Optimized atomic loads with zext1835multiclass ZXATMLDm<SDPatternOperator from, int VAL,1836                    RM torri, RM torii,1837                    RM tozri, RM tozii> {1838  def : Pat<(i64 (and (anyext (from ADDRrri:$addr)), VAL)),1839            (i2l (torri MEMrri:$addr))>;1840  def : Pat<(i64 (and (anyext (from ADDRrii:$addr)), VAL)),1841            (i2l (torii MEMrii:$addr))>;1842  def : Pat<(i64 (and (anyext (from ADDRzri:$addr)), VAL)),1843            (i2l (tozri MEMzri:$addr))>;1844  def : Pat<(i64 (and (anyext (from ADDRzii:$addr)), VAL)),1845            (i2l (tozii MEMzii:$addr))>;1846}1847multiclass ZXATMLD32m<SDPatternOperator from,1848                      RM torri, RM torii,1849                      RM tozri, RM tozii> {1850  def : Pat<(i64 (zext (from ADDRrri:$addr))),1851            (i2l (torri MEMrri:$addr))>;1852  def : Pat<(i64 (zext (from ADDRrii:$addr))),1853            (i2l (torii MEMrii:$addr))>;1854  def : Pat<(i64 (zext (from ADDRzri:$addr))),1855            (i2l (tozri MEMzri:$addr))>;1856  def : Pat<(i64 (zext (from ADDRzii:$addr))),1857            (i2l (tozii MEMzii:$addr))>;1858}1859defm : ZXATMLDm<atomic_load_aext_8, 0xFF, LD1BZXrri, LD1BZXrii, LD1BZXzri,1860                LD1BZXzii>;1861defm : ZXATMLDm<atomic_load_aext_16, 0xFFFF, LD2BZXrri, LD2BZXrii, LD2BZXzri,1862                LD2BZXzii>;1863defm : ZXATMLD32m<atomic_load_nonext_32, LDLZXrri, LDLZXrii, LDLZXzri, LDLZXzii>;1864 1865// Atomic stores1866multiclass ATMSTm<SDPatternOperator from, ValueType ty,1867                  RM torri, RM torii,1868                  RM tozri, RM tozii> {1869  def : Pat<(from ty:$src, ADDRrri:$addr), (torri MEMrri:$addr, $src)>;1870  def : Pat<(from ty:$src, ADDRrii:$addr), (torii MEMrii:$addr, $src)>;1871  def : Pat<(from ty:$src, ADDRzri:$addr), (tozri MEMzri:$addr, $src)>;1872  def : Pat<(from ty:$src, ADDRzii:$addr), (tozii MEMzii:$addr, $src)>;1873}1874defm : ATMSTm<atomic_store_8, i32, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>;1875defm : ATMSTm<atomic_store_16, i32, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>;1876defm : ATMSTm<atomic_store_32, i32, STLrri, STLrii, STLzri, STLzii>;1877defm : ATMSTm<atomic_store_64, i64, STrri, STrii, STzri, STzii>;1878 1879// Optimized atomic stores with truncate1880multiclass TRATMSTm<SDPatternOperator from,1881                  RM torri,1882                  RM torii,1883                  RM tozri,1884                  RM tozii> {1885  def : Pat<(from (i32 (trunc i64:$src)), ADDRrri:$addr),1886            (torri MEMrri:$addr, (EXTRACT_SUBREG $src, sub_i32))>;1887  def : Pat<(from (i32 (trunc i64:$src)), ADDRrii:$addr),1888            (torii MEMrii:$addr, (EXTRACT_SUBREG $src, sub_i32))>;1889  def : Pat<(from (i32 (trunc i64:$src)), ADDRzri:$addr),1890            (tozri MEMzri:$addr, (EXTRACT_SUBREG $src, sub_i32))>;1891  def : Pat<(from (i32 (trunc i64:$src)), ADDRzii:$addr),1892            (tozii MEMzii:$addr, (EXTRACT_SUBREG $src, sub_i32))>;1893}1894defm : TRATMSTm<atomic_store_8, ST1Brri, ST1Brii, ST1Bzri, ST1Bzii>;1895defm : TRATMSTm<atomic_store_16, ST2Brri, ST2Brii, ST2Bzri, ST2Bzii>;1896defm : TRATMSTm<atomic_store_32, STLrri, STLrii, STLzri, STLzii>;1897 1898// Atomic swaps1899def : Pat<(i32 (ts1am i64:$src, i32:$flag, i32:$new)),1900          (TS1AMWrir $src, 0, $flag, $new)>;1901def : Pat<(i32 (atomic_swap_i32 ADDRri:$src, i32:$new)),1902          (TS1AMWrii MEMriRRM:$src, 15, $new)>;1903def : Pat<(i64 (atomic_swap_i64 ADDRri:$src, i64:$new)),1904          (TS1AMLrir MEMriRRM:$src, (LEAzii 0, 0, 255), i64:$new)>;1905 1906//===----------------------------------------------------------------------===//1907// SJLJ Exception handling patterns1908//===----------------------------------------------------------------------===//1909 1910let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,1911    usesCustomInserter = 1 in {1912  let isTerminator = 1 in1913  def EH_SjLj_LongJmp : Pseudo<(outs), (ins I64:$buf),1914                               "# EH_SJLJ_LONGJMP",1915                               [(VEeh_sjlj_longjmp I64:$buf)]>;1916 1917  def EH_SjLj_SetJmp  : Pseudo<(outs I32:$dst), (ins I64:$buf),1918                               "# EH_SJLJ_SETJMP",1919                               [(set I32:$dst, (VEeh_sjlj_setjmp I64:$buf))]>;1920 1921  def EH_SjLj_Setup_Dispatch : Pseudo<(outs), (ins), "# EH_SJLJ_SETUP_DISPATCH",1922                                      [(VEeh_sjlj_setup_dispatch)]>;1923}1924 1925let isTerminator = 1, isBranch = 1, isCodeGenOnly = 1 in1926  def EH_SjLj_Setup : Pseudo<(outs), (ins brtarget32:$dst),1927                             "# EH_SJlJ_SETUP $dst">;1928 1929//===----------------------------------------------------------------------===//1930// Branch related patterns1931//===----------------------------------------------------------------------===//1932 1933// Branches1934def : Pat<(br bb:$addr), (BRCFLa bb:$addr)>;1935 1936// brcc1937// integer brcc1938multiclass BRCCIm<ValueType ty, CF BrOpNode1,1939                 CF BrOpNode2,1940                 RR CmpOpNode1,1941                 RR CmpOpNode2> {1942  def : Pat<(brcc CCSIOp:$cond, ty:$l, simm7:$r, bb:$addr),1943            (BrOpNode2 (icond2ccSwap $cond), (LO7 $r), $l, bb:$addr)>;1944  def : Pat<(brcc CCSIOp:$cond, ty:$l, ty:$r, bb:$addr),1945            (BrOpNode1 (icond2cc $cond), $l, $r, bb:$addr)>;1946  def : Pat<(brcc CCUIOp:$cond, ty:$l, simm7:$r, bb:$addr),1947            (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode2 (LO7 $r), $l),1948                       bb:$addr)>;1949  def : Pat<(brcc CCUIOp:$cond, ty:$l, ty:$r, bb:$addr),1950            (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode1 $r, $l), bb:$addr)>;1951}1952defm : BRCCIm<i32, BRCFWrr, BRCFWir, CMPUWrr, CMPUWir>;1953defm : BRCCIm<i64, BRCFLrr, BRCFLir, CMPULrr, CMPULir>;1954 1955// floating point brcc1956multiclass BRCCFm<ValueType ty, CF BrOpNode1, CF BrOpNode2> {1957  def : Pat<(brcc cond:$cond, ty:$l, simm7fp:$r, bb:$addr),1958            (BrOpNode2 (fcond2ccSwap $cond), (LO7FP $r), $l, bb:$addr)>;1959  def : Pat<(brcc cond:$cond, ty:$l, ty:$r, bb:$addr),1960            (BrOpNode1 (fcond2cc $cond), $l, $r, bb:$addr)>;1961}1962defm : BRCCFm<f32, BRCFSrr, BRCFSir>;1963defm : BRCCFm<f64, BRCFDrr, BRCFDir>;1964def : Pat<(brcc cond:$cond, f128:$l, f128:$r, bb:$addr),1965          (BRCFDir (fcond2cc $cond), 0, (FCMPQrr $r, $l), bb:$addr)>;1966 1967//===----------------------------------------------------------------------===//1968// Pseudo Instructions1969//===----------------------------------------------------------------------===//1970 1971// GETGOT for PIC1972let Defs = [SX15 /* %got */, SX16 /* %plt */], hasSideEffects = 0 in {1973  def GETGOT : Pseudo<(outs getGOT:$getpcseq), (ins), "$getpcseq">;1974}1975 1976// GETFUNPLT for PIC1977let hasSideEffects = 0 in1978def GETFUNPLT : Pseudo<(outs I64:$dst), (ins i64imm:$addr),1979                       "$dst, $addr",1980                       [(set iPTR:$dst, (GetFunPLT tglobaladdr:$addr))] >;1981 1982def : Pat<(GetFunPLT tglobaladdr:$dst),1983          (GETFUNPLT tglobaladdr:$dst)>;1984def : Pat<(GetFunPLT texternalsym:$dst),1985          (GETFUNPLT texternalsym:$dst)>;1986 1987// GETTLSADDR for TLS1988let Defs = [SX0, SX10, SX12], hasSideEffects = 0 in1989def GETTLSADDR : Pseudo<(outs), (ins i64imm:$addr),1990                        "# GETTLSADDR $addr",1991                        [(GetTLSAddr tglobaltlsaddr:$addr)] >;1992 1993def : Pat<(GetTLSAddr tglobaltlsaddr:$dst),1994          (GETTLSADDR tglobaltlsaddr:$dst)>;1995 1996let Defs = [SX11], Uses = [SX11], hasSideEffects = 0 in {1997def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt, i64imm:$amt2),1998                              "# ADJCALLSTACKDOWN $amt, $amt2",1999                              [(callseq_start timm:$amt, timm:$amt2)]>;2000def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),2001                            "# ADJCALLSTACKUP $amt1",2002                            [(callseq_end timm:$amt1, timm:$amt2)]>;2003}2004 2005let Defs = [SX8], Uses = [SX8, SX11], hasSideEffects = 0 in2006def EXTEND_STACK : Pseudo<(outs), (ins),2007                          "# EXTEND STACK",2008                          []>;2009let  hasSideEffects = 0 in2010def EXTEND_STACK_GUARD : Pseudo<(outs), (ins),2011                                "# EXTEND STACK GUARD",2012                                []>;2013 2014// Dynamic stack allocation yields a __llvm_grow_stack for VE targets.2015// These calls are needed to probe the stack when allocating more over2016// %s8 (%sl - stack limit).2017 2018let Uses = [SX11], hasSideEffects = 1 in2019def GETSTACKTOP : Pseudo<(outs I64:$dst), (ins),2020                         "# GET STACK TOP",2021                         [(set iPTR:$dst, (GetStackTop))]>;2022 2023//===----------------------------------------------------------------------===//2024// Other patterns2025//===----------------------------------------------------------------------===//2026 2027// SETCC pattern matches2028//2029//   CMP  %tmp, lhs, rhs     ; compare lhs and rhs2030//   or   %res, 0, (0)1      ; initialize by 02031//   CMOV %res, (63)0, %tmp  ; set 1 if %tmp is true2032 2033class setccrr<Instruction INSN> :2034    OutPatFrag<(ops node:$cond, node:$comp),2035               (EXTRACT_SUBREG2036                   (INSN $cond, $comp,2037                         !add(63, 64), // means (63)0 == 12038                         (ORim 0, 0)), sub_i32)>;2039 2040def : Pat<(i32 (setcc i32:$l, i32:$r, CCSIOp:$cond)),2041          (setccrr<CMOVWrm> (icond2cc $cond), (CMPSWSXrr $l, $r))>;2042def : Pat<(i32 (setcc i32:$l, i32:$r, CCUIOp:$cond)),2043          (setccrr<CMOVWrm> (icond2cc $cond), (CMPUWrr $l, $r))>;2044def : Pat<(i32 (setcc i64:$l, i64:$r, CCSIOp:$cond)),2045          (setccrr<CMOVLrm> (icond2cc $cond), (CMPSLrr $l, $r))>;2046def : Pat<(i32 (setcc i64:$l, i64:$r, CCUIOp:$cond)),2047          (setccrr<CMOVLrm> (icond2cc $cond), (CMPULrr $l, $r))>;2048def : Pat<(i32 (setcc f32:$l, f32:$r, cond:$cond)),2049          (setccrr<CMOVSrm> (fcond2cc $cond), (FCMPSrr $l, $r))>;2050def : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)),2051          (setccrr<CMOVDrm> (fcond2cc $cond), (FCMPDrr $l, $r))>;2052def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)),2053          (setccrr<CMOVDrm> (fcond2cc $cond), (FCMPQrr $l, $r))>;2054 2055// Generic CMOV pattern matches2056//   CMOV accepts i64 $t, $f, and result.  So, we extend it to support2057//   i32/f32/f64/f128 $t, $f, and result.2058 2059// CMOV for i322060multiclass CMOVI32m<ValueType TY, string Insn> {2061  def : Pat<(i32 (cmov TY:$cmp, i32:$t, i32:$f, (i32 CCOp:$cond))),2062            (EXTRACT_SUBREG2063                (!cast<Instruction>(Insn#"rr") (CCOP $cond), $cmp,2064                           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32),2065                           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)),2066                sub_i32)>;2067  def : Pat<(i32 (cmov TY:$cmp, (i32 mimm:$t), i32:$f, (i32 CCOp:$cond))),2068            (EXTRACT_SUBREG2069                (!cast<Instruction>(Insn#"rm") (CCOP $cond), $cmp,2070                           (MIMM $t),2071                           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)),2072                sub_i32)>;2073}2074defm : CMOVI32m<i64, "CMOVL">;2075defm : CMOVI32m<i32, "CMOVW">;2076defm : CMOVI32m<f64, "CMOVD">;2077defm : CMOVI32m<f32, "CMOVS">;2078 2079// CMOV for f322080multiclass CMOVF32m<ValueType TY, string Insn> {2081  def : Pat<(f32 (cmov TY:$cmp, f32:$t, f32:$f, (i32 CCOp:$cond))),2082            (EXTRACT_SUBREG2083                (!cast<Instruction>(Insn#"rr")2084                    (CCOP $cond), $cmp,2085                    (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_f32),2086                    (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_f32)),2087                sub_f32)>;2088  def : Pat<(f32 (cmov TY:$cmp, (f32 mimmfp:$t), f32:$f, (i32 CCOp:$cond))),2089            (EXTRACT_SUBREG2090                (!cast<Instruction>(Insn#"rm")2091                    (CCOP $cond), $cmp, (MIMMFP $t),2092                    (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_f32)),2093                sub_f32)>;2094}2095defm : CMOVF32m<i64, "CMOVL">;2096defm : CMOVF32m<i32, "CMOVW">;2097defm : CMOVF32m<f64, "CMOVD">;2098defm : CMOVF32m<f32, "CMOVS">;2099 2100// CMOV for f642101multiclass CMOVF64m<ValueType TY, string Insn> {2102  def : Pat<(f64 (cmov TY:$cmp, f64:$t, f64:$f, (i32 CCOp:$cond))),2103            (!cast<Instruction>(Insn#"rr") (CCOP $cond), $cmp, $t, $f)>;2104  def : Pat<(f64 (cmov TY:$cmp, (f64 mimmfp:$t), f64:$f, (i32 CCOp:$cond))),2105            (!cast<Instruction>(Insn#"rm") (CCOP $cond), $cmp, (MIMMFP $t),2106                                           $f)>;2107}2108defm : CMOVF64m<i64, "CMOVL">;2109defm : CMOVF64m<i32, "CMOVW">;2110defm : CMOVF64m<f64, "CMOVD">;2111defm : CMOVF64m<f32, "CMOVS">;2112 2113// CMOV for f1282114multiclass CMOVF128m<ValueType TY, string Insn> {2115  def : Pat<(f128 (cmov TY:$cmp, f128:$t, f128:$f, (i32 CCOp:$cond))),2116            (INSERT_SUBREG2117              (INSERT_SUBREG (f128 (IMPLICIT_DEF)),2118                (!cast<Instruction>(Insn#"rr") (CCOP $cond), $cmp,2119                  (EXTRACT_SUBREG $t, sub_odd),2120                  (EXTRACT_SUBREG $f, sub_odd)), sub_odd),2121              (!cast<Instruction>(Insn#"rr") (CCOP $cond), $cmp,2122                (EXTRACT_SUBREG $t, sub_even),2123                (EXTRACT_SUBREG $f, sub_even)), sub_even)>;2124}2125defm : CMOVF128m<i64, "CMOVL">;2126defm : CMOVF128m<i32, "CMOVW">;2127defm : CMOVF128m<f64, "CMOVD">;2128defm : CMOVF128m<f32, "CMOVS">;2129 2130// bitconvert2131def : Pat<(f64 (bitconvert i64:$src)), (COPY_TO_REGCLASS $src, I64)>;2132def : Pat<(i64 (bitconvert f64:$src)), (COPY_TO_REGCLASS $src, I64)>;2133 2134def : Pat<(i32 (bitconvert f32:$op)), (l2i (SRALri (f2l $op), 32))>;2135def : Pat<(f32 (bitconvert i32:$op)), (l2f (SLLri (i2l $op), 32))>;2136 2137//===----------------------------------------------------------------------===//2138// Vector Instruction Pattern Stuff2139//===----------------------------------------------------------------------===//2140 2141// Custom intermediate ISDs.2142class IsVLVT<int OpIdx> : SDTCisVT<OpIdx,i32>;2143def vec_broadcast       : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2,2144                                 [SDTCisVec<0>, IsVLVT<2>]>>;2145 2146///// Packed mode Support /////2147// unpack the lo part of this vector2148def vec_unpack_lo   : SDNode<"VEISD::VEC_UNPACK_LO", SDTypeProfile<1, 2,2149                             [SDTCisVec<0>, SDTCisVec<1>, IsVLVT<2>]>>;2150// unpack the hipart of this vector2151def vec_unpack_hi   : SDNode<"VEISD::VEC_UNPACK_HI", SDTypeProfile<1, 2,2152                             [SDTCisVec<0>, SDTCisVec<1>, IsVLVT<2>]>>;2153// re-pack v256i32, v256f32 back into tone v512.322154def vec_pack        : SDNode<"VEISD::VEC_PACK", SDTypeProfile<1, 3,2155                             [SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>,2156                              SDTCisSameNumEltsAs<1,2>, IsVLVT<3>]>>;2157 2158// replicate lower 32bit to upper 32bit (f32 scalar replication).2159def repl_f32            : SDNode<"VEISD::REPL_F32",2160                            SDTypeProfile<1, 1,2161                              [SDTCisInt<0>, SDTCisFP<1>]>>;2162// replicate upper 32bit to lower 32 bit (i32 scalar replication).2163def repl_i32            : SDNode<"VEISD::REPL_I32",2164                            SDTypeProfile<1, 1,2165                              [SDTCisInt<0>, SDTCisInt<1>]>>;2166 2167 2168// Whether this is an all-true mask (assuming undef-bits above VL are all-true).2169def true_mask           : PatLeaf<2170                            (vec_broadcast (i32 nonzero), (i32 srcvalue))>;2171// Match any broadcast (ignoring VL).2172def any_broadcast       : PatFrag<(ops node:$sx),2173                                  (vec_broadcast node:$sx, (i32 srcvalue))>;2174 2175// Vector instructions.2176include "VEInstrVec.td"2177 2178// The vevlintrin2179include "VEInstrIntrinsicVL.td"2180 2181// Patterns and intermediate SD nodes (VEC_*).2182include "VEInstrPatternsVec.td"2183 2184// Patterns and intermediate SD nodes (VVP_*).2185include "VVPInstrPatternsVec.td"2186