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1//===----------------------------------------------------------------------===//2// Vector Instructions3//===----------------------------------------------------------------------===//4 5// Pseudo instructions for VM/VM512 spill/restore6//7// These pseudo instructions are used for only spill/restore since8// InlineSpiller assumes storeRegToStackSlot/loadRegFromStackSlot9// functions emit only single instruction. Those functions emit a10// single store/load instruction or one of these pseudo store/load11// instructions.12//13// Specifies hasSideEffects = 0 to disable UnmodeledSideEffects.14 15let mayLoad = 1, hasSideEffects = 0 in {16def LDVMrii : Pseudo<17 (outs VM:$vmx), (ins MEMrii:$addr),18 "# pseudo ldvm $vmx, $addr", []>;19def LDVM512rii : Pseudo<20 (outs VM512:$vmx), (ins MEMrii:$addr),21 "# pseudo ldvm512 $vmx, $addr", []>;22}23let mayStore = 1, hasSideEffects = 0 in {24def STVMrii : Pseudo<25 (outs), (ins MEMrii:$addr, VM:$vmx),26 "# pseudo stvm $addr, $vmx", []>;27def STVM512rii : Pseudo<28 (outs), (ins MEMrii:$addr, VM512:$vmx),29 "# pseudo stvm512 $addr, $vmx", []>;30}31 32//===----------------------------------------------------------------------===//33// Pseudo instructions for VM512 modifications34//===----------------------------------------------------------------------===//35 36// LVM/SVM instructions using VM51237let hasSideEffects = 0, isCodeGenOnly = 1 in {38 let Constraints = "$vx = $vd" in {39 def LVMyir_y : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz, VM512:$vd),40 "# pseudo LVM $vx, $sy, $sz, $vd">;41 def LVMyim_y : Pseudo<(outs VM512:$vx),42 (ins uimm3:$sy, mimm:$sz, VM512:$vd),43 "# pseudo LVM $vx, $sy, $sz, $vd">;44 }45 def LVMyir : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz),46 "# pseudo LVM $vx, $sy, $sz">;47 def LVMyim : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, mimm:$sz),48 "# pseudo LVM $vx, $sy, $sz">;49 def SVMyi : Pseudo<(outs I64:$sx), (ins VM512:$vz, uimm3:$sy),50 "# pseudo SVM $sx, $vz, $sy">;51}52 53// VFMK/VFMKW/VFMKS instructions using VM51254let hasSideEffects = 0, isCodeGenOnly = 1 in {55 def VFMKyal : Pseudo<(outs VM512:$vmx), (ins I32:$vl),56 "# pseudo-vfmk.at $vmx">;57 def VFMKynal : Pseudo<(outs VM512:$vmx), (ins I32:$vl),58 "# pseudo-vfmk.af $vmx">;59 def VFMKWyvl : Pseudo<(outs VM512:$vmx),60 (ins CCOp:$cf, V64:$vz, I32:$vl),61 "# pseudo-vfmk.w.$cf $vmx, $vz">;62 def VFMKWyvyl : Pseudo<(outs VM512:$vmx),63 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),64 "# pseudo-vfmk.w.$cf $vmx, $vz, $vm">;65 def VFMKSyvl : Pseudo<(outs VM512:$vmx),66 (ins CCOp:$cf, V64:$vz, I32:$vl),67 "# pseudo-vfmk.s.$cf $vmx, $vz">;68 def VFMKSyvyl : Pseudo<(outs VM512:$vmx),69 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),70 "# pseudo-vfmk.s.$cf $vmx, $vz, $vm">;71}72 73// ANDM/ORM/XORM/EQVM/NNDM/NEGM instructions using VM51274let hasSideEffects = 0, isCodeGenOnly = 1 in {75 def ANDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),76 "# andm $vmx, $vmy, $vmz">;77 def ORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),78 "# orm $vmx, $vmy, $vmz">;79 def XORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),80 "# xorm $vmx, $vmy, $vmz">;81 def EQVMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),82 "# eqvm $vmx, $vmy, $vmz">;83 def NNDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz),84 "# nndm $vmx, $vmy, $vmz">;85 def NEGMy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy),86 "# negm $vmx, $vmy">;87}88 89//===----------------------------------------------------------------------===//90// Instructions91//92// Define all vector instructions defined in SX-Aurora TSUBASA Architecture93// Guide here. As those mnemonics, we use mnemonics defined in Vector Engine94// Assembly Language Reference Manual.95//96// Some instructions can update existing data by following instructions97// sequence.98//99// lea %s0, 256100// lea %s1, 128101// lvl %s0102// vbrd %v0, 2 # v0 = { 2, 2, 2, ..., 2, 2, 2 }103// lvl %s1104// vbrd %v0, 3 # v0 = { 3, 3, 3, ..., 3, 2, 2, 2, ..., 2, 2, 2 }105//106// In order to represent above with a virtual register, we defines instructions107// with an additional base register and `_v` suffiex in mnemonic.108//109// lea t0, 256110// lea t1, 128111// lea t0112// vbrd tv0, 2113// lvl t1114// vbrd_v tv1, 2, tv0115//116// We also have some instructions uses VL register with an pseudo VL value117// with following suffixes in mnemonic.118//119// l: have an additional I32 register to represent the VL value.120// L: have an additional VL register to represent the VL value.121//===----------------------------------------------------------------------===//122 123//-----------------------------------------------------------------------------124// Section 8.9 - Vector Load/Store and Move Instructions125//-----------------------------------------------------------------------------126 127// Multiclass for VLD instructions128let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in129multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {130 def "" : RVM<opc, (outs RC:$vx), dag_in,131 !strconcat(opcStr, " $vx, $sy, $sz")>;132 let Constraints = "$vx = $base", isCodeGenOnly = 1 in133 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),134 !strconcat(opcStr, " $vx, $sy, $sz")>;135}136multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {137 defm "" : VLDbm<opcStr, opc, RC, dag_in>;138 let isCodeGenOnly = 1, VE_VLInUse = 1 in {139 defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl))>;140 defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl))>;141 }142}143let VE_VLIndex = 3 in144multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {145 defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;146 let cy = 0 in147 defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;148 let cz = 0 in149 defm rz : VLDlm<opcStr, opc, RC, (ins I64:$sy, zero:$sz)>;150 let cy = 0, cz = 0 in151 defm iz : VLDlm<opcStr, opc, RC, (ins simm7:$sy, zero:$sz)>;152}153multiclass VLDm<string opcStr, bits<8>opc, RegisterClass RC> {154 let vc = 1 in defm "" : VLDtgm<opcStr, opc, RC>;155 let vc = 0 in defm NC : VLDtgm<opcStr#".nc", opc, RC>;156}157 158// Section 8.9.1 - VLD (Vector Load)159defm VLD : VLDm<"vld", 0x81, V64>;160 161// Section 8.9.2 - VLDU (Vector Load Upper)162defm VLDU : VLDm<"vldu", 0x82, V64>;163 164// Section 8.9.3 - VLDL (Vector Load Lower)165defm VLDLSX : VLDm<"vldl.sx", 0x83, V64>;166let cx = 1 in defm VLDLZX : VLDm<"vldl.zx", 0x83, V64>;167 168// Section 8.9.4 - VLD2D (Vector Load 2D)169defm VLD2D : VLDm<"vld2d", 0xc1, V64>;170 171// Section 8.9.5 - VLDU2D (Vector Load Upper 2D)172defm VLDU2D : VLDm<"vldu2d", 0xc2, V64>;173 174// Section 8.9.6 - VLDL2D (Vector Load Lower 2D)175defm VLDL2DSX : VLDm<"vldl2d.sx", 0xc3, V64>;176let cx = 1 in defm VLDL2DZX : VLDm<"vldl2d.zx", 0xc3, V64>;177 178// Multiclass for VST instructions179let mayStore = 1, hasSideEffects = 0, Uses = [VL] in180multiclass VSTbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {181 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;182 let isCodeGenOnly = 1, VE_VLInUse = 1 in {183 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),184 !strconcat(opcStr, argStr)>;185 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),186 !strconcat(opcStr, argStr)>;187 }188}189multiclass VSTmm<string opcStr, bits<8>opc, dag dag_in> {190 defm "" : VSTbm<opcStr, " $vx, $sy, $sz", opc, dag_in>;191 let m = ?, VE_VLWithMask = 1 in192 defm m : VSTbm<opcStr, " $vx, $sy, $sz, $m", opc, !con(dag_in, (ins VM:$m))>;193}194let VE_VLIndex = 3 in195multiclass VSTtgm<string opcStr, bits<8>opc, RegisterClass RC> {196 defm rrv : VSTmm<opcStr, opc, (ins I64:$sy, I64:$sz, RC:$vx)>;197 let cy = 0 in198 defm irv : VSTmm<opcStr, opc, (ins simm7:$sy, I64:$sz, RC:$vx)>;199 let cz = 0 in200 defm rzv : VSTmm<opcStr, opc, (ins I64:$sy, zero:$sz, RC:$vx)>;201 let cy = 0, cz = 0 in202 defm izv : VSTmm<opcStr, opc, (ins simm7:$sy, zero:$sz, RC:$vx)>;203}204multiclass VSTm<string opcStr, bits<8>opc, RegisterClass RC> {205 let vc = 1, cx = 0 in defm "" : VSTtgm<opcStr, opc, RC>;206 let vc = 0, cx = 0 in defm NC : VSTtgm<opcStr#".nc", opc, RC>;207 let vc = 1, cx = 1 in defm OT : VSTtgm<opcStr#".ot", opc, RC>;208 let vc = 0, cx = 1 in defm NCOT : VSTtgm<opcStr#".nc.ot", opc, RC>;209}210 211// Section 8.9.7 - VST (Vector Store)212defm VST : VSTm<"vst", 0x91, V64>;213 214// Section 8.9.8 - VST (Vector Store Upper)215defm VSTU : VSTm<"vstu", 0x92, V64>;216 217// Section 8.9.9 - VSTL (Vector Store Lower)218defm VSTL : VSTm<"vstl", 0x93, V64>;219 220// Section 8.9.10 - VST2D (Vector Store 2D)221defm VST2D : VSTm<"vst2d", 0xd1, V64>;222 223// Section 8.9.11 - VSTU2D (Vector Store Upper 2D)224defm VSTU2D : VSTm<"vstu2d", 0xd2, V64>;225 226// Section 8.9.12 - VSTL2D (Vector Store Lower 2D)227defm VSTL2D : VSTm<"vstl2d", 0xd3, V64>;228 229// Multiclass for VGT instructions230let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in231multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,232 dag dag_in> {233 def "" : RVM<opc, (outs RC:$vx), dag_in,234 !strconcat(opcStr, " $vx, ", argStr)>;235 let Constraints = "$vx = $base", isCodeGenOnly = 1 in236 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),237 !strconcat(opcStr, " $vx, ", argStr)>;238}239multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,240 dag dag_in> {241 defm "" : VGTbm<opcStr, argStr, opc, RC, dag_in>;242 let isCodeGenOnly = 1, VE_VLInUse = 1 in {243 defm l : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl))>;244 defm L : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl))>;245 }246}247multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,248 dag dag_in> {249 defm "" : VGTlm<opcStr, argStr, opc, RC, dag_in>;250 let m = ?, VE_VLWithMask = 1 in251 defm m : VGTlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins VM:$m))>;252}253let VE_VLIndex = 4 in254multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,255 dag dag_in> {256 defm rr : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,257 !con(dag_in, (ins I64:$sy, I64:$sz))>;258 let cy = 0 in259 defm ir : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,260 !con(dag_in, (ins simm7:$sy, I64:$sz))>;261 let cz = 0 in262 defm rz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,263 !con(dag_in, (ins I64:$sy, zero:$sz))>;264 let cy = 0, cz = 0 in265 defm iz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,266 !con(dag_in, (ins simm7:$sy, zero:$sz))>;267}268multiclass VGTtgm<string opcStr, bits<8>opc, RegisterClass RC> {269 let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;270 let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;271}272multiclass VGTm<string opcStr, bits<8>opc, RegisterClass RC> {273 let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>;274 let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>;275}276 277// Section 8.9.13 - VGT (Vector Gather)278defm VGT : VGTm<"vgt", 0xa1, V64>;279 280// Section 8.9.14 - VGTU (Vector Gather Upper)281defm VGTU : VGTm<"vgtu", 0xa2, V64>;282 283// Section 8.9.15 - VGTL (Vector Gather Lower)284defm VGTLSX : VGTm<"vgtl.sx", 0xa3, V64>;285let cx = 1 in defm VGTLZX : VGTm<"vgtl.zx", 0xa3, V64>;286def : MnemonicAlias<"vgtl", "vgtl.zx">;287def : MnemonicAlias<"vgtl.nc", "vgtl.zx.nc">;288 289// Multiclass for VSC instructions290let mayStore = 1, hasSideEffects = 0, Uses = [VL] in291multiclass VSCbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {292 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;293 let isCodeGenOnly = 1, VE_VLInUse = 1 in {294 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),295 !strconcat(opcStr, argStr)>;296 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),297 !strconcat(opcStr, argStr)>;298 }299}300multiclass VSCmm<string opcStr, string argStr, bits<8>opc, dag dag_in> {301 defm "" : VSCbm<opcStr, argStr, opc, dag_in>;302 let m = ?, VE_VLWithMask = 1 in303 defm m : VSCbm<opcStr, argStr#", $m", opc, !con(dag_in, (ins VM:$m))>;304}305let VE_VLIndex = 4 in306multiclass VSClhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,307 dag dag_in> {308 defm rrv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,309 !con(dag_in, (ins I64:$sy, I64:$sz, RC:$vx))>;310 let cy = 0 in311 defm irv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,312 !con(dag_in, (ins simm7:$sy, I64:$sz, RC:$vx))>;313 let cz = 0 in314 defm rzv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,315 !con(dag_in, (ins I64:$sy, zero:$sz, RC:$vx))>;316 let cy = 0, cz = 0 in317 defm izv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,318 !con(dag_in, (ins simm7:$sy, zero:$sz, RC:$vx))>;319}320multiclass VSCtgm<string opcStr, bits<8>opc, RegisterClass RC> {321 let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;322 let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;323}324multiclass VSCm<string opcStr, bits<8>opc, RegisterClass RC> {325 let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>;326 let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>;327 let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>;328 let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>;329}330 331// Section 8.9.16 - VSC (Vector Scatter)332defm VSC : VSCm<"vsc", 0xb1, V64>;333 334// Section 8.9.17 - VSCU (Vector Scatter Upper)335defm VSCU : VSCm<"vscu", 0xb2, V64>;336 337// Section 8.9.18 - VSCL (Vector Scatter Lower)338defm VSCL : VSCm<"vscl", 0xb3, V64>;339 340// Section 8.9.19 - PFCHV (Prefetch Vector)341let Uses = [VL] in342multiclass PFCHVbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {343 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;344 let isCodeGenOnly = 1, VE_VLInUse = 1 in {345 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),346 !strconcat(opcStr, argStr)>;347 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),348 !strconcat(opcStr, argStr)>;349 }350}351let VE_VLIndex = 2 in352multiclass PFCHVm<string opcStr, bits<8>opc> {353 defm rr : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, I64:$sz)>;354 let cy = 0 in355 defm ir : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, I64:$sz)>;356 let cz = 0 in357 defm rz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, zero:$sz)>;358 let cy = 0, cz = 0 in359 defm iz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, zero:$sz)>;360}361let vc = 1, vx = 0 in defm PFCHV : PFCHVm<"pfchv", 0x80>;362let vc = 0, vx = 0 in defm PFCHVNC : PFCHVm<"pfchv.nc", 0x80>;363 364// Section 8.9.20 - LSV (Load S to V)365let sx = 0, vx = ?, hasSideEffects = 0 in366multiclass LSVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,367 dag dag_in> {368 def "" : RR<opc, (outs RC:$vx), dag_in, !strconcat(opcStr, " ${vx}", argStr)>;369 let Constraints = "$vx = $base", isCodeGenOnly = 1 in370 def _v : RR<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),371 !strconcat(opcStr, " ${vx}", argStr)>;372}373multiclass LSVm<string opcStr, bits<8>opc, RegisterClass RC> {374 defm rr : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, I64:$sz)>;375 let cy = 0 in376 defm ir : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, I64:$sz)>;377 let cz = 0 in378 defm rm : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, mimm:$sz)>;379 let cy = 0, cz = 0 in380 defm im : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, mimm:$sz)>;381}382defm LSV : LSVm<"lsv", 0x8e, V64>;383 384// Section 8.9.21 - LVS (Load V to S)385let cz = 0, sz = 0, vx = ?, hasSideEffects = 0 in386multiclass LVSm<string opcStr, bits<8>opc, RegisterClass RC> {387 def vr : RR<opc, (outs I64:$sx), (ins RC:$vx, I64:$sy),388 opcStr#" $sx, ${vx}(${sy})">;389 let cy = 0 in390 def vi : RR<opc, (outs I64:$sx), (ins RC:$vx, uimm7:$sy),391 opcStr#" $sx, ${vx}(${sy})">;392}393defm LVS : LVSm<"lvs", 0x9e, V64>;394 395// Section 8.9.22 - LVM (Load VM)396let sx = 0, vx = ?, hasSideEffects = 0 in397multiclass LVMbm<string opcStr, string argStr, bits<8>opc, RegisterClass RCM,398 dag dag_in> {399 def "" : RR<opc, (outs RCM:$vx), dag_in,400 !strconcat(opcStr, " $vx, ", argStr)>;401 let Constraints = "$vx = $base", isCodeGenOnly = 1 in {402 def _m : RR<opc, (outs RCM:$vx), !con(dag_in, (ins RCM:$base)),403 !strconcat(opcStr, " $vx, ", argStr)>;404 }405}406multiclass LVMom<string opcStr, bits<8>opc, RegisterClass RCM> {407 defm rr : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins I64:$sy, I64:$sz)>;408 let cy = 0 in409 defm ir : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins uimm2:$sy, I64:$sz)>;410 let cz = 0 in411 defm rm : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins I64:$sy, mimm:$sz)>;412 let cy = 0, cz = 0 in413 defm im : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins uimm2:$sy, mimm:$sz)>;414}415multiclass LVMm<string opcStr, bits<8>opc, RegisterClass RCM> {416 defm "" : LVMom<opcStr, opc, RCM>;417}418defm LVM : LVMm<"lvm", 0xb7, VM>;419 420// Section 8.9.23 - SVM (Save VM)421let cz = 0, sz = 0, vz = ?, hasSideEffects = 0 in422multiclass SVMm<string opcStr, bits<8>opc, RegisterClass RCM> {423 def mr : RR<opc, (outs I64:$sx), (ins RCM:$vz, I64:$sy),424 opcStr#" $sx, $vz, $sy">;425 let cy = 0 in426 def mi : RR<opc, (outs I64:$sx), (ins RCM:$vz, uimm2:$sy),427 opcStr#" $sx, $vz, $sy">;428}429defm SVM : SVMm<"svm", 0xa7, VM>;430 431// Section 8.9.24 - VBRD (Vector Broadcast)432let vx = ?, hasSideEffects = 0, Uses = [VL] in433multiclass VBRDbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,434 dag dag_in> {435 def "" : RV<opc, (outs RC:$vx), dag_in,436 !strconcat(opcStr, " $vx, ", argStr)>;437 let Constraints = "$vx = $base",438 isCodeGenOnly = 1 in439 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),440 !strconcat(opcStr, " $vx, ", argStr)>;441}442multiclass VBRDlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,443 dag dag_in> {444 defm "" : VBRDbm<opcStr, argStr, opc, RC, dag_in>;445 let isCodeGenOnly = 1, VE_VLInUse = 1 in {446 defm l : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl))>;447 defm L : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl))>;448 }449}450multiclass VBRDmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,451 RegisterClass RCM, dag dag_in> {452 defm "" : VBRDlm<opcStr, argStr, opc, RC, dag_in>;453 let m = ?, VE_VLWithMask = 1 in454 defm m : VBRDlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;455}456let VE_VLIndex = 2 in457multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,458 RegisterClass RCM> {459 defm r : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins RC:$sy)>;460 let cy = 0 in461 defm i : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins simm7:$sy)>;462}463let cx = 0, cx2 = 0 in464defm VBRD : VBRDm<"vbrd", 0x8c, V64, I64, VM>;465let cx = 0, cx2 = 1 in466defm VBRDL : VBRDm<"vbrdl", 0x8c, V64, I32, VM>;467let cx = 1, cx2 = 0 in468defm VBRDU : VBRDm<"vbrdu", 0x8c, V64, F32, VM>;469let cx = 1, cx2 = 1 in470defm PVBRD : VBRDm<"pvbrd", 0x8c, V64, I64, VM512>;471 472// Section 8.9.25 - VMV (Vector Move)473let vx = ?, vz = ?, hasSideEffects = 0, Uses = [VL] in474multiclass VMVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,475 dag dag_in> {476 def "" : RV<opc, (outs RC:$vx), dag_in,477 !strconcat(opcStr, " $vx, ", argStr)>;478 let Constraints = "$vx = $base",479 isCodeGenOnly = 1 in480 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),481 !strconcat(opcStr, " $vx, ", argStr)>;482}483multiclass VMVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,484 dag dag_in> {485 defm "" : VMVbm<opcStr, argStr, opc, RC, dag_in>;486 let isCodeGenOnly = 1, VE_VLInUse = 1 in {487 defm l : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl))>;488 defm L : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl))>;489 }490}491multiclass VMVmm<string opcStr, bits<8>opc, RegisterClass RC,492 RegisterClass RCM, dag dag_in> {493 defm "" : VMVlm<opcStr, "$sy, $vz", opc, RC, dag_in>;494 let m = ?, VE_VLWithMask = 1 in495 defm m : VMVlm<opcStr, "$sy, $vz, $m", opc, RC, !con(dag_in, (ins RCM:$m))>;496}497let VE_VLIndex = 3 in498multiclass VMVm<string opcStr, bits<8>opc, RegisterClass RC,499 RegisterClass RCM> {500 defm rv : VMVmm<opcStr, opc, RC, RCM, (ins I64:$sy, RC:$vz)>;501 let cy = 0 in502 defm iv : VMVmm<opcStr, opc, RC, RCM, (ins uimm7:$sy, RC:$vz)>;503}504defm VMV : VMVm<"vmv", 0x9c, V64, VM>;505 506//-----------------------------------------------------------------------------507// Section 8.10 - Vector Fixed-Point Arithmetic Instructions508//-----------------------------------------------------------------------------509 510// Multiclass for generic vector calculation511let vx = ?, hasSideEffects = 0, Uses = [VL] in512multiclass RVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,513 dag dag_in> {514 def "" : RV<opc, (outs RC:$vx), dag_in,515 !strconcat(opcStr, " $vx", argStr)>;516 let Constraints = "$vx = $base", isCodeGenOnly = 1 in517 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),518 !strconcat(opcStr, " $vx", argStr)>;519}520multiclass RVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,521 dag dag_in> {522 defm "" : RVbm<opcStr, argStr, opc, RC, dag_in>;523 let isCodeGenOnly = 1, VE_VLInUse = 1 in {524 defm l : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl))>;525 defm L : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl))>;526 }527}528multiclass RVmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,529 RegisterClass RCM, dag dag_in> {530 defm "" : RVlm<opcStr, argStr, opc, RC, dag_in>;531 let m = ?, VE_VLWithMask = 1 in532 defm m : RVlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;533}534// Generic RV multiclass with 2 arguments.535// e.g. VADD, VSUB, VMPY, and etc.536let VE_VLIndex = 3 in537multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,538 RegisterClass RCM, Operand SIMM = simm7> {539 let cy = 0, sy = 0, vy = ?, vz = ? in540 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;541 let cs = 1, vz = ? in542 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;543 let cs = 1, cy = 0, vz = ? in544 defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>;545}546// Special RV multiclass with 2 arguments using cs2.547// e.g. VDIV, VDVS, and VDVX.548let VE_VLIndex = 3 in549multiclass RVDIVm<string opcStr, bits<8>opc, RegisterClass VRC,550 RegisterClass RC, RegisterClass RCM, Operand SIMM = simm7> {551 let cy = 0, sy = 0, vy = ?, vz = ? in552 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;553 let cs2 = 1, vy = ? in554 defm vr : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, RC:$sy)>;555 let cs2 = 1, cy = 0, vy = ? in556 defm vi : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, SIMM:$sy)>;557 let cs = 1, vz = ? in558 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;559 let cs = 1, cy = 0, vz = ? in560 defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>;561}562// Generic RV multiclass with 2 arguments for logical operations.563// e.g. VAND, VOR, VXOR, and etc.564let VE_VLIndex = 3 in565multiclass RVLm<string opcStr, bits<8>opc, RegisterClass ScaRC,566 RegisterClass RC, RegisterClass RCM> {567 let cy = 0, sy = 0, vy = ?, vz = ? in568 defm vv : RVmm<opcStr, ", $vy, $vz", opc, RC, RCM, (ins RC:$vy, RC:$vz)>;569 let cs = 1, vz = ? in570 defm rv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins ScaRC:$sy, RC:$vz)>;571 let cs = 1, cy = 0, vz = ? in572 defm mv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins mimm:$sy, RC:$vz)>;573}574// Generic RV multiclass with 1 argument.575// e.g. VLDZ, VPCNT, and VBRV.576let VE_VLIndex = 2 in577multiclass RV1m<string opcStr, bits<8>opc, RegisterClass RC,578 RegisterClass RCM> {579 let cy = 0, sy = 0, vz = ? in580 defm v : RVmm<opcStr, ", $vz", opc, RC, RCM, (ins RC:$vz)>;581}582// Generic RV multiclass with no argument.583// e.g. VSEQ.584let VE_VLIndex = 1 in585multiclass RV0m<string opcStr, bits<8>opc, RegisterClass RC,586 RegisterClass RCM> {587 let cy = 0, sy = 0 in588 defm "" : RVmm<opcStr, "", opc, RC, RCM, (ins)>;589}590// Generic RV multiclass with 2 arguments for shift operations.591// e.g. VSLL, VSRL, VSLA, and etc.592let VE_VLIndex = 3 in593multiclass RVSm<string opcStr, bits<8>opc, RegisterClass ScaRC,594 RegisterClass RC, RegisterClass RCM> {595 let cy = 0, sy = 0, vy = ?, vz = ? in596 defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>;597 let cs = 1, vz = ? in598 defm vr : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, ScaRC:$sy)>;599 let cs = 1, cy = 0, vz = ? in600 defm vi : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, uimm7:$sy)>;601}602// Generic RV multiclass with 3 arguments for shift operations.603// e.g. VSLD and VSRD.604let VE_VLIndex = 4 in605multiclass RVSDm<string opcStr, bits<8>opc, RegisterClass RC,606 RegisterClass RCM> {607 let vy = ?, vz = ? in608 defm vvr : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,609 (ins RC:$vy, RC:$vz, I64:$sy)>;610 let cy = 0, vy = ?, vz = ? in611 defm vvi : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,612 (ins RC:$vy, RC:$vz, uimm7:$sy)>;613}614// Special RV multiclass with 3 arguments.615// e.g. VSFA616let VE_VLIndex = 4 in617multiclass RVSAm<string opcStr, bits<8>opc, RegisterClass RC,618 RegisterClass RCM> {619 let cz = 1, sz = ?, vz = ? in620 defm vrr : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,621 (ins RC:$vz, I64:$sy, I64:$sz)>;622 let cz = 0, sz = ?, vz = ? in623 defm vrm : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,624 (ins RC:$vz, I64:$sy, mimm:$sz)>;625 let cy = 0, cz = 1, sz = ?, vz = ? in626 defm vir : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,627 (ins RC:$vz, uimm3:$sy, I64:$sz)>;628 let cy = 0, cz = 0, sz = ?, vz = ? in629 defm vim : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,630 (ins RC:$vz, uimm3:$sy, mimm:$sz)>;631}632// Generic RV multiclass with 1 argument using vy field.633// e.g. VFSQRT, VRCP, and VRSQRT.634let VE_VLIndex = 2 in635multiclass RVF1m<string opcStr, bits<8>opc, RegisterClass RC,636 RegisterClass RCM> {637 let cy = 0, sy = 0, vy = ? in638 defm v : RVmm<opcStr, ", $vy", opc, RC, RCM, (ins RC:$vy)>;639}640// Special RV multiclass with 3 arguments using cs2.641// e.g. VFMAD, VFMSB, VFNMAD, and etc.642let VE_VLIndex = 4 in643multiclass RVMm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,644 RegisterClass RCM, Operand SIMM = simm7> {645 let cy = 0, sy = 0, vy = ?, vz = ?, vw = ? in646 defm vvv : RVmm<opcStr, ", $vy, $vz, $vw", opc, VRC, RCM,647 (ins VRC:$vy, VRC:$vz, VRC:$vw)>;648 let cs2 = 1, vy = ?, vw = ? in649 defm vrv : RVmm<opcStr, ", $vy, $sy, $vw", opc, VRC, RCM,650 (ins VRC:$vy, RC:$sy, VRC:$vw)>;651 let cs2 = 1, cy = 0, vy = ?, vw = ? in652 defm viv : RVmm<opcStr, ", $vy, $sy, $vw", opc, VRC, RCM,653 (ins VRC:$vy, SIMM:$sy, VRC:$vw)>;654 let cs = 1, vz = ?, vw = ? in655 defm rvv : RVmm<opcStr, ", $sy, $vz, $vw", opc, VRC, RCM,656 (ins RC:$sy, VRC:$vz, VRC:$vw)>;657 let cs = 1, cy = 0, vz = ?, vw = ? in658 defm ivv : RVmm<opcStr, ", $sy, $vz, $vw", opc, VRC, RCM,659 (ins SIMM:$sy, VRC:$vz, VRC:$vw)>;660}661// Special RV multiclass with 2 arguments for floating point conversions.662// e.g. VFIX and VFIXX663let hasSideEffects = 0, VE_VLIndex = 3 in664multiclass RVFIXm<string opcStr, bits<8> opc, RegisterClass RC,665 RegisterClass RCM> {666 let cy = 0, sy = 0, vy = ?, vz = ? in667 defm v : RVmm<opcStr#"$vz", ", $vy", opc, RC, RCM, (ins RDOp:$vz, RC:$vy)>;668}669// Multiclass for generic iterative vector calculation670let vx = ?, hasSideEffects = 0, Uses = [VL] in671multiclass RVIbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,672 dag dag_in> {673 def "" : RV<opc, (outs RC:$vx), dag_in,674 !strconcat(opcStr, " $vx", argStr)>;675 let isCodeGenOnly = 1, Constraints = "$vx = $base" in676 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),677 !strconcat(opcStr, " $vx", argStr)>;678}679multiclass RVIlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,680 dag dag_in> {681 defm "" : RVIbm<opcStr, argStr, opc, RC, dag_in>;682 let isCodeGenOnly = 1, VE_VLInUse = 1 in {683 defm l : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl))>;684 defm L : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl))>;685 }686}687// Generic RV multiclass for iterative operation with 2 argument.688// e.g. VFIA, VFIS, and VFIM689let VE_VLIndex = 3 in690multiclass RVI2m<string opcStr, bits<8>opc, RegisterClass VRC,691 RegisterClass RC> {692 let vy = ? in693 defm vr : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, RC:$sy)>;694 let cy = 0, vy = ? in695 defm vi : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, simm7fp:$sy)>;696}697// Generic RV multiclass for iterative operation with 3 argument.698// e.g. VFIAM, VFISM, VFIMA, and etc.699let VE_VLIndex = 4 in700multiclass RVI3m<string opcStr, bits<8>opc, RegisterClass VRC,701 RegisterClass RC> {702 let vy = ?, vz = ? in703 defm vvr : RVIlm<opcStr, ", $vy, $vz, $sy", opc, VRC,704 (ins VRC:$vy, VRC:$vz, RC:$sy)>;705 let cy = 0, vy = ?, vz = ? in706 defm vvi : RVIlm<opcStr, ", $vy, $vz, $sy", opc, VRC,707 (ins VRC:$vy, VRC:$vz, simm7fp:$sy)>;708}709// special RV multiclass with 3 arguments for VSHF.710// e.g. VSHF711let vy = ?, vz = ?, VE_VLIndex = 4 in712multiclass RVSHFm<string opcStr, bits<8>opc, RegisterClass RC,713 Operand SIMM = uimm4> {714 defm vvr : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,715 (ins RC:$vy, RC:$vz, I64:$sy)>;716 let cy = 0 in defm vvi : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,717 (ins RC:$vy, RC:$vz, SIMM:$sy)>;718}719// Multiclass for generic mask calculation720let vx = ?, hasSideEffects = 0, Uses = [VL] in721multiclass RVMKbm<string opcStr, string argStr, bits<8>opc, dag dag_out,722 dag dag_in> {723 def "" : RV<opc, dag_out, dag_in, !strconcat(opcStr, argStr)>;724 let isCodeGenOnly = 1, VE_VLInUse = 1 in {725 def l : RV<opc, dag_out, !con(dag_in, (ins I32:$vl)),726 !strconcat(opcStr, argStr)>;727 def L : RV<opc, dag_out, !con(dag_in, (ins VLS:$vl)),728 !strconcat(opcStr, argStr)>;729 }730}731multiclass RVMKlm<string opcStr, string argStr, bits<8>opc, RegisterClass RCM,732 dag dag_in> {733 defm "" : RVMKbm<opcStr, " $vx"#argStr, opc, (outs RCM:$vx), dag_in>;734 let m = ?, VE_VLWithMask = 1 in735 defm m : RVMKbm<opcStr, " $vx"#argStr#", $m", opc, (outs RCM:$vx),736 !con(dag_in, (ins RCM:$m))>;737}738// Generic RV multiclass for mask calculation with a condition.739// e.g. VFMK, VFMS, and VFMF740let cy = 0, sy = 0 in741multiclass RVMKom<string opcStr, bits<8> opc, RegisterClass RC,742 RegisterClass RCM> {743 let vy = ?, vz = ?, VE_VLIndex = 3 in744 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>;745 let vy = 15 /* AT */, VE_VLIndex = 1 in746 defm a : RVMKlm<opcStr#"at", "", opc, RCM, (ins)>;747 let vy = 0 /* AF */, VE_VLIndex = 1 in748 defm na : RVMKlm<opcStr#"af", "", opc, RCM, (ins)>;749}750multiclass RVMKm<string opcStr, bits<8> opc, RegisterClass RC,751 RegisterClass RCM> {752 defm "" : RVMKom<opcStr, opc, RC, RCM>;753}754// Generic RV multiclass for mask calculation with 2 arguments.755// e.g. ANDM, ORM, XORM, and etc.756let cy = 0, sy = 0, vx = ?, vy = ?, vz = ?, hasSideEffects = 0 in757multiclass RVM2m<string opcStr, bits<8> opc, RegisterClass RCM> {758 def mm : RV<opc, (outs RCM:$vx), (ins RCM:$vy, RCM:$vz),759 !strconcat(opcStr, " $vx, $vy, $vz")>;760}761// Generic RV multiclass for mask calculation with 1 argument.762// e.g. NEGM763let cy = 0, sy = 0, vx = ?, vy = ?, hasSideEffects = 0 in764multiclass RVM1m<string opcStr, bits<8> opc, RegisterClass RCM> {765 def m : RV<opc, (outs RCM:$vx), (ins RCM:$vy),766 !strconcat(opcStr, " $vx, $vy")>;767}768// Generic RV multiclass for mask calculation with 1 argument.769// e.g. PCVM, LZVM, and TOVM770let cy = 0, sy = 0, vy = ?, hasSideEffects = 0, Uses = [VL] in771multiclass RVMSbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {772 def "" : RV<opc, (outs I64:$sx), dag_in,773 !strconcat(opcStr, " $sx,", argStr)> {774 bits<7> sx;775 let Inst{54-48} = sx;776 }777 let isCodeGenOnly = 1, VE_VLInUse = 1 in {778 def l : RV<opc, (outs I64:$sx), !con(dag_in, (ins I32:$vl)),779 !strconcat(opcStr, " $sx,", argStr)> {780 bits<7> sx;781 let Inst{54-48} = sx;782 }783 def L : RV<opc, (outs I64:$sx), !con(dag_in, (ins VLS:$vl)),784 !strconcat(opcStr, " $sx,", argStr)> {785 bits<7> sx;786 let Inst{54-48} = sx;787 }788 }789}790let VE_VLIndex = 2 in791multiclass RVMSm<string opcStr, bits<8> opc, RegisterClass RCM> {792 defm m : RVMSbm<opcStr, " $vy", opc, (ins RCM:$vy)>;793}794 795// Section 8.10.1 - VADD (Vector Add)796let cx = 0, cx2 = 0 in797defm VADDUL : RVm<"vaddu.l", 0xc8, V64, I64, VM>;798let cx = 0, cx2 = 1 in {799 defm PVADDULO : RVm<"pvaddu.lo", 0xc8, V64, I32, VM>;800 let isCodeGenOnly = 1 in801 defm VADDUW : RVm<"vaddu.w", 0xc8, V64, I32, VM>;802}803let cx = 1, cx2 = 0 in804defm PVADDUUP : RVm<"pvaddu.up", 0xc8, V64, I64, VM>;805let cx = 1, cx2 = 1 in806defm PVADDU : RVm<"pvaddu", 0xc8, V64, I64, VM512>;807def : MnemonicAlias<"vaddu.w", "pvaddu.lo">;808 809// Section 8.10.2 - VADS (Vector Add Single)810let cx = 0, cx2 = 0 in811defm VADDSWSX : RVm<"vadds.w.sx", 0xca, V64, I32, VM>;812let cx = 0, cx2 = 1 in {813 defm PVADDSLO : RVm<"pvadds.lo", 0xca, V64, I32, VM>;814 let isCodeGenOnly = 1 in815 defm VADDSWZX : RVm<"vadds.w.zx", 0xca, V64, I32, VM>;816}817let cx = 1, cx2 = 0 in818defm PVADDSUP : RVm<"pvadds.up", 0xca, V64, I64, VM>;819let cx = 1, cx2 = 1 in820defm PVADDS : RVm<"pvadds", 0xca, V64, I64, VM512>;821def : MnemonicAlias<"pvadds.lo.sx", "vadds.w.sx">;822def : MnemonicAlias<"vadds.w.zx", "pvadds.lo">;823def : MnemonicAlias<"vadds.w", "pvadds.lo">;824def : MnemonicAlias<"pvadds.lo.zx", "pvadds.lo">;825 826// Section 8.10.3 - VADX (Vector Add)827defm VADDSL : RVm<"vadds.l", 0x8b, V64, I64, VM>;828 829// Section 8.10.4 - VSUB (Vector Subtract)830let cx = 0, cx2 = 0 in831defm VSUBUL : RVm<"vsubu.l", 0xd8, V64, I64, VM>;832let cx = 0, cx2 = 1 in {833 defm PVSUBULO : RVm<"pvsubu.lo", 0xd8, V64, I32, VM>;834 let isCodeGenOnly = 1 in835 defm VSUBUW : RVm<"vsubu.w", 0xd8, V64, I32, VM>;836}837let cx = 1, cx2 = 0 in838defm PVSUBUUP : RVm<"pvsubu.up", 0xd8, V64, I64, VM>;839let cx = 1, cx2 = 1 in840defm PVSUBU : RVm<"pvsubu", 0xd8, V64, I64, VM512>;841def : MnemonicAlias<"vsubu.w", "pvsubu.lo">;842 843// Section 8.10.5 - VSBS (Vector Subtract Single)844let cx = 0, cx2 = 0 in845defm VSUBSWSX : RVm<"vsubs.w.sx", 0xda, V64, I32, VM>;846let cx = 0, cx2 = 1 in {847 defm PVSUBSLO : RVm<"pvsubs.lo", 0xda, V64, I32, VM>;848 let isCodeGenOnly = 1 in849 defm VSUBSWZX : RVm<"vsubs.w.zx", 0xda, V64, I32, VM>;850}851let cx = 1, cx2 = 0 in852defm PVSUBSUP : RVm<"pvsubs.up", 0xda, V64, I64, VM>;853let cx = 1, cx2 = 1 in854defm PVSUBS : RVm<"pvsubs", 0xda, V64, I64, VM512>;855def : MnemonicAlias<"pvsubs.lo.sx", "vsubs.w.sx">;856def : MnemonicAlias<"vsubs.w.zx", "pvsubs.lo">;857def : MnemonicAlias<"vsubs.w", "pvsubs.lo">;858def : MnemonicAlias<"pvsubs.lo.zx", "pvsubs.lo">;859 860// Section 8.10.6 - VSBX (Vector Subtract)861defm VSUBSL : RVm<"vsubs.l", 0x9b, V64, I64, VM>;862 863// Section 8.10.7 - VMPY (Vector Multiply)864let cx2 = 0 in865defm VMULUL : RVm<"vmulu.l", 0xc9, V64, I64, VM>;866let cx2 = 1 in867defm VMULUW : RVm<"vmulu.w", 0xc9, V64, I32, VM>;868 869// Section 8.10.8 - VMPS (Vector Multiply Single)870let cx2 = 0 in871defm VMULSWSX : RVm<"vmuls.w.sx", 0xcb, V64, I32, VM>;872let cx2 = 1 in873defm VMULSWZX : RVm<"vmuls.w.zx", 0xcb, V64, I32, VM>;874def : MnemonicAlias<"vmuls.w", "vmuls.w.zx">;875 876// Section 8.10.9 - VMPX (Vector Multiply)877defm VMULSL : RVm<"vmuls.l", 0xdb, V64, I64, VM>;878 879// Section 8.10.10 - VMPD (Vector Multiply)880defm VMULSLW : RVm<"vmuls.l.w", 0xd9, V64, I32, VM>;881 882// Section 8.10.11 - VDIV (Vector Divide)883let cx2 = 0 in884defm VDIVUL : RVDIVm<"vdivu.l", 0xe9, V64, I64, VM>;885let cx2 = 1 in886defm VDIVUW : RVDIVm<"vdivu.w", 0xe9, V64, I32, VM>;887 888// Section 8.10.12 - VDVS (Vector Divide Single)889let cx2 = 0 in890defm VDIVSWSX : RVDIVm<"vdivs.w.sx", 0xeb, V64, I32, VM>;891let cx2 = 1 in892defm VDIVSWZX : RVDIVm<"vdivs.w.zx", 0xeb, V64, I32, VM>;893def : MnemonicAlias<"vdivs.w", "vdivs.w.zx">;894 895// Section 8.10.13 - VDVX (Vector Divide)896defm VDIVSL : RVDIVm<"vdivs.l", 0xfb, V64, I64, VM>;897 898// Section 8.10.14 - VCMP (Vector Compare)899let cx = 0, cx2 = 0 in900defm VCMPUL : RVm<"vcmpu.l", 0xb9, V64, I64, VM>;901let cx = 0, cx2 = 1 in {902 defm PVCMPULO : RVm<"pvcmpu.lo", 0xb9, V64, I32, VM>;903 let isCodeGenOnly = 1 in904 defm VCMPUW : RVm<"vcmpu.w", 0xb9, V64, I32, VM>;905}906let cx = 1, cx2 = 0 in907defm PVCMPUUP : RVm<"pvcmpu.up", 0xb9, V64, I64, VM>;908let cx = 1, cx2 = 1 in909defm PVCMPU : RVm<"pvcmpu", 0xb9, V64, I64, VM512>;910def : MnemonicAlias<"vcmpu.w", "pvcmpu.lo">;911 912// Section 8.10.15 - VCPS (Vector Compare Single)913let cx = 0, cx2 = 0 in914defm VCMPSWSX : RVm<"vcmps.w.sx", 0xfa, V64, I32, VM>;915let cx = 0, cx2 = 1 in {916 defm PVCMPSLO : RVm<"pvcmps.lo", 0xfa, V64, I32, VM>;917 let isCodeGenOnly = 1 in918 defm VCMPSWZX : RVm<"vcmps.w.zx", 0xfa, V64, I32, VM>;919}920let cx = 1, cx2 = 0 in921defm PVCMPSUP : RVm<"pvcmps.up", 0xfa, V64, I64, VM>;922let cx = 1, cx2 = 1 in923defm PVCMPS : RVm<"pvcmps", 0xfa, V64, I64, VM512>;924def : MnemonicAlias<"pvcmps.lo.sx", "vcmps.w.sx">;925def : MnemonicAlias<"vcmps.w.zx", "pvcmps.lo">;926def : MnemonicAlias<"vcmps.w", "pvcmps.lo">;927def : MnemonicAlias<"pvcmps.lo.zx", "pvcmps.lo">;928 929// Section 8.10.16 - VCPX (Vector Compare)930defm VCMPSL : RVm<"vcmps.l", 0xba, V64, I64, VM>;931 932// Section 8.10.17 - VCMS (Vector Compare and Select Maximum/Minimum Single)933let cx = 0, cx2 = 0 in934defm VMAXSWSX : RVm<"vmaxs.w.sx", 0x8a, V64, I32, VM>;935let cx = 0, cx2 = 1 in {936 defm PVMAXSLO : RVm<"pvmaxs.lo", 0x8a, V64, I32, VM>;937 let isCodeGenOnly = 1 in938 defm VMAXSWZX : RVm<"vmaxs.w.zx", 0x8a, V64, I32, VM>;939}940let cx = 1, cx2 = 0 in941defm PVMAXSUP : RVm<"pvmaxs.up", 0x8a, V64, I64, VM>;942let cx = 1, cx2 = 1 in943defm PVMAXS : RVm<"pvmaxs", 0x8a, V64, I64, VM512>;944let cs2 = 1 in {945 let cx = 0, cx2 = 0 in946 defm VMINSWSX : RVm<"vmins.w.sx", 0x8a, V64, I32, VM>;947 let cx = 0, cx2 = 1 in {948 defm PVMINSLO : RVm<"pvmins.lo", 0x8a, V64, I32, VM>;949 let isCodeGenOnly = 1 in950 defm VMINSWZX : RVm<"vmins.w.zx", 0x8a, V64, I32, VM>;951 }952 let cx = 1, cx2 = 0 in953 defm PVMINSUP : RVm<"pvmins.up", 0x8a, V64, I64, VM>;954 let cx = 1, cx2 = 1 in955 defm PVMINS : RVm<"pvmins", 0x8a, V64, I64, VM512>;956}957def : MnemonicAlias<"pvmaxs.lo.sx", "vmaxs.w.sx">;958def : MnemonicAlias<"vmaxs.w.zx", "pvmaxs.lo">;959def : MnemonicAlias<"vmaxs.w", "pvmaxs.lo">;960def : MnemonicAlias<"pvmaxs.lo.zx", "pvmaxs.lo">;961def : MnemonicAlias<"pvmins.lo.sx", "vmins.w.sx">;962def : MnemonicAlias<"vmins.w.zx", "pvmins.lo">;963def : MnemonicAlias<"vmins.w", "pvmins.lo">;964def : MnemonicAlias<"pvmins.lo.zx", "pvmins.lo">;965 966// Section 8.10.18 - VCMX (Vector Compare and Select Maximum/Minimum)967defm VMAXSL : RVm<"vmaxs.l", 0x9a, V64, I64, VM>;968let cs2 = 1 in969defm VMINSL : RVm<"vmins.l", 0x9a, V64, I64, VM>;970 971//-----------------------------------------------------------------------------972// Section 8.11 - Vector Logical Operation Instructions973//-----------------------------------------------------------------------------974 975// Section 8.11.1 - VAND (Vector And)976let cx = 0, cx2 = 0 in defm VAND : RVLm<"vand", 0xc4, I64, V64, VM>;977let cx = 0, cx2 = 1 in defm PVANDLO : RVLm<"pvand.lo", 0xc4, I32, V64, VM>;978let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, F32, V64, VM>;979let cx = 1, cx2 = 1 in defm PVAND : RVLm<"pvand", 0xc4, I64, V64, VM512>;980 981// Section 8.11.2 - VOR (Vector Or)982let cx = 0, cx2 = 0 in defm VOR : RVLm<"vor", 0xc5, I64, V64, VM>;983let cx = 0, cx2 = 1 in defm PVORLO : RVLm<"pvor.lo", 0xc5, I32, V64, VM>;984let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, F32, V64, VM>;985let cx = 1, cx2 = 1 in defm PVOR : RVLm<"pvor", 0xc5, I64, V64, VM512>;986 987// Section 8.11.3 - VXOR (Vector Exclusive Or)988let cx = 0, cx2 = 0 in defm VXOR : RVLm<"vxor", 0xc6, I64, V64, VM>;989let cx = 0, cx2 = 1 in defm PVXORLO : RVLm<"pvxor.lo", 0xc6, I32, V64, VM>;990let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, F32, V64, VM>;991let cx = 1, cx2 = 1 in defm PVXOR : RVLm<"pvxor", 0xc6, I64, V64, VM512>;992 993// Section 8.11.4 - VEQV (Vector Equivalence)994let cx = 0, cx2 = 0 in defm VEQV : RVLm<"veqv", 0xc7, I64, V64, VM>;995let cx = 0, cx2 = 1 in defm PVEQVLO : RVLm<"pveqv.lo", 0xc7, I32, V64, VM>;996let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, F32, V64, VM>;997let cx = 1, cx2 = 1 in defm PVEQV : RVLm<"pveqv", 0xc7, I64, V64, VM512>;998 999// Section 8.11.5 - VLDZ (Vector Leading Zero Count)1000let cx = 0, cx2 = 0 in defm VLDZ : RV1m<"vldz", 0xe7, V64, VM>;1001let cx = 0, cx2 = 1 in defm PVLDZLO : RV1m<"pvldz.lo", 0xe7, V64, VM>;1002let cx = 1, cx2 = 0 in defm PVLDZUP : RV1m<"pvldz.up", 0xe7, V64, VM>;1003let cx = 1, cx2 = 1 in defm PVLDZ : RV1m<"pvldz", 0xe7, V64, VM512>;1004 1005// Section 8.11.6 - VPCNT (Vector Population Count)1006let cx = 0, cx2 = 0 in defm VPCNT : RV1m<"vpcnt", 0xac, V64, VM>;1007let cx = 0, cx2 = 1 in defm PVPCNTLO : RV1m<"pvpcnt.lo", 0xac, V64, VM>;1008let cx = 1, cx2 = 0 in defm PVPCNTUP : RV1m<"pvpcnt.up", 0xac, V64, VM>;1009let cx = 1, cx2 = 1 in defm PVPCNT : RV1m<"pvpcnt", 0xac, V64, VM512>;1010 1011// Section 8.11.7 - VBRV (Vector Bit Reverse)1012let cx = 0, cx2 = 0 in defm VBRV : RV1m<"vbrv", 0xf7, V64, VM>;1013let cx = 0, cx2 = 1 in defm PVBRVLO : RV1m<"pvbrv.lo", 0xf7, V64, VM>;1014let cx = 1, cx2 = 0 in defm PVBRVUP : RV1m<"pvbrv.up", 0xf7, V64, VM>;1015let cx = 1, cx2 = 1 in defm PVBRV : RV1m<"pvbrv", 0xf7, V64, VM512>;1016 1017// Section 8.11.8 - VSEQ (Vector Sequential Number)1018let cx = 0, cx2 = 0 in defm VSEQ : RV0m<"vseq", 0x99, V64, VM>;1019let cx = 0, cx2 = 1 in defm PVSEQLO : RV0m<"pvseq.lo", 0x99, V64, VM>;1020let cx = 1, cx2 = 0 in defm PVSEQUP : RV0m<"pvseq.up", 0x99, V64, VM>;1021let cx = 1, cx2 = 1 in defm PVSEQ : RV0m<"pvseq", 0x99, V64, VM512>;1022 1023//-----------------------------------------------------------------------------1024// Section 8.12 - Vector Shift Operation Instructions1025//-----------------------------------------------------------------------------1026 1027// Section 8.12.1 - VSLL (Vector Shift Left Logical)1028let cx = 0, cx2 = 0 in defm VSLL : RVSm<"vsll", 0xe5, I64, V64, VM>;1029let cx = 0, cx2 = 1 in defm PVSLLLO : RVSm<"pvsll.lo", 0xe5, I32, V64, VM>;1030let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM>;1031let cx = 1, cx2 = 1 in defm PVSLL : RVSm<"pvsll", 0xe5, I64, V64, VM512>;1032 1033// Section 8.12.2 - VSLD (Vector Shift Left Double)1034defm VSLD : RVSDm<"vsld", 0xe4, V64, VM>;1035 1036// Section 8.12.3 - VSRL (Vector Shift Right Logical)1037let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM>;1038let cx = 0, cx2 = 1 in defm PVSRLLO : RVSm<"pvsrl.lo", 0xf5, I32, V64, VM>;1039let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM>;1040let cx = 1, cx2 = 1 in defm PVSRL : RVSm<"pvsrl", 0xf5, I64, V64, VM512>;1041 1042// Section 8.12.4 - VSRD (Vector Shift Right Double)1043defm VSRD : RVSDm<"vsrd", 0xf4, V64, VM>;1044 1045// Section 8.12.5 - VSLA (Vector Shift Left Arithmetic)1046let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, I32, V64, VM>;1047let cx = 0, cx2 = 1 in {1048 defm PVSLALO : RVSm<"pvsla.lo", 0xe6, I32, V64, VM>;1049 let isCodeGenOnly = 1 in defm VSLAWZX : RVSm<"vsla.w.zx", 0xe6, I32, V64, VM>;1050}1051let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM>;1052let cx = 1, cx2 = 1 in defm PVSLA : RVSm<"pvsla", 0xe6, I64, V64, VM512>;1053def : MnemonicAlias<"pvsla.lo.sx", "vsla.w.sx">;1054def : MnemonicAlias<"vsla.w.zx", "pvsla.lo">;1055def : MnemonicAlias<"vsla.w", "pvsla.lo">;1056def : MnemonicAlias<"pvsla.lo.zx", "pvsla.lo">;1057 1058// Section 8.12.6 - VSLAX (Vector Shift Left Arithmetic)1059defm VSLAL : RVSm<"vsla.l", 0xd4, I64, V64, VM>;1060 1061// Section 8.12.7 - VSRA (Vector Shift Right Arithmetic)1062let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, I32, V64, VM>;1063let cx = 0, cx2 = 1 in {1064 defm PVSRALO : RVSm<"pvsra.lo", 0xf6, I32, V64, VM>;1065 let isCodeGenOnly = 1 in defm VSRAWZX : RVSm<"vsra.w.zx", 0xf6, I32, V64, VM>;1066}1067let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM>;1068let cx = 1, cx2 = 1 in defm PVSRA : RVSm<"pvsra", 0xf6, I64, V64, VM512>;1069def : MnemonicAlias<"pvsra.lo.sx", "vsra.w.sx">;1070def : MnemonicAlias<"vsra.w.zx", "pvsra.lo">;1071def : MnemonicAlias<"vsra.w", "pvsra.lo">;1072def : MnemonicAlias<"pvsra.lo.zx", "pvsra.lo">;1073 1074// Section 8.12.8 - VSRAX (Vector Shift Right Arithmetic)1075defm VSRAL : RVSm<"vsra.l", 0xd5, I64, V64, VM>;1076 1077// Section 8.12.9 - VSFA (Vector Shift Left and Add)1078defm VSFA : RVSAm<"vsfa", 0xd7, V64, VM>;1079 1080//-----------------------------------------------------------------------------1081// Section 8.13 - Vector Floating-Point Arithmetic Instructions1082//-----------------------------------------------------------------------------1083 1084// Section 8.13.1 - VFAD (Vector Floating Add)1085let cx = 0, cx2 = 0 in1086defm VFADDD : RVm<"vfadd.d", 0xcc, V64, I64, VM, simm7fp>;1087let cx = 0, cx2 = 1 in1088defm PVFADDLO : RVm<"pvfadd.lo", 0xcc, V64, I64, VM, simm7fp>;1089let cx = 1, cx2 = 0 in {1090 defm PVFADDUP : RVm<"pvfadd.up", 0xcc, V64, F32, VM, simm7fp>;1091 let isCodeGenOnly = 1 in1092 defm VFADDS : RVm<"vfadd.s", 0xcc, V64, F32, VM, simm7fp>;1093}1094let cx = 1, cx2 = 1 in1095defm PVFADD : RVm<"pvfadd", 0xcc, V64, I64, VM512, simm7fp>;1096def : MnemonicAlias<"vfadd.s", "pvfadd.up">;1097 1098// Section 8.13.2 - VFSB (Vector Floating Subtract)1099let cx = 0, cx2 = 0 in1100defm VFSUBD : RVm<"vfsub.d", 0xdc, V64, I64, VM, simm7fp>;1101let cx = 0, cx2 = 1 in1102defm PVFSUBLO : RVm<"pvfsub.lo", 0xdc, V64, I64, VM, simm7fp>;1103let cx = 1, cx2 = 0 in {1104 defm PVFSUBUP : RVm<"pvfsub.up", 0xdc, V64, F32, VM, simm7fp>;1105 let isCodeGenOnly = 1 in1106 defm VFSUBS : RVm<"vfsub.s", 0xdc, V64, F32, VM, simm7fp>;1107}1108let cx = 1, cx2 = 1 in1109defm PVFSUB : RVm<"pvfsub", 0xdc, V64, I64, VM512, simm7fp>;1110def : MnemonicAlias<"vfsub.s", "pvfsub.up">;1111 1112// Section 8.13.3 - VFMP (Vector Floating Multiply)1113let cx = 0, cx2 = 0 in1114defm VFMULD : RVm<"vfmul.d", 0xcd, V64, I64, VM, simm7fp>;1115let cx = 0, cx2 = 1 in1116defm PVFMULLO : RVm<"pvfmul.lo", 0xcd, V64, I64, VM, simm7fp>;1117let cx = 1, cx2 = 0 in {1118 defm PVFMULUP : RVm<"pvfmul.up", 0xcd, V64, F32, VM, simm7fp>;1119 let isCodeGenOnly = 1 in1120 defm VFMULS : RVm<"vfmul.s", 0xcd, V64, F32, VM, simm7fp>;1121}1122let cx = 1, cx2 = 1 in1123defm PVFMUL : RVm<"pvfmul", 0xcd, V64, I64, VM512, simm7fp>;1124def : MnemonicAlias<"vfmul.s", "pvfmul.up">;1125 1126// Section 8.13.4 - VFDV (Vector Floating Divide)1127defm VFDIVD : RVDIVm<"vfdiv.d", 0xdd, V64, I64, VM, simm7fp>;1128let cx = 1 in1129defm VFDIVS : RVDIVm<"vfdiv.s", 0xdd, V64, F32, VM, simm7fp>;1130 1131// Section 8.13.5 - VFSQRT (Vector Floating Square Root)1132defm VFSQRTD : RVF1m<"vfsqrt.d", 0xed, V64, VM>;1133let cx = 1 in1134defm VFSQRTS : RVF1m<"vfsqrt.s", 0xed, V64, VM>;1135 1136// Section 8.13.6 - VFCP (Vector Floating Compare)1137let cx = 0, cx2 = 0 in1138defm VFCMPD : RVm<"vfcmp.d", 0xfc, V64, I64, VM, simm7fp>;1139let cx = 0, cx2 = 1 in1140defm PVFCMPLO : RVm<"pvfcmp.lo", 0xfc, V64, I64, VM, simm7fp>;1141let cx = 1, cx2 = 0 in {1142 defm PVFCMPUP : RVm<"pvfcmp.up", 0xfc, V64, F32, VM, simm7fp>;1143 let isCodeGenOnly = 1 in1144 defm VFCMPS : RVm<"vfcmp.s", 0xfc, V64, F32, VM, simm7fp>;1145}1146let cx = 1, cx2 = 1 in1147defm PVFCMP : RVm<"pvfcmp", 0xfc, V64, I64, VM512, simm7fp>;1148def : MnemonicAlias<"vfcmp.s", "pvfcmp.up">;1149 1150// Section 8.13.7 - VFCM (Vector Floating Compare and Select Maximum/Minimum)1151let cx = 0, cx2 = 0 in1152defm VFMAXD : RVm<"vfmax.d", 0xbd, V64, I64, VM, simm7fp>;1153let cx = 0, cx2 = 1 in1154defm PVFMAXLO : RVm<"pvfmax.lo", 0xbd, V64, I64, VM, simm7fp>;1155let cx = 1, cx2 = 0 in {1156 defm PVFMAXUP : RVm<"pvfmax.up", 0xbd, V64, F32, VM, simm7fp>;1157 let isCodeGenOnly = 1 in1158 defm VFMAXS : RVm<"vfmax.s", 0xbd, V64, F32, VM, simm7fp>;1159}1160let cx = 1, cx2 = 1 in1161defm PVFMAX : RVm<"pvfmax", 0xbd, V64, I64, VM512, simm7fp>;1162let cs2 = 1 in {1163 let cx = 0, cx2 = 0 in1164 defm VFMIND : RVm<"vfmin.d", 0xbd, V64, I64, VM, simm7fp>;1165 let cx = 0, cx2 = 1 in1166 defm PVFMINLO : RVm<"pvfmin.lo", 0xbd, V64, I64, VM, simm7fp>;1167 let cx = 1, cx2 = 0 in {1168 defm PVFMINUP : RVm<"pvfmin.up", 0xbd, V64, F32, VM, simm7fp>;1169 let isCodeGenOnly = 1 in1170 defm VFMINS : RVm<"vfmin.s", 0xbd, V64, F32, VM, simm7fp>;1171 }1172 let cx = 1, cx2 = 1 in1173 defm PVFMIN : RVm<"pvfmin", 0xbd, V64, I64, VM512, simm7fp>;1174}1175def : MnemonicAlias<"vfmax.s", "pvfmax.up">;1176def : MnemonicAlias<"vfmin.s", "pvfmin.up">;1177 1178// Section 8.13.8 - VFMAD (Vector Floating Fused Multiply Add)1179let cx = 0, cx2 = 0 in1180defm VFMADD : RVMm<"vfmad.d", 0xe2, V64, I64, VM, simm7fp>;1181let cx = 0, cx2 = 1 in1182defm PVFMADLO : RVMm<"pvfmad.lo", 0xe2, V64, I64, VM, simm7fp>;1183let cx = 1, cx2 = 0 in {1184 defm PVFMADUP : RVMm<"pvfmad.up", 0xe2, V64, F32, VM, simm7fp>;1185 let isCodeGenOnly = 1 in1186 defm VFMADS : RVMm<"vfmad.s", 0xe2, V64, F32, VM, simm7fp>;1187}1188let cx = 1, cx2 = 1 in1189defm PVFMAD : RVMm<"pvfmad", 0xe2, V64, I64, VM512, simm7fp>;1190def : MnemonicAlias<"vfmad.s", "pvfmad.up">;1191 1192// Section 8.13.9 - VFMSB (Vector Floating Fused Multiply Subtract)1193let cx = 0, cx2 = 0 in1194defm VFMSBD : RVMm<"vfmsb.d", 0xf2, V64, I64, VM, simm7fp>;1195let cx = 0, cx2 = 1 in1196defm PVFMSBLO : RVMm<"pvfmsb.lo", 0xf2, V64, I64, VM, simm7fp>;1197let cx = 1, cx2 = 0 in {1198 defm PVFMSBUP : RVMm<"pvfmsb.up", 0xf2, V64, F32, VM, simm7fp>;1199 let isCodeGenOnly = 1 in1200 defm VFMSBS : RVMm<"vfmsb.s", 0xf2, V64, F32, VM, simm7fp>;1201}1202let cx = 1, cx2 = 1 in1203defm PVFMSB : RVMm<"pvfmsb", 0xf2, V64, I64, VM512, simm7fp>;1204def : MnemonicAlias<"vfmsb.s", "pvfmsb.up">;1205 1206// Section 8.13.10 - VFNMAD (Vector Floating Fused Negative Multiply Add)1207let cx = 0, cx2 = 0 in1208defm VFNMADD : RVMm<"vfnmad.d", 0xe3, V64, I64, VM, simm7fp>;1209let cx = 0, cx2 = 1 in1210defm PVFNMADLO : RVMm<"pvfnmad.lo", 0xe3, V64, I64, VM, simm7fp>;1211let cx = 1, cx2 = 0 in {1212 defm PVFNMADUP : RVMm<"pvfnmad.up", 0xe3, V64, F32, VM, simm7fp>;1213 let isCodeGenOnly = 1 in1214 defm VFNMADS : RVMm<"vfnmad.s", 0xe3, V64, F32, VM, simm7fp>;1215}1216let cx = 1, cx2 = 1 in1217defm PVFNMAD : RVMm<"pvfnmad", 0xe3, V64, I64, VM512, simm7fp>;1218def : MnemonicAlias<"vfnmad.s", "pvfnmad.up">;1219 1220// Section 8.13.11 - VFNMSB (Vector Floating Fused Negative Multiply Subtract)1221let cx = 0, cx2 = 0 in1222defm VFNMSBD : RVMm<"vfnmsb.d", 0xf3, V64, I64, VM, simm7fp>;1223let cx = 0, cx2 = 1 in1224defm PVFNMSBLO : RVMm<"pvfnmsb.lo", 0xf3, V64, I64, VM, simm7fp>;1225let cx = 1, cx2 = 0 in {1226 defm PVFNMSBUP : RVMm<"pvfnmsb.up", 0xf3, V64, F32, VM, simm7fp>;1227 let isCodeGenOnly = 1 in1228 defm VFNMSBS : RVMm<"vfnmsb.s", 0xf3, V64, F32, VM, simm7fp>;1229}1230let cx = 1, cx2 = 1 in1231defm PVFNMSB : RVMm<"pvfnmsb", 0xf3, V64, I64, VM512, simm7fp>;1232def : MnemonicAlias<"vfnmsb.s", "pvfnmsb.up">;1233 1234// Section 8.13.12 - VRCP (Vector Floating Reciprocal)1235let cx = 0, cx2 = 0 in defm VRCPD : RVF1m<"vrcp.d", 0xe1, V64, VM>;1236let cx = 0, cx2 = 1 in defm PVRCPLO : RVF1m<"pvrcp.lo", 0xe1, V64, VM>;1237let cx = 1, cx2 = 0 in {1238 defm PVRCPUP : RVF1m<"pvrcp.up", 0xe1, V64, VM>;1239 let isCodeGenOnly = 1 in defm VRCPS : RVF1m<"vrcp.s", 0xe1, V64, VM>;1240}1241let cx = 1, cx2 = 1 in defm PVRCP : RVF1m<"pvrcp", 0xe1, V64, VM512>;1242def : MnemonicAlias<"vrcp.s", "pvrcp.up">;1243 1244// Section 8.13.13 - VRSQRT (Vector Floating Reciprocal Square Root)1245let cx = 0, cx2 = 0 in defm VRSQRTD : RVF1m<"vrsqrt.d", 0xf1, V64, VM>;1246let cx = 0, cx2 = 1 in defm PVRSQRTLO : RVF1m<"pvrsqrt.lo", 0xf1, V64, VM>;1247let cx = 1, cx2 = 0 in {1248 defm PVRSQRTUP : RVF1m<"pvrsqrt.up", 0xf1, V64, VM>;1249 let isCodeGenOnly = 1 in1250 defm VRSQRTS : RVF1m<"vrsqrt.s", 0xf1, V64, VM>;1251}1252let cx = 1, cx2 = 1 in1253defm PVRSQRT : RVF1m<"pvrsqrt", 0xf1, V64, VM512>;1254let cs2 = 1 in {1255 let cx = 0, cx2 = 0 in1256 defm VRSQRTDNEX : RVF1m<"vrsqrt.d.nex", 0xf1, V64, VM>;1257 let cx = 0, cx2 = 1 in1258 defm PVRSQRTLONEX : RVF1m<"pvrsqrt.lo.nex", 0xf1, V64, VM>;1259 let cx = 1, cx2 = 0 in {1260 defm PVRSQRTUPNEX : RVF1m<"pvrsqrt.up.nex", 0xf1, V64, VM>;1261 let isCodeGenOnly = 1 in1262 defm VRSQRTSNEX : RVF1m<"vrsqrt.s.nex", 0xf1, V64, VM>;1263 }1264 let cx = 1, cx2 = 1 in1265 defm PVRSQRTNEX : RVF1m<"pvrsqrt.nex", 0xf1, V64, VM512>;1266}1267def : MnemonicAlias<"vrsqrt.s", "pvrsqrt.up">;1268def : MnemonicAlias<"vrsqrt.s.nex", "pvrsqrt.up.nex">;1269 1270// Section 8.13.14 - VFIX (Vector Convert to Fixed Pointer)1271let cx = 0, cx2 = 0, cs2 = 0 in1272defm VCVTWDSX : RVFIXm<"vcvt.w.d.sx", 0xe8, V64, VM>;1273let cx = 0, cx2 = 1, cs2 = 0 in1274defm VCVTWDZX : RVFIXm<"vcvt.w.d.zx", 0xe8, V64, VM>;1275let cx = 1, cx2 = 0, cs2 = 0 in1276defm VCVTWSSX : RVFIXm<"vcvt.w.s.sx", 0xe8, V64, VM>;1277let cx = 1, cx2 = 1, cs2 = 0 in1278defm VCVTWSZX : RVFIXm<"vcvt.w.s.zx", 0xe8, V64, VM>;1279let cx = 0, cx2 = 1, cs2 = 1 in1280defm PVCVTWSLO : RVFIXm<"pvcvt.w.s.lo", 0xe8, V64, VM>;1281let cx = 1, cx2 = 0, cs2 = 1 in1282defm PVCVTWSUP : RVFIXm<"pvcvt.w.s.up", 0xe8, V64, VM>;1283let cx = 1, cx2 = 1, cs2 = 1 in1284defm PVCVTWS : RVFIXm<"pvcvt.w.s", 0xe8, V64, VM512>;1285 1286// Section 8.13.15 - VFIXX (Vector Convert to Fixed Pointer)1287defm VCVTLD : RVFIXm<"vcvt.l.d", 0xa8, V64, VM>;1288 1289// Section 8.13.16 - VFLT (Vector Convert to Floating Pointer)1290let cx = 0, cx2 = 0, cs2 = 0 in1291defm VCVTDW : RVF1m<"vcvt.d.w", 0xf8, V64, VM>;1292let cx = 1, cx2 = 0, cs2 = 0 in1293defm VCVTSW : RVF1m<"vcvt.s.w", 0xf8, V64, VM>;1294let cx = 0, cx2 = 1, cs2 = 1 in1295defm PVCVTSWLO : RVF1m<"pvcvt.s.w.lo", 0xf8, V64, VM>;1296let cx = 1, cx2 = 0, cs2 = 1 in1297defm PVCVTSWUP : RVF1m<"pvcvt.s.w.up", 0xf8, V64, VM>;1298let cx = 1, cx2 = 1, cs2 = 1 in1299defm PVCVTSW : RVF1m<"pvcvt.s.w", 0xf8, V64, VM512>;1300 1301// Section 8.13.17 - VFLTX (Vector Convert to Floating Pointer)1302defm VCVTDL : RVF1m<"vcvt.d.l", 0xb8, V64, VM>;1303 1304// Section 8.13.18 - VCVS (Vector Convert to Single-format)1305defm VCVTSD : RVF1m<"vcvt.s.d", 0x9f, V64, VM>;1306 1307// Section 8.13.19 - VCVD (Vector Convert to Double-format)1308defm VCVTDS : RVF1m<"vcvt.d.s", 0x8f, V64, VM>;1309 1310//-----------------------------------------------------------------------------1311// Section 8.14 - Vector Reduction Instructions1312//-----------------------------------------------------------------------------1313 1314// Section 8.14.1 - VSUMS (Vector Sum Single)1315defm VSUMWSX : RVF1m<"vsum.w.sx", 0xea, V64, VM>;1316let cx2 = 1 in defm VSUMWZX : RVF1m<"vsum.w.zx", 0xea, V64, VM>;1317 1318// Section 8.14.2 - VSUMX (Vector Sum)1319defm VSUML : RVF1m<"vsum.l", 0xaa, V64, VM>;1320 1321// Section 8.14.3 - VFSUM (Vector Floating Sum)1322defm VFSUMD : RVF1m<"vfsum.d", 0xec, V64, VM>;1323let cx = 1 in defm VFSUMS : RVF1m<"vfsum.s", 0xec, V64, VM>;1324 1325// Section 8.14.4 - VMAXS (Vector Maximum/Minimum Single)1326let cx2 = 0 in defm VRMAXSWFSTSX : RVF1m<"vrmaxs.w.fst.sx", 0xbb, V64, VM>;1327let cx2 = 1 in defm VRMAXSWFSTZX : RVF1m<"vrmaxs.w.fst.zx", 0xbb, V64, VM>;1328let cs = 1 in {1329 let cx2 = 0 in1330 defm VRMAXSWLSTSX : RVF1m<"vrmaxs.w.lst.sx", 0xbb, V64, VM>;1331 let cx2 = 1 in1332 defm VRMAXSWLSTZX : RVF1m<"vrmaxs.w.lst.zx", 0xbb, V64, VM>;1333}1334let cs2 = 1 in {1335 let cx2 = 0 in1336 defm VRMINSWFSTSX : RVF1m<"vrmins.w.fst.sx", 0xbb, V64, VM>;1337 let cx2 = 1 in1338 defm VRMINSWFSTZX : RVF1m<"vrmins.w.fst.zx", 0xbb, V64, VM>;1339 let cs = 1 in {1340 let cx2 = 0 in1341 defm VRMINSWLSTSX : RVF1m<"vrmins.w.lst.sx", 0xbb, V64, VM>;1342 let cx2 = 1 in1343 defm VRMINSWLSTZX : RVF1m<"vrmins.w.lst.zx", 0xbb, V64, VM>;1344 }1345}1346 1347// Section 8.14.5 - VMAXX (Vector Maximum/Minimum)1348let cs = 0 in defm VRMAXSLFST : RVF1m<"vrmaxs.l.fst", 0xab, V64, VM>;1349let cs = 1 in defm VRMAXSLLST : RVF1m<"vrmaxs.l.lst", 0xab, V64, VM>;1350let cs2 = 1 in {1351 let cs = 0 in defm VRMINSLFST : RVF1m<"vrmins.l.fst", 0xab, V64, VM>;1352 let cs = 1 in defm VRMINSLLST : RVF1m<"vrmins.l.lst", 0xab, V64, VM>;1353}1354 1355// Section 8.14.6 - VFMAX (Vector Floating Maximum/Minimum)1356let cs = 0 in defm VFRMAXDFST : RVF1m<"vfrmax.d.fst", 0xad, V64, VM>;1357let cs = 1 in defm VFRMAXDLST : RVF1m<"vfrmax.d.lst", 0xad, V64, VM>;1358let cs2 = 1 in {1359 let cs = 0 in defm VFRMINDFST : RVF1m<"vfrmin.d.fst", 0xad, V64, VM>;1360 let cs = 1 in defm VFRMINDLST : RVF1m<"vfrmin.d.lst", 0xad, V64, VM>;1361}1362let cx = 1 in {1363 let cs = 0 in defm VFRMAXSFST : RVF1m<"vfrmax.s.fst", 0xad, V64, VM>;1364 let cs = 1 in defm VFRMAXSLST : RVF1m<"vfrmax.s.lst", 0xad, V64, VM>;1365 let cs2 = 1 in {1366 let cs = 0 in defm VFRMINSFST : RVF1m<"vfrmin.s.fst", 0xad, V64, VM>;1367 let cs = 1 in defm VFRMINSLST : RVF1m<"vfrmin.s.lst", 0xad, V64, VM>;1368 }1369}1370 1371// Section 8.14.7 - VRAND (Vector Reduction And)1372defm VRAND : RVF1m<"vrand", 0x88, V64, VM>;1373 1374// Section 8.14.8 - VROR (Vector Reduction Or)1375defm VROR : RVF1m<"vror", 0x98, V64, VM>;1376 1377// Section 8.14.9 - VRXOR (Vector Reduction Exclusive Or)1378defm VRXOR : RVF1m<"vrxor", 0x89, V64, VM>;1379 1380//-----------------------------------------------------------------------------1381// Section 8.15 - Vector Iterative Operation Instructions1382//-----------------------------------------------------------------------------1383 1384// Section 8.15.1 - VFIA (Vector Floating Iteration Add)1385let cx = 0 in defm VFIAD : RVI2m<"vfia.d", 0xce, V64, I64>;1386let cx = 1 in defm VFIAS : RVI2m<"vfia.s", 0xce, V64, F32>;1387 1388// Section 8.15.2 - VFIS (Vector Floating Iteration Subtract)1389let cx = 0 in defm VFISD : RVI2m<"vfis.d", 0xde, V64, I64>;1390let cx = 1 in defm VFISS : RVI2m<"vfis.s", 0xde, V64, F32>;1391 1392// Section 8.15.3 - VFIM (Vector Floating Iteration Multiply)1393let cx = 0 in defm VFIMD : RVI2m<"vfim.d", 0xcf, V64, I64>;1394let cx = 1 in defm VFIMS : RVI2m<"vfim.s", 0xcf, V64, F32>;1395 1396// Section 8.15.4 - VFIAM (Vector Floating Iteration Add and Multiply)1397let cx = 0 in defm VFIAMD : RVI3m<"vfiam.d", 0xee, V64, I64>;1398let cx = 1 in defm VFIAMS : RVI3m<"vfiam.s", 0xee, V64, F32>;1399 1400// Section 8.15.5 - VFISM (Vector Floating Iteration Subtract and Multiply)1401let cx = 0 in defm VFISMD : RVI3m<"vfism.d", 0xfe, V64, I64>;1402let cx = 1 in defm VFISMS : RVI3m<"vfism.s", 0xfe, V64, F32>;1403 1404// Section 8.15.6 - VFIMA (Vector Floating Iteration Multiply and Add)1405let cx = 0 in defm VFIMAD : RVI3m<"vfima.d", 0xef, V64, I64>;1406let cx = 1 in defm VFIMAS : RVI3m<"vfima.s", 0xef, V64, F32>;1407 1408// Section 8.15.7 - VFIMS (Vector Floating Iteration Multiply and Subtract)1409let cx = 0 in defm VFIMSD : RVI3m<"vfims.d", 0xff, V64, I64>;1410let cx = 1 in defm VFIMSS : RVI3m<"vfims.s", 0xff, V64, F32>;1411 1412//-----------------------------------------------------------------------------1413// Section 8.16 - Vector Merger Operation Instructions1414//-----------------------------------------------------------------------------1415 1416// Section 8.16.1 - VMRG (Vector Merge)1417let cx = 0 in defm VMRG : RVm<"vmrg", 0xd6, V64, I64, VM>;1418// FIXME: vmrg.w should be called as pvmrg, but following assembly manual.1419let cx = 1 in defm VMRGW : RVm<"vmrg.w", 0xd6, V64, I64, VM512>;1420def : MnemonicAlias<"vmrg.l", "vmrg">;1421 1422// Section 8.16.2 - VSHF (Vector Shuffle)1423defm VSHF : RVSHFm<"vshf", 0xbc, V64>;1424 1425// Section 8.16.3 - VCP (Vector Compress)1426defm VCP : RV1m<"vcp", 0x8d, V64, VM>;1427 1428// Section 8.16.4 - VEX (Vector Expand)1429defm VEX : RV1m<"vex", 0x9d, V64, VM>;1430 1431//-----------------------------------------------------------------------------1432// Section 8.17 - Vector Mask Operation Instructions1433//-----------------------------------------------------------------------------1434 1435// Section 8.17.1 - VFMK (Vector Form Mask)1436defm VFMKL : RVMKm<"vfmk.l.", 0xb4, V64, VM>;1437def : MnemonicAlias<"vfmk.l", "vfmk.l.at">;1438 1439// Section 8.17.2 - VFMS (Vector Form Mask Single)1440defm VFMKW : RVMKm<"vfmk.w.", 0xb5, V64, VM>;1441let isCodeGenOnly = 1 in defm PVFMKWLO : RVMKm<"vfmk.w.", 0xb5, V64, VM>;1442let cx = 1 in defm PVFMKWUP : RVMKm<"pvfmk.w.up.", 0xb5, V64, VM>;1443def : MnemonicAlias<"vfmk.w", "vfmk.w.at">;1444def : MnemonicAlias<"pvfmk.w.up", "pvfmk.w.up.at">;1445def : MnemonicAlias<"pvfmk.w.lo", "vfmk.w.at">;1446foreach CC = [ "af", "gt", "lt", "ne", "eq", "ge", "le", "at" ] in {1447 def : MnemonicAlias<"pvfmk.w.lo."#CC, "vfmk.w."#CC>;1448}1449 1450// Section 8.17.3 - VFMF (Vector Form Mask Floating Point)1451defm VFMKD : RVMKm<"vfmk.d.", 0xb6, V64, VM>;1452let cx2 = 1 in defm PVFMKSLO : RVMKm<"pvfmk.s.lo.", 0xb6, V64, VM>;1453let cx = 1 in {1454 defm PVFMKSUP : RVMKm<"pvfmk.s.up.", 0xb6, V64, VM>;1455 let isCodeGenOnly = 1 in defm VFMKS : RVMKm<"vfmk.s.", 0xb6, V64, VM>;1456}1457def : MnemonicAlias<"vfmk.d", "vfmk.d.at">;1458def : MnemonicAlias<"pvfmk.s.lo", "pvfmk.s.lo.at">;1459def : MnemonicAlias<"pvfmk.s.up", "pvfmk.s.up.at">;1460def : MnemonicAlias<"vfmk.s", "pvfmk.s.up.at">;1461foreach CC = [ "af", "gt", "lt", "ne", "eq", "ge", "le", "at", "num", "nan",1462 "gtnan", "ltnan", "nenan", "eqnan", "genan", "lenan" ] in {1463 def : MnemonicAlias<"vfmk.s."#CC, "pvfmk.s.up."#CC>;1464}1465 1466// Section 8.17.4 - ANDM (And VM)1467defm ANDM : RVM2m<"andm", 0x84, VM>;1468 1469// Section 8.17.5 - ORM (Or VM)1470defm ORM : RVM2m<"orm", 0x85, VM>;1471 1472// Section 8.17.6 - XORM (Exclusive Or VM)1473defm XORM : RVM2m<"xorm", 0x86, VM>;1474 1475// Section 8.17.7 - EQVM (Equivalence VM)1476defm EQVM : RVM2m<"eqvm", 0x87, VM>;1477 1478// Section 8.17.8 - NNDM (Negate And VM)1479defm NNDM : RVM2m<"nndm", 0x94, VM>;1480 1481// Section 8.17.9 - NEGM (Negate VM)1482defm NEGM : RVM1m<"negm", 0x95, VM>;1483 1484// Section 8.17.10 - PCVM (Population Count of VM)1485defm PCVM : RVMSm<"pcvm", 0xa4, VM>;1486 1487// Section 8.17.11 - LZVM (Leading Zero of VM)1488defm LZVM : RVMSm<"lzvm", 0xa5, VM>;1489 1490// Section 8.17.12 - TOVM (Trailing One of VM)1491defm TOVM : RVMSm<"tovm", 0xa6, VM>;1492 1493//-----------------------------------------------------------------------------1494// Section 8.18 - Vector Control Instructions1495//-----------------------------------------------------------------------------1496 1497// Section 8.18.1 - LVL (Load VL)1498let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VL] in {1499 def LVLr : RR<0xbf, (outs), (ins I64:$sy), "lvl $sy">;1500 let cy = 0 in def LVLi : RR<0xbf, (outs), (ins simm7:$sy), "lvl $sy">;1501}1502 1503// Section 8.18.2 - SVL (Save VL)1504let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0, Uses = [VL] in1505def SVL : RR<0x2f, (outs I64:$sx), (ins), "svl $sx">;1506 1507// Section 8.18.3 - SMVL (Save Maximum Vector Length)1508let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in1509def SMVL : RR<0x2e, (outs I64:$sx), (ins), "smvl $sx">;1510 1511// Section 8.18.4 - LVIX (Load Vector Data Index)1512let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VIX] in {1513 def LVIXr : RR<0xaf, (outs), (ins I64:$sy), "lvix $sy">;1514 let cy = 0 in def LVIXi : RR<0xaf, (outs), (ins uimm6:$sy), "lvix $sy">;1515}1516