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1//===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8/// \file9/// This file a TargetTransformInfoImplBase conforming object specific to the10/// VE target machine. It uses the target's detailed information to11/// provide more precise answers to certain TTI queries, while letting the12/// target independent and default TTI implementations handle the rest.13///14//===----------------------------------------------------------------------===//15 16#ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H17#define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H18 19#include "VE.h"20#include "VETargetMachine.h"21#include "llvm/Analysis/TargetTransformInfo.h"22#include "llvm/CodeGen/BasicTTIImpl.h"23 24static llvm::Type *getVectorElementType(llvm::Type *Ty) {25 return llvm::cast<llvm::FixedVectorType>(Ty)->getElementType();26}27 28static llvm::Type *getLaneType(llvm::Type *Ty) {29 using namespace llvm;30 if (!isa<VectorType>(Ty))31 return Ty;32 return getVectorElementType(Ty);33}34 35static bool isVectorLaneType(llvm::Type &ElemTy) {36 // check element sizes for vregs37 if (ElemTy.isIntegerTy()) {38 unsigned ScaBits = ElemTy.getScalarSizeInBits();39 return ScaBits == 1 || ScaBits == 32 || ScaBits == 64;40 }41 if (ElemTy.isPointerTy()) {42 return true;43 }44 if (ElemTy.isFloatTy() || ElemTy.isDoubleTy()) {45 return true;46 }47 return false;48}49 50namespace llvm {51 52class VETTIImpl final : public BasicTTIImplBase<VETTIImpl> {53 using BaseT = BasicTTIImplBase<VETTIImpl>;54 friend BaseT;55 56 const VESubtarget *ST;57 const VETargetLowering *TLI;58 59 const VESubtarget *getST() const { return ST; }60 const VETargetLowering *getTLI() const { return TLI; }61 62 bool enableVPU() const { return getST()->enableVPU(); }63 64 static bool isSupportedReduction(Intrinsic::ID ReductionID) {65#define VEC_VP_CASE(SUFFIX) \66 case Intrinsic::vp_reduce_##SUFFIX: \67 case Intrinsic::vector_reduce_##SUFFIX:68 69 switch (ReductionID) {70 VEC_VP_CASE(add)71 VEC_VP_CASE(and)72 VEC_VP_CASE(or)73 VEC_VP_CASE(xor)74 VEC_VP_CASE(smax)75 return true;76 77 default:78 return false;79 }80#undef VEC_VP_CASE81 }82 83public:84 explicit VETTIImpl(const VETargetMachine *TM, const Function &F)85 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),86 TLI(ST->getTargetLowering()) {}87 88 unsigned getNumberOfRegisters(unsigned ClassID) const override {89 bool VectorRegs = (ClassID == 1);90 if (VectorRegs) {91 // TODO report vregs once vector isel is stable.92 return 0;93 }94 95 return 64;96 }97 98 TypeSize99 getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override {100 switch (K) {101 case TargetTransformInfo::RGK_Scalar:102 return TypeSize::getFixed(64);103 case TargetTransformInfo::RGK_FixedWidthVector:104 // TODO report vregs once vector isel is stable.105 return TypeSize::getFixed(0);106 case TargetTransformInfo::RGK_ScalableVector:107 return TypeSize::getScalable(0);108 }109 110 llvm_unreachable("Unsupported register kind");111 }112 113 /// \returns How the target needs this vector-predicated operation to be114 /// transformed.115 TargetTransformInfo::VPLegalization116 getVPLegalizationStrategy(const VPIntrinsic &PI) const override {117 using VPLegalization = TargetTransformInfo::VPLegalization;118 return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);119 }120 121 unsigned getMinVectorRegisterBitWidth() const override {122 // TODO report vregs once vector isel is stable.123 return 0;124 }125 126 bool shouldBuildRelLookupTables() const override {127 // NEC nld doesn't support relative lookup tables. It shows following128 // errors. So, we disable it at the moment.129 // /opt/nec/ve/bin/nld: src/CMakeFiles/cxxabi_shared.dir/cxa_demangle.cpp130 // .o(.rodata+0x17b4): reloc against `.L.str.376': error 2131 // /opt/nec/ve/bin/nld: final link failed: Nonrepresentable section on132 // output133 return false;134 }135 136 // Load & Store {137 bool138 isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned /*AddressSpace*/,139 TargetTransformInfo::MaskKind /*MaskKind*/) const override {140 return isVectorLaneType(*getLaneType(DataType));141 }142 bool isLegalMaskedStore(143 Type *DataType, Align Alignment, unsigned /*AddressSpace*/,144 TargetTransformInfo::MaskKind /*MaskKind*/) const override {145 return isVectorLaneType(*getLaneType(DataType));146 }147 bool isLegalMaskedGather(Type *DataType, Align Alignment) const override {148 return isVectorLaneType(*getLaneType(DataType));149 };150 bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override {151 return isVectorLaneType(*getLaneType(DataType));152 }153 // } Load & Store154 155 bool shouldExpandReduction(const IntrinsicInst *II) const override {156 if (!enableVPU())157 return true;158 return !isSupportedReduction(II->getIntrinsicID());159 }160};161 162} // namespace llvm163 164#endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H165