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1//===-- VVPNodes.def - Lists & properties of VE Vector Predication Nodes --===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines all VVP_* SDNodes and their properties10//11//===----------------------------------------------------------------------===//12 13/// HANDLE_VP_TO_VVP(VPOPC, VVPOPC)14/// \p VPOPC is the VP_* SDNode opcode.15/// \p VVPOPC is the VVP_* SDNode opcode.16#ifndef HANDLE_VP_TO_VVP17#define HANDLE_VP_TO_VVP(VPOPC, VVPOPC)18#endif19 20/// ADD_VVP_OP(VVPNAME,SDNAME)21/// \p VVPName is a VVP SDNode operator.22/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.23#ifndef ADD_VVP_OP24#define ADD_VVP_OP(X, Y)25#endif26 27/// ADD_UNARY_VVP_OP(VVPNAME,SDNAME)28/// \p VVPName is a VVP Unary operator.29/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.30#ifndef ADD_UNARY_VVP_OP31#define ADD_UNARY_VVP_OP(VVPNAME,SDNAME) \32 ADD_VVP_OP(VVPNAME,SDNAME)33#endif34 35/// ADD_BINARY_VVP_OP(VVPNAME,SDNAME)36/// \p VVPName is a VVP Binary operator.37/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.38#ifndef ADD_BINARY_VVP_OP39#define ADD_BINARY_VVP_OP(VVPNAME,VPNAME,SDNAME) \40 ADD_VVP_OP(VVPNAME,SDNAME) \41 HANDLE_VP_TO_VVP(VPNAME, VVPNAME)42#endif43 44/// ADD_TERNARY_VVP_OP(VVPNAME,SDNAME)45/// \p VVPName is a VVP Ternary operator.46/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.47#ifndef ADD_TERNARY_VVP_OP48#define ADD_TERNARY_VVP_OP(VVPNAME,SDNAME) \49 ADD_VVP_OP(VVPNAME,SDNAME)50#endif51 52#ifndef ADD_BINARY_VVP_OP_COMPACT53#define ADD_BINARY_VVP_OP_COMPACT(NAME) \54 ADD_BINARY_VVP_OP(VVP_##NAME,VP_##NAME,NAME)55#endif56 57/// REGISTER_PACKED(OPC)58/// \p OPC The VVP opcode of the operation.59#ifndef REGISTER_PACKED60#define REGISTER_PACKED(OPC)61#endif62 63/// ADD_REDUCE_VVP_OP(OPC)64/// \p OPC The VVP opcode of the operation.65/// \p SDNAME The standard opcode of the operation.66#ifndef ADD_REDUCE_VVP_OP67#define ADD_REDUCE_VVP_OP(OPC, SDNAME) ADD_VVP_OP(OPC, SDNAME)68#endif69 70// Scalar standard ISD to perform this reduction.71#ifndef HANDLE_VVP_REDUCE_TO_SCALAR72#define HANDLE_VVP_REDUCE_TO_SCALAR(VVP_RED_ISD, REDUCE_ISD)73#endif74 75/// Reductions.76#define HELPER_REDUCTION(OPC, SCALAR_OPC) \77 ADD_REDUCE_VVP_OP(VVP_REDUCE_##OPC,VECREDUCE_##OPC) \78 HANDLE_VP_TO_VVP(VP_REDUCE_##OPC, VVP_REDUCE_##OPC) \79 HANDLE_VVP_REDUCE_TO_SCALAR(VVP_REDUCE_##OPC, SCALAR_OPC)80 81HELPER_REDUCTION(ADD, ADD)82HELPER_REDUCTION(AND, AND)83HELPER_REDUCTION(OR, OR)84HELPER_REDUCTION(XOR, XOR)85HELPER_REDUCTION(SMAX, SMAX)86 87#undef HELPER_REDUCTION88 89ADD_VVP_OP(VVP_LOAD,LOAD) HANDLE_VP_TO_VVP(VP_LOAD, VVP_LOAD) REGISTER_PACKED(VVP_LOAD)90ADD_VVP_OP(VVP_STORE,STORE) HANDLE_VP_TO_VVP(VP_STORE, VVP_STORE) REGISTER_PACKED(VVP_STORE)91 92ADD_VVP_OP(VVP_GATHER, MGATHER) HANDLE_VP_TO_VVP(VP_GATHER, VVP_GATHER)93ADD_VVP_OP(VVP_SCATTER, MSCATTER) HANDLE_VP_TO_VVP(VP_SCATTER, VVP_SCATTER)94 95// Integer arithmetic.96ADD_BINARY_VVP_OP_COMPACT(ADD) REGISTER_PACKED(VVP_ADD)97ADD_BINARY_VVP_OP_COMPACT(SUB) REGISTER_PACKED(VVP_SUB)98ADD_BINARY_VVP_OP_COMPACT(MUL)99ADD_BINARY_VVP_OP_COMPACT(UDIV)100ADD_BINARY_VVP_OP_COMPACT(SDIV)101 102ADD_BINARY_VVP_OP(VVP_SRA,VP_SRA,SRA) REGISTER_PACKED(VVP_SRA)103ADD_BINARY_VVP_OP(VVP_SRL,VP_SRL,SRL) REGISTER_PACKED(VVP_SRL)104ADD_BINARY_VVP_OP_COMPACT(SHL) REGISTER_PACKED(VVP_SHL)105 106ADD_BINARY_VVP_OP_COMPACT(AND) REGISTER_PACKED(VVP_AND)107ADD_BINARY_VVP_OP_COMPACT(OR) REGISTER_PACKED(VVP_OR)108ADD_BINARY_VVP_OP_COMPACT(XOR) REGISTER_PACKED(VVP_XOR)109 110// FP arithmetic.111ADD_UNARY_VVP_OP(VVP_FNEG, FNEG) HANDLE_VP_TO_VVP(VP_FNEG, VVP_FNEG) REGISTER_PACKED(VVP_FNEG)112ADD_BINARY_VVP_OP_COMPACT(FADD) REGISTER_PACKED(VVP_FADD)113ADD_BINARY_VVP_OP_COMPACT(FSUB) REGISTER_PACKED(VVP_FSUB)114ADD_BINARY_VVP_OP_COMPACT(FMUL) REGISTER_PACKED(VVP_FMUL)115ADD_BINARY_VVP_OP_COMPACT(FDIV)116 117ADD_TERNARY_VVP_OP(VVP_FFMA,FMA) HANDLE_VP_TO_VVP(VP_FMA, VVP_FFMA) REGISTER_PACKED(VVP_FFMA)118 119ADD_VVP_OP(VVP_SETCC, SETCC)120 121// Shuffles.122ADD_VVP_OP(VVP_SELECT,VSELECT) REGISTER_PACKED(VVP_SELECT)123HANDLE_VP_TO_VVP(VP_SELECT, VVP_SELECT)124HANDLE_VP_TO_VVP(VP_MERGE, VVP_SELECT)125 126 127#undef ADD_BINARY_VVP_OP128#undef ADD_TERNARY_VVP_OP129#undef ADD_UNARY_VVP_OP130#undef ADD_BINARY_VVP_OP_COMPACT131#undef ADD_REDUCE_VVP_OP132#undef ADD_VVP_OP133#undef HANDLE_VP_TO_VVP134#undef HANDLE_VVP_REDUCE_TO_SCALAR135#undef REGISTER_PACKED136