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1// WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// WebAssembly Memory operand code-gen constructs.11///12//===----------------------------------------------------------------------===//13 14// TODO:15// - WebAssemblyTargetLowering having to do with atomics16// - Each has optional alignment.17 18// WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i1619// local types. These memory-only types instead zero- or sign-extend into local20// types when loading, and truncate when storing.21 22// Address Operands23 24// These patterns match the static (offset) and dynamic (address stack operand)25// operands for loads and stores, based on a combination of target global26// addresses and constants.27// For example,28// (load (add tga, x)) -> load offset=tga, addr=x29// (store v, tga) -> store v, offset=tga, addr=030// (load (add const, x)) -> load offset=const, addr=x31// (store v, const) -> store v, offset=const, addr=032// (load x) -> load offset=0, addr=x33def AddrOps32 : ComplexPattern<i32, 2, "SelectAddrOperands32">;34def AddrOps64 : ComplexPattern<i64, 2, "SelectAddrOperands64">;35 36// Defines atomic and non-atomic loads, regular and extending.37multiclass WebAssemblyLoad<WebAssemblyRegClass rc, string Name, int Opcode,38 list<Predicate> reqs = []> {39 let mayLoad = 1, UseNamedOperandTable = 1 in {40 defm "_A32": I<(outs rc:$dst),41 (ins P2Align:$p2align, offset32_op:$off, I32:$addr),42 (outs), (ins P2Align:$p2align, offset32_op:$off),43 [], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"),44 !strconcat(Name, "\t${off}${p2align}"), Opcode, false>,45 Requires<reqs>;46 defm "_A64": I<(outs rc:$dst),47 (ins P2Align:$p2align, offset64_op:$off, I64:$addr),48 (outs), (ins P2Align:$p2align, offset64_op:$off),49 [], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"),50 !strconcat(Name, "\t${off}${p2align}"), Opcode, true>,51 Requires<reqs>;52 }53}54 55// Basic load.56// FIXME: When we can break syntax compatibility, reorder the fields in the57// asmstrings to match the binary encoding.58defm LOAD_I32 : WebAssemblyLoad<I32, "i32.load", 0x28, []>;59defm LOAD_I64 : WebAssemblyLoad<I64, "i64.load", 0x29, []>;60defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a, []>;61defm LOAD_F64 : WebAssemblyLoad<F64, "f64.load", 0x2b, []>;62 63// Extending load.64defm LOAD8_S_I32 : WebAssemblyLoad<I32, "i32.load8_s", 0x2c, []>;65defm LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.load8_u", 0x2d, []>;66defm LOAD16_S_I32 : WebAssemblyLoad<I32, "i32.load16_s", 0x2e, []>;67defm LOAD16_U_I32 : WebAssemblyLoad<I32, "i32.load16_u", 0x2f, []>;68defm LOAD8_S_I64 : WebAssemblyLoad<I64, "i64.load8_s", 0x30, []>;69defm LOAD8_U_I64 : WebAssemblyLoad<I64, "i64.load8_u", 0x31, []>;70defm LOAD16_S_I64 : WebAssemblyLoad<I64, "i64.load16_s", 0x32, []>;71defm LOAD16_U_I64 : WebAssemblyLoad<I64, "i64.load16_u", 0x33, []>;72defm LOAD32_S_I64 : WebAssemblyLoad<I64, "i64.load32_s", 0x34, []>;73defm LOAD32_U_I64 : WebAssemblyLoad<I64, "i64.load32_u", 0x35, []>;74 75// Half-precision load.76defm LOAD_F16_F32 :77 WebAssemblyLoad<F32, "f32.load_f16", 0xfc30, [HasFP16]>;78 79// Pattern matching80 81multiclass LoadPat<ValueType ty, SDPatternOperator kind, string Name> {82 def : Pat<(ty (kind (AddrOps32 offset32_op:$offset, I32:$addr))),83 (!cast<NI>(Name # "_A32") 0,84 offset32_op:$offset,85 I32:$addr)>,86 Requires<[HasAddr32]>;87 88 def : Pat<(ty (kind (AddrOps64 offset64_op:$offset, I64:$addr))),89 (!cast<NI>(Name # "_A64") 0,90 offset64_op:$offset,91 I64:$addr)>,92 Requires<[HasAddr64]>;93}94 95defm : LoadPat<i32, load, "LOAD_I32">;96defm : LoadPat<i64, load, "LOAD_I64">;97defm : LoadPat<f32, load, "LOAD_F32">;98defm : LoadPat<f64, load, "LOAD_F64">;99 100defm : LoadPat<i32, sextloadi8, "LOAD8_S_I32">;101defm : LoadPat<i32, sextloadi16, "LOAD16_S_I32">;102defm : LoadPat<i64, sextloadi8, "LOAD8_S_I64">;103defm : LoadPat<i64, sextloadi16, "LOAD16_S_I64">;104defm : LoadPat<i64, sextloadi32, "LOAD32_S_I64">;105 106defm : LoadPat<i32, zextloadi8, "LOAD8_U_I32">;107defm : LoadPat<i32, zextloadi16, "LOAD16_U_I32">;108defm : LoadPat<i64, zextloadi8, "LOAD8_U_I64">;109defm : LoadPat<i64, zextloadi16, "LOAD16_U_I64">;110defm : LoadPat<i64, zextloadi32, "LOAD32_U_I64">;111 112defm : LoadPat<i32, extloadi8, "LOAD8_U_I32">;113defm : LoadPat<i32, extloadi16, "LOAD16_U_I32">;114defm : LoadPat<i64, extloadi8, "LOAD8_U_I64">;115defm : LoadPat<i64, extloadi16, "LOAD16_U_I64">;116defm : LoadPat<i64, extloadi32, "LOAD32_U_I64">;117 118defm : LoadPat<f32, int_wasm_loadf16_f32, "LOAD_F16_F32">;119 120// Defines atomic and non-atomic stores, regular and truncating121multiclass WebAssemblyStore<WebAssemblyRegClass rc, string Name, int Opcode,122 list<Predicate> reqs = []> {123 let mayStore = 1, UseNamedOperandTable = 1 in124 defm "_A32" : I<(outs),125 (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),126 (outs),127 (ins P2Align:$p2align, offset32_op:$off), [],128 !strconcat(Name, "\t${off}(${addr})${p2align}, $val"),129 !strconcat(Name, "\t${off}${p2align}"), Opcode, false>,130 Requires<reqs>;131 let mayStore = 1, UseNamedOperandTable = 1 in132 defm "_A64" : I<(outs),133 (ins P2Align:$p2align, offset64_op:$off, I64:$addr, rc:$val),134 (outs),135 (ins P2Align:$p2align, offset64_op:$off), [],136 !strconcat(Name, "\t${off}(${addr})${p2align}, $val"),137 !strconcat(Name, "\t${off}${p2align}"), Opcode, true>,138 Requires<reqs>;139}140 141// Basic store.142// Note: WebAssembly inverts SelectionDAG's usual operand order.143defm STORE_I32 : WebAssemblyStore<I32, "i32.store", 0x36>;144defm STORE_I64 : WebAssemblyStore<I64, "i64.store", 0x37>;145defm STORE_F32 : WebAssemblyStore<F32, "f32.store", 0x38>;146defm STORE_F64 : WebAssemblyStore<F64, "f64.store", 0x39>;147 148multiclass StorePat<ValueType ty, SDPatternOperator kind, string Name> {149 def : Pat<(kind ty:$val, (AddrOps32 offset32_op:$offset, I32:$addr)),150 (!cast<NI>(Name # "_A32") 0,151 offset32_op:$offset,152 I32:$addr,153 ty:$val)>,154 Requires<[HasAddr32]>;155 def : Pat<(kind ty:$val, (AddrOps64 offset64_op:$offset, I64:$addr)),156 (!cast<NI>(Name # "_A64") 0,157 offset64_op:$offset,158 I64:$addr,159 ty:$val)>,160 Requires<[HasAddr64]>;161}162 163defm : StorePat<i32, store, "STORE_I32">;164defm : StorePat<i64, store, "STORE_I64">;165defm : StorePat<f32, store, "STORE_F32">;166defm : StorePat<f64, store, "STORE_F64">;167 168// Truncating store.169defm STORE8_I32 : WebAssemblyStore<I32, "i32.store8", 0x3a>;170defm STORE16_I32 : WebAssemblyStore<I32, "i32.store16", 0x3b>;171defm STORE8_I64 : WebAssemblyStore<I64, "i64.store8", 0x3c>;172defm STORE16_I64 : WebAssemblyStore<I64, "i64.store16", 0x3d>;173defm STORE32_I64 : WebAssemblyStore<I64, "i64.store32", 0x3e>;174 175// Half-precision store.176defm STORE_F16_F32 :177 WebAssemblyStore<F32, "f32.store_f16", 0xfc31, [HasFP16]>;178 179defm : StorePat<i32, truncstorei8, "STORE8_I32">;180defm : StorePat<i32, truncstorei16, "STORE16_I32">;181defm : StorePat<i64, truncstorei8, "STORE8_I64">;182defm : StorePat<i64, truncstorei16, "STORE16_I64">;183defm : StorePat<i64, truncstorei32, "STORE32_I64">;184 185defm : StorePat<f32, int_wasm_storef16_f32, "STORE_F16_F32">;186 187multiclass MemoryOps<WebAssemblyRegClass rc, string B> {188// Current memory size.189defm MEMORY_SIZE_A#B : I<(outs rc:$dst), (ins i32imm:$flags),190 (outs), (ins i32imm:$flags),191 [(set rc:$dst,192 (int_wasm_memory_size (i32 imm:$flags)))],193 "memory.size\t$dst, $flags", "memory.size\t$flags",194 0x3f>;195 196// Grow memory.197defm MEMORY_GROW_A#B : I<(outs rc:$dst), (ins i32imm:$flags, rc:$delta),198 (outs), (ins i32imm:$flags),199 [(set rc:$dst,200 (int_wasm_memory_grow (i32 imm:$flags),201 rc:$delta))],202 "memory.grow\t$dst, $flags, $delta",203 "memory.grow\t$flags", 0x40>;204}205 206defm : MemoryOps<I32, "32">;207defm : MemoryOps<I64, "64">;208