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1//WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*-2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// This file describes the WebAssembly register classes and some nominal11/// physical registers.12///13//===----------------------------------------------------------------------===//14 15class WebAssemblyReg<string n> : Register<n> {16 let Namespace = "WebAssembly";17}18 19class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>20 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;21 22//===----------------------------------------------------------------------===//23// Registers24//===----------------------------------------------------------------------===//25 26// Special registers used as the frame and stack pointer.27//28// WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same29// application, which requires separate width FP and SP.30def FP32 : WebAssemblyReg<"%FP32">;31def FP64 : WebAssemblyReg<"%FP64">;32def SP32 : WebAssemblyReg<"%SP32">;33def SP64 : WebAssemblyReg<"%SP64">;34 35// The register allocation framework requires register classes have at least36// one register, so we define a few for the integer / floating point register37// classes since we otherwise don't need a physical register in those classes.38// These are also used a "types" in the generated assembly matcher.39def I32_0 : WebAssemblyReg<"%i32.0">;40def I64_0 : WebAssemblyReg<"%i64.0">;41def F32_0 : WebAssemblyReg<"%f32.0">;42def F64_0 : WebAssemblyReg<"%f64.0">;43 44def V128_0: WebAssemblyReg<"%v128">;45 46def FUNCREF_0 : WebAssemblyReg<"%funcref.0">;47def EXTERNREF_0 : WebAssemblyReg<"%externref.0">;48def EXNREF_0 : WebAssemblyReg<"%exnref.0">;49 50// The value stack "register". This is an opaque entity which serves to order51// uses and defs that must remain in LIFO order.52def VALUE_STACK : WebAssemblyReg<"STACK">;53 54// The incoming arguments "register". This is an opaque entity which serves to55// order the ARGUMENT instructions that are emulating live-in registers and56// must not be scheduled below other instructions.57def ARGUMENTS : WebAssemblyReg<"ARGUMENTS">;58 59//===----------------------------------------------------------------------===//60// Register classes61//===----------------------------------------------------------------------===//62 63def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;64def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;65def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;66def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;67def V128 : WebAssemblyRegClass<[v2i64, v4i32, v16i8, v8i16,68 v8f16, v4f32, v2f64],69 128, (add V128_0)>;70def FUNCREF : WebAssemblyRegClass<[funcref], 0, (add FUNCREF_0)>;71def EXTERNREF : WebAssemblyRegClass<[externref], 0, (add EXTERNREF_0)>;72def EXNREF : WebAssemblyRegClass<[exnref], 0, (add EXNREF_0)>;73