84 lines · cpp
1//===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// \file10/// This file implements the WebAssembly-specific subclass of11/// TargetSubtarget.12///13//===----------------------------------------------------------------------===//14 15#include "WebAssemblySubtarget.h"16#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"17#include "WebAssemblyInstrInfo.h"18#include "llvm/MC/TargetRegistry.h"19using namespace llvm;20 21#define DEBUG_TYPE "wasm-subtarget"22 23#define GET_SUBTARGETINFO_CTOR24#define GET_SUBTARGETINFO_TARGET_DESC25#include "WebAssemblyGenSubtargetInfo.inc"26 27WebAssemblySubtarget &28WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,29 StringRef FS) {30 // Determine default and user-specified characteristics31 LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");32 33 if (CPU.empty())34 CPU = "generic";35 36 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);37 38 FeatureBitset Bits = getFeatureBits();39 40 // bulk-memory implies bulk-memory-opt41 if (HasBulkMemory) {42 HasBulkMemoryOpt = true;43 Bits.set(WebAssembly::FeatureBulkMemoryOpt);44 }45 46 // gc implies reference-types47 if (HasGC) {48 HasReferenceTypes = true;49 }50 51 // reference-types implies call-indirect-overlong52 if (HasReferenceTypes) {53 HasCallIndirectOverlong = true;54 Bits.set(WebAssembly::FeatureCallIndirectOverlong);55 }56 57 // In case we changed any bits, update `MCSubtargetInfo`'s `FeatureBitset`.58 setFeatureBits(Bits);59 60 return *this;61}62 63WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,64 const std::string &CPU,65 const std::string &FS,66 const TargetMachine &TM)67 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),68 TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),69 TLInfo(TM, *this) {}70 71bool WebAssemblySubtarget::enableAtomicExpand() const {72 // If atomics are disabled, atomic ops are lowered instead of expanded73 return hasAtomics();74}75 76bool WebAssemblySubtarget::enableMachineScheduler() const {77 // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and78 // enableMachineSchedDefaultSched overridden, it appears to have an overall79 // negative effect for the kinds of register optimizations we're doing.80 return false;81}82 83bool WebAssemblySubtarget::useAA() const { return true; }84