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1//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file is part of the X86 Disassembler.10// It contains the public interface of the instruction decoder.11// Documentation for the disassembler can be found in X86Disassembler.h.12//13//===----------------------------------------------------------------------===//14 15#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H16#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H17 18#include "llvm/ADT/ArrayRef.h"19#include "llvm/Support/X86DisassemblerDecoderCommon.h"20 21namespace llvm {22namespace X86Disassembler {23// Helper macros24#define bitFromOffset0(val) ((val) & 0x1)25#define bitFromOffset1(val) (((val) >> 1) & 0x1)26#define bitFromOffset2(val) (((val) >> 2) & 0x1)27#define bitFromOffset3(val) (((val) >> 3) & 0x1)28#define bitFromOffset4(val) (((val) >> 4) & 0x1)29#define bitFromOffset5(val) (((val) >> 5) & 0x1)30#define bitFromOffset6(val) (((val) >> 6) & 0x1)31#define bitFromOffset7(val) (((val) >> 7) & 0x1)32#define twoBitsFromOffset0(val) ((val) & 0x3)33#define twoBitsFromOffset6(val) (((val) >> 6) & 0x3)34#define threeBitsFromOffset0(val) ((val) & 0x7)35#define threeBitsFromOffset3(val) (((val) >> 3) & 0x7)36#define fourBitsFromOffset0(val) ((val) & 0xf)37#define fourBitsFromOffset3(val) (((val) >> 3) & 0xf)38#define fiveBitsFromOffset0(val) ((val) & 0x1f)39#define invertedBitFromOffset2(val) (((~(val)) >> 2) & 0x1)40#define invertedBitFromOffset3(val) (((~(val)) >> 3) & 0x1)41#define invertedBitFromOffset4(val) (((~(val)) >> 4) & 0x1)42#define invertedBitFromOffset5(val) (((~(val)) >> 5) & 0x1)43#define invertedBitFromOffset6(val) (((~(val)) >> 6) & 0x1)44#define invertedBitFromOffset7(val) (((~(val)) >> 7) & 0x1)45#define invertedFourBitsFromOffset3(val) (((~(val)) >> 3) & 0xf)46// MOD/RM47#define modFromModRM(modRM) twoBitsFromOffset6(modRM)48#define regFromModRM(modRM) threeBitsFromOffset3(modRM)49#define rmFromModRM(modRM) threeBitsFromOffset0(modRM)50// SIB51#define scaleFromSIB(sib) twoBitsFromOffset6(sib)52#define indexFromSIB(sib) threeBitsFromOffset3(sib)53#define baseFromSIB(sib) threeBitsFromOffset0(sib)54// REX55#define wFromREX(rex) bitFromOffset3(rex)56#define rFromREX(rex) bitFromOffset2(rex)57#define xFromREX(rex) bitFromOffset1(rex)58#define bFromREX(rex) bitFromOffset0(rex)59// REX260#define mFromREX2(rex2) bitFromOffset7(rex2)61#define r2FromREX2(rex2) bitFromOffset6(rex2)62#define x2FromREX2(rex2) bitFromOffset5(rex2)63#define b2FromREX2(rex2) bitFromOffset4(rex2)64#define wFromREX2(rex2) bitFromOffset3(rex2)65#define rFromREX2(rex2) bitFromOffset2(rex2)66#define xFromREX2(rex2) bitFromOffset1(rex2)67#define bFromREX2(rex2) bitFromOffset0(rex2)68// XOP69#define rFromXOP2of3(xop) invertedBitFromOffset7(xop)70#define xFromXOP2of3(xop) invertedBitFromOffset6(xop)71#define bFromXOP2of3(xop) invertedBitFromOffset5(xop)72#define mmmmmFromXOP2of3(xop) fiveBitsFromOffset0(xop)73#define wFromXOP3of3(xop) bitFromOffset7(xop)74#define vvvvFromXOP3of3(xop) invertedFourBitsFromOffset3(xop)75#define lFromXOP3of3(xop) bitFromOffset2(xop)76#define ppFromXOP3of3(xop) twoBitsFromOffset0(xop)77// VEX278#define rFromVEX2of2(vex) invertedBitFromOffset7(vex)79#define vvvvFromVEX2of2(vex) invertedFourBitsFromOffset3(vex)80#define lFromVEX2of2(vex) bitFromOffset2(vex)81#define ppFromVEX2of2(vex) twoBitsFromOffset0(vex)82// VEX383#define rFromVEX2of3(vex) invertedBitFromOffset7(vex)84#define xFromVEX2of3(vex) invertedBitFromOffset6(vex)85#define bFromVEX2of3(vex) invertedBitFromOffset5(vex)86#define mmmmmFromVEX2of3(vex) fiveBitsFromOffset0(vex)87#define wFromVEX3of3(vex) bitFromOffset7(vex)88#define vvvvFromVEX3of3(vex) invertedFourBitsFromOffset3(vex)89#define lFromVEX3of3(vex) bitFromOffset2(vex)90#define ppFromVEX3of3(vex) twoBitsFromOffset0(vex)91// EVEX92#define rFromEVEX2of4(evex) invertedBitFromOffset7(evex)93#define xFromEVEX2of4(evex) invertedBitFromOffset6(evex)94#define bFromEVEX2of4(evex) invertedBitFromOffset5(evex)95#define r2FromEVEX2of4(evex) invertedBitFromOffset4(evex)96#define b2FromEVEX2of4(evex) bitFromOffset3(evex)97#define mmmFromEVEX2of4(evex) threeBitsFromOffset0(evex)98#define wFromEVEX3of4(evex) bitFromOffset7(evex)99#define vvvvFromEVEX3of4(evex) invertedFourBitsFromOffset3(evex)100#define uFromEVEX3of4(evex) invertedBitFromOffset2(evex)101#define ppFromEVEX3of4(evex) twoBitsFromOffset0(evex)102#define oszcFromEVEX3of4(evex) fourBitsFromOffset3(evex)103#define zFromEVEX4of4(evex) bitFromOffset7(evex)104#define l2FromEVEX4of4(evex) bitFromOffset6(evex)105#define lFromEVEX4of4(evex) bitFromOffset5(evex)106#define bFromEVEX4of4(evex) bitFromOffset4(evex)107#define v2FromEVEX4of4(evex) invertedBitFromOffset3(evex)108#define aaaFromEVEX4of4(evex) threeBitsFromOffset0(evex)109#define nfFromEVEX4of4(evex) bitFromOffset2(evex)110#define scFromEVEX4of4(evex) fourBitsFromOffset0(evex)111 112// These enums represent Intel registers for use by the decoder.113#define REGS_8BIT \114 ENTRY(AL) \115 ENTRY(CL) \116 ENTRY(DL) \117 ENTRY(BL) \118 ENTRY(AH) \119 ENTRY(CH) \120 ENTRY(DH) \121 ENTRY(BH) \122 ENTRY(R8B) \123 ENTRY(R9B) \124 ENTRY(R10B) \125 ENTRY(R11B) \126 ENTRY(R12B) \127 ENTRY(R13B) \128 ENTRY(R14B) \129 ENTRY(R15B) \130 ENTRY(R16B) \131 ENTRY(R17B) \132 ENTRY(R18B) \133 ENTRY(R19B) \134 ENTRY(R20B) \135 ENTRY(R21B) \136 ENTRY(R22B) \137 ENTRY(R23B) \138 ENTRY(R24B) \139 ENTRY(R25B) \140 ENTRY(R26B) \141 ENTRY(R27B) \142 ENTRY(R28B) \143 ENTRY(R29B) \144 ENTRY(R30B) \145 ENTRY(R31B) \146 ENTRY(SPL) \147 ENTRY(BPL) \148 ENTRY(SIL) \149 ENTRY(DIL)150 151#define EA_BASES_16BIT \152 ENTRY(BX_SI) \153 ENTRY(BX_DI) \154 ENTRY(BP_SI) \155 ENTRY(BP_DI) \156 ENTRY(SI) \157 ENTRY(DI) \158 ENTRY(BP) \159 ENTRY(BX) \160 ENTRY(R8W) \161 ENTRY(R9W) \162 ENTRY(R10W) \163 ENTRY(R11W) \164 ENTRY(R12W) \165 ENTRY(R13W) \166 ENTRY(R14W) \167 ENTRY(R15W) \168 ENTRY(R16W) \169 ENTRY(R17W) \170 ENTRY(R18W) \171 ENTRY(R19W) \172 ENTRY(R20W) \173 ENTRY(R21W) \174 ENTRY(R22W) \175 ENTRY(R23W) \176 ENTRY(R24W) \177 ENTRY(R25W) \178 ENTRY(R26W) \179 ENTRY(R27W) \180 ENTRY(R28W) \181 ENTRY(R29W) \182 ENTRY(R30W) \183 ENTRY(R31W)184 185#define REGS_16BIT \186 ENTRY(AX) \187 ENTRY(CX) \188 ENTRY(DX) \189 ENTRY(BX) \190 ENTRY(SP) \191 ENTRY(BP) \192 ENTRY(SI) \193 ENTRY(DI) \194 ENTRY(R8W) \195 ENTRY(R9W) \196 ENTRY(R10W) \197 ENTRY(R11W) \198 ENTRY(R12W) \199 ENTRY(R13W) \200 ENTRY(R14W) \201 ENTRY(R15W) \202 ENTRY(R16W) \203 ENTRY(R17W) \204 ENTRY(R18W) \205 ENTRY(R19W) \206 ENTRY(R20W) \207 ENTRY(R21W) \208 ENTRY(R22W) \209 ENTRY(R23W) \210 ENTRY(R24W) \211 ENTRY(R25W) \212 ENTRY(R26W) \213 ENTRY(R27W) \214 ENTRY(R28W) \215 ENTRY(R29W) \216 ENTRY(R30W) \217 ENTRY(R31W)218 219#define EA_BASES_32BIT \220 ENTRY(EAX) \221 ENTRY(ECX) \222 ENTRY(EDX) \223 ENTRY(EBX) \224 ENTRY(sib) \225 ENTRY(EBP) \226 ENTRY(ESI) \227 ENTRY(EDI) \228 ENTRY(R8D) \229 ENTRY(R9D) \230 ENTRY(R10D) \231 ENTRY(R11D) \232 ENTRY(R12D) \233 ENTRY(R13D) \234 ENTRY(R14D) \235 ENTRY(R15D) \236 ENTRY(R16D) \237 ENTRY(R17D) \238 ENTRY(R18D) \239 ENTRY(R19D) \240 ENTRY(R20D) \241 ENTRY(R21D) \242 ENTRY(R22D) \243 ENTRY(R23D) \244 ENTRY(R24D) \245 ENTRY(R25D) \246 ENTRY(R26D) \247 ENTRY(R27D) \248 ENTRY(R28D) \249 ENTRY(R29D) \250 ENTRY(R30D) \251 ENTRY(R31D)252 253#define REGS_32BIT \254 ENTRY(EAX) \255 ENTRY(ECX) \256 ENTRY(EDX) \257 ENTRY(EBX) \258 ENTRY(ESP) \259 ENTRY(EBP) \260 ENTRY(ESI) \261 ENTRY(EDI) \262 ENTRY(R8D) \263 ENTRY(R9D) \264 ENTRY(R10D) \265 ENTRY(R11D) \266 ENTRY(R12D) \267 ENTRY(R13D) \268 ENTRY(R14D) \269 ENTRY(R15D) \270 ENTRY(R16D) \271 ENTRY(R17D) \272 ENTRY(R18D) \273 ENTRY(R19D) \274 ENTRY(R20D) \275 ENTRY(R21D) \276 ENTRY(R22D) \277 ENTRY(R23D) \278 ENTRY(R24D) \279 ENTRY(R25D) \280 ENTRY(R26D) \281 ENTRY(R27D) \282 ENTRY(R28D) \283 ENTRY(R29D) \284 ENTRY(R30D) \285 ENTRY(R31D)286 287#define EA_BASES_64BIT \288 ENTRY(RAX) \289 ENTRY(RCX) \290 ENTRY(RDX) \291 ENTRY(RBX) \292 ENTRY(sib64) \293 ENTRY(RBP) \294 ENTRY(RSI) \295 ENTRY(RDI) \296 ENTRY(R8) \297 ENTRY(R9) \298 ENTRY(R10) \299 ENTRY(R11) \300 ENTRY(R12) \301 ENTRY(R13) \302 ENTRY(R14) \303 ENTRY(R15) \304 ENTRY(R16) \305 ENTRY(R17) \306 ENTRY(R18) \307 ENTRY(R19) \308 ENTRY(R20) \309 ENTRY(R21) \310 ENTRY(R22) \311 ENTRY(R23) \312 ENTRY(R24) \313 ENTRY(R25) \314 ENTRY(R26) \315 ENTRY(R27) \316 ENTRY(R28) \317 ENTRY(R29) \318 ENTRY(R30) \319 ENTRY(R31)320 321#define REGS_64BIT \322 ENTRY(RAX) \323 ENTRY(RCX) \324 ENTRY(RDX) \325 ENTRY(RBX) \326 ENTRY(RSP) \327 ENTRY(RBP) \328 ENTRY(RSI) \329 ENTRY(RDI) \330 ENTRY(R8) \331 ENTRY(R9) \332 ENTRY(R10) \333 ENTRY(R11) \334 ENTRY(R12) \335 ENTRY(R13) \336 ENTRY(R14) \337 ENTRY(R15) \338 ENTRY(R16) \339 ENTRY(R17) \340 ENTRY(R18) \341 ENTRY(R19) \342 ENTRY(R20) \343 ENTRY(R21) \344 ENTRY(R22) \345 ENTRY(R23) \346 ENTRY(R24) \347 ENTRY(R25) \348 ENTRY(R26) \349 ENTRY(R27) \350 ENTRY(R28) \351 ENTRY(R29) \352 ENTRY(R30) \353 ENTRY(R31)354 355#define REGS_MMX \356 ENTRY(MM0) \357 ENTRY(MM1) \358 ENTRY(MM2) \359 ENTRY(MM3) \360 ENTRY(MM4) \361 ENTRY(MM5) \362 ENTRY(MM6) \363 ENTRY(MM7)364 365#define REGS_XMM \366 ENTRY(XMM0) \367 ENTRY(XMM1) \368 ENTRY(XMM2) \369 ENTRY(XMM3) \370 ENTRY(XMM4) \371 ENTRY(XMM5) \372 ENTRY(XMM6) \373 ENTRY(XMM7) \374 ENTRY(XMM8) \375 ENTRY(XMM9) \376 ENTRY(XMM10) \377 ENTRY(XMM11) \378 ENTRY(XMM12) \379 ENTRY(XMM13) \380 ENTRY(XMM14) \381 ENTRY(XMM15) \382 ENTRY(XMM16) \383 ENTRY(XMM17) \384 ENTRY(XMM18) \385 ENTRY(XMM19) \386 ENTRY(XMM20) \387 ENTRY(XMM21) \388 ENTRY(XMM22) \389 ENTRY(XMM23) \390 ENTRY(XMM24) \391 ENTRY(XMM25) \392 ENTRY(XMM26) \393 ENTRY(XMM27) \394 ENTRY(XMM28) \395 ENTRY(XMM29) \396 ENTRY(XMM30) \397 ENTRY(XMM31)398 399#define REGS_YMM \400 ENTRY(YMM0) \401 ENTRY(YMM1) \402 ENTRY(YMM2) \403 ENTRY(YMM3) \404 ENTRY(YMM4) \405 ENTRY(YMM5) \406 ENTRY(YMM6) \407 ENTRY(YMM7) \408 ENTRY(YMM8) \409 ENTRY(YMM9) \410 ENTRY(YMM10) \411 ENTRY(YMM11) \412 ENTRY(YMM12) \413 ENTRY(YMM13) \414 ENTRY(YMM14) \415 ENTRY(YMM15) \416 ENTRY(YMM16) \417 ENTRY(YMM17) \418 ENTRY(YMM18) \419 ENTRY(YMM19) \420 ENTRY(YMM20) \421 ENTRY(YMM21) \422 ENTRY(YMM22) \423 ENTRY(YMM23) \424 ENTRY(YMM24) \425 ENTRY(YMM25) \426 ENTRY(YMM26) \427 ENTRY(YMM27) \428 ENTRY(YMM28) \429 ENTRY(YMM29) \430 ENTRY(YMM30) \431 ENTRY(YMM31)432 433#define REGS_ZMM \434 ENTRY(ZMM0) \435 ENTRY(ZMM1) \436 ENTRY(ZMM2) \437 ENTRY(ZMM3) \438 ENTRY(ZMM4) \439 ENTRY(ZMM5) \440 ENTRY(ZMM6) \441 ENTRY(ZMM7) \442 ENTRY(ZMM8) \443 ENTRY(ZMM9) \444 ENTRY(ZMM10) \445 ENTRY(ZMM11) \446 ENTRY(ZMM12) \447 ENTRY(ZMM13) \448 ENTRY(ZMM14) \449 ENTRY(ZMM15) \450 ENTRY(ZMM16) \451 ENTRY(ZMM17) \452 ENTRY(ZMM18) \453 ENTRY(ZMM19) \454 ENTRY(ZMM20) \455 ENTRY(ZMM21) \456 ENTRY(ZMM22) \457 ENTRY(ZMM23) \458 ENTRY(ZMM24) \459 ENTRY(ZMM25) \460 ENTRY(ZMM26) \461 ENTRY(ZMM27) \462 ENTRY(ZMM28) \463 ENTRY(ZMM29) \464 ENTRY(ZMM30) \465 ENTRY(ZMM31)466 467#define REGS_MASKS \468 ENTRY(K0) \469 ENTRY(K1) \470 ENTRY(K2) \471 ENTRY(K3) \472 ENTRY(K4) \473 ENTRY(K5) \474 ENTRY(K6) \475 ENTRY(K7)476 477#define REGS_MASK_PAIRS \478 ENTRY(K0_K1) \479 ENTRY(K2_K3) \480 ENTRY(K4_K5) \481 ENTRY(K6_K7)482 483#define REGS_SEGMENT \484 ENTRY(ES) \485 ENTRY(CS) \486 ENTRY(SS) \487 ENTRY(DS) \488 ENTRY(FS) \489 ENTRY(GS)490 491#define REGS_DEBUG \492 ENTRY(DR0) \493 ENTRY(DR1) \494 ENTRY(DR2) \495 ENTRY(DR3) \496 ENTRY(DR4) \497 ENTRY(DR5) \498 ENTRY(DR6) \499 ENTRY(DR7) \500 ENTRY(DR8) \501 ENTRY(DR9) \502 ENTRY(DR10) \503 ENTRY(DR11) \504 ENTRY(DR12) \505 ENTRY(DR13) \506 ENTRY(DR14) \507 ENTRY(DR15)508 509#define REGS_CONTROL \510 ENTRY(CR0) \511 ENTRY(CR1) \512 ENTRY(CR2) \513 ENTRY(CR3) \514 ENTRY(CR4) \515 ENTRY(CR5) \516 ENTRY(CR6) \517 ENTRY(CR7) \518 ENTRY(CR8) \519 ENTRY(CR9) \520 ENTRY(CR10) \521 ENTRY(CR11) \522 ENTRY(CR12) \523 ENTRY(CR13) \524 ENTRY(CR14) \525 ENTRY(CR15)526 527#undef REGS_TMM528#define REGS_TMM \529 ENTRY(TMM0) \530 ENTRY(TMM1) \531 ENTRY(TMM2) \532 ENTRY(TMM3) \533 ENTRY(TMM4) \534 ENTRY(TMM5) \535 ENTRY(TMM6) \536 ENTRY(TMM7)537 538#define ALL_EA_BASES \539 EA_BASES_16BIT \540 EA_BASES_32BIT \541 EA_BASES_64BIT542 543#define ALL_SIB_BASES \544 REGS_32BIT \545 REGS_64BIT546 547#define ALL_REGS \548 REGS_8BIT \549 REGS_16BIT \550 REGS_32BIT \551 REGS_64BIT \552 REGS_MMX \553 REGS_XMM \554 REGS_YMM \555 REGS_ZMM \556 REGS_MASKS \557 REGS_MASK_PAIRS \558 REGS_SEGMENT \559 REGS_DEBUG \560 REGS_CONTROL \561 REGS_TMM \562 ENTRY(RIP)563 564/// All possible values of the base field for effective-address565/// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.566/// We distinguish between bases (EA_BASE_*) and registers that just happen567/// to be referred to when Mod == 0b11 (EA_REG_*).568enum EABase {569 // clang-format off570 EA_BASE_NONE,571#define ENTRY(x) EA_BASE_##x,572 ALL_EA_BASES573#undef ENTRY574#define ENTRY(x) EA_REG_##x,575 ALL_REGS576#undef ENTRY577 EA_max578 // clang-format on579};580 581/// All possible values of the SIB index field.582/// borrows entries from ALL_EA_BASES with the special case that583/// sib is synonymous with NONE.584/// Vector SIB: index can be XMM or YMM.585enum SIBIndex {586 // clang-format off587 SIB_INDEX_NONE,588#define ENTRY(x) SIB_INDEX_##x,589 ALL_EA_BASES590 REGS_XMM591 REGS_YMM592 REGS_ZMM593#undef ENTRY594 SIB_INDEX_max595 // clang-format on596};597 598/// All possible values of the SIB base field.599enum SIBBase {600 // clang-format off601 SIB_BASE_NONE,602#define ENTRY(x) SIB_BASE_##x,603 ALL_SIB_BASES604#undef ENTRY605 SIB_BASE_max606 // clang-format on607};608 609/// Possible displacement types for effective-address computations.610enum EADisplacement { EA_DISP_NONE, EA_DISP_8, EA_DISP_16, EA_DISP_32 };611 612/// All possible values of the reg field in the ModR/M byte.613// clang-format off614enum Reg {615#define ENTRY(x) MODRM_REG_##x,616 ALL_REGS617#undef ENTRY618 MODRM_REG_max619};620// clang-format on621 622/// All possible segment overrides.623enum SegmentOverride {624 SEG_OVERRIDE_NONE,625 SEG_OVERRIDE_CS,626 SEG_OVERRIDE_SS,627 SEG_OVERRIDE_DS,628 SEG_OVERRIDE_ES,629 SEG_OVERRIDE_FS,630 SEG_OVERRIDE_GS,631 SEG_OVERRIDE_max632};633 634/// Possible values for the VEX.m-mmmm field635enum VEXLeadingOpcodeByte {636 VEX_LOB_0F = 0x1,637 VEX_LOB_0F38 = 0x2,638 VEX_LOB_0F3A = 0x3,639 VEX_LOB_MAP4 = 0x4,640 VEX_LOB_MAP5 = 0x5,641 VEX_LOB_MAP6 = 0x6,642 VEX_LOB_MAP7 = 0x7643};644 645enum XOPMapSelect {646 XOP_MAP_SELECT_8 = 0x8,647 XOP_MAP_SELECT_9 = 0x9,648 XOP_MAP_SELECT_A = 0xA649};650 651/// Possible values for the VEX.pp/EVEX.pp field652enum VEXPrefixCode {653 VEX_PREFIX_NONE = 0x0,654 VEX_PREFIX_66 = 0x1,655 VEX_PREFIX_F3 = 0x2,656 VEX_PREFIX_F2 = 0x3657};658 659enum VectorExtensionType {660 TYPE_NO_VEX_XOP = 0x0,661 TYPE_VEX_2B = 0x1,662 TYPE_VEX_3B = 0x2,663 TYPE_EVEX = 0x3,664 TYPE_XOP = 0x4665};666 667/// The specification for how to extract and interpret a full instruction and668/// its operands.669struct InstructionSpecifier {670 uint16_t operands;671};672 673/// The x86 internal instruction, which is produced by the decoder.674struct InternalInstruction {675 // Opaque value passed to the reader676 llvm::ArrayRef<uint8_t> bytes;677 // The address of the next byte to read via the reader678 uint64_t readerCursor;679 680 // General instruction information681 682 // The mode to disassemble for (64-bit, protected, real)683 DisassemblerMode mode;684 // The start of the instruction, usable with the reader685 uint64_t startLocation;686 // The length of the instruction, in bytes687 size_t length;688 689 // Prefix state690 691 // The possible mandatory prefix692 uint8_t mandatoryPrefix;693 // The value of the vector extension prefix(EVEX/VEX/XOP), if present694 uint8_t vectorExtensionPrefix[4];695 // The type of the vector extension prefix696 VectorExtensionType vectorExtensionType;697 // The value of the REX2 prefix, if present698 uint8_t rex2ExtensionPrefix[2];699 // The value of the REX prefix, if present700 uint8_t rexPrefix;701 // The segment override type702 SegmentOverride segmentOverride;703 // 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease704 bool xAcquireRelease;705 706 // Address-size override707 bool hasAdSize;708 // Operand-size override709 bool hasOpSize;710 // Lock prefix711 bool hasLockPrefix;712 // The repeat prefix if any713 uint8_t repeatPrefix;714 715 // Sizes of various critical pieces of data, in bytes716 uint8_t registerSize;717 uint8_t addressSize;718 uint8_t displacementSize;719 uint8_t immediateSize;720 721 // Offsets from the start of the instruction to the pieces of data, which is722 // needed to find relocation entries for adding symbolic operands.723 uint8_t displacementOffset;724 uint8_t immediateOffset;725 726 // opcode state727 728 // The last byte of the opcode, not counting any ModR/M extension729 uint8_t opcode;730 731 // decode state732 733 // The type of opcode, used for indexing into the array of decode tables734 OpcodeType opcodeType;735 // The instruction ID, extracted from the decode table736 uint16_t instructionID;737 // The specifier for the instruction, from the instruction info table738 const InstructionSpecifier *spec;739 740 // state for additional bytes, consumed during operand decode. Pattern:741 // consumed___ indicates that the byte was already consumed and does not742 // need to be consumed again.743 744 // The VEX.vvvv field, which contains a third register operand for some AVX745 // instructions.746 Reg vvvv;747 748 // The writemask for AVX-512 instructions which is contained in EVEX.aaa749 Reg writemask;750 751 // The ModR/M byte, which contains most register operands and some portion of752 // all memory operands.753 bool consumedModRM;754 uint8_t modRM;755 756 // The SIB byte, used for more complex 32- or 64-bit memory operands757 uint8_t sib;758 759 // The displacement, used for memory operands760 int32_t displacement;761 762 // Immediates. There can be three in some cases763 uint8_t numImmediatesConsumed;764 uint8_t numImmediatesTranslated;765 uint64_t immediates[3];766 767 // A register or immediate operand encoded into the opcode768 Reg opcodeRegister;769 770 // Portions of the ModR/M byte771 772 // These fields determine the allowable values for the ModR/M fields, which773 // depend on operand and address widths.774 EABase eaRegBase;775 Reg regBase;776 777 // The Mod and R/M fields can encode a base for an effective address, or a778 // register. These are separated into two fields here.779 EABase eaBase;780 EADisplacement eaDisplacement;781 // The reg field always encodes a register782 Reg reg;783 784 // SIB state785 SIBIndex sibIndexBase;786 SIBIndex sibIndex;787 uint8_t sibScale;788 SIBBase sibBase;789 790 // Embedded rounding control.791 uint8_t RC;792 793 ArrayRef<OperandSpecifier> operands;794};795 796} // namespace X86Disassembler797} // namespace llvm798 799#endif800