83 lines · cpp
1//===------------------- X86CustomBehaviour.cpp -----------------*-C++ -* -===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8/// \file9///10/// This file implements methods from the X86CustomBehaviour class.11///12//===----------------------------------------------------------------------===//13 14#include "X86CustomBehaviour.h"15#include "MCTargetDesc/X86BaseInfo.h"16#include "TargetInfo/X86TargetInfo.h"17#include "llvm-c/Visibility.h"18#include "llvm/MC/TargetRegistry.h"19 20namespace llvm {21namespace mca {22 23void X86InstrPostProcess::setMemBarriers(Instruction &Inst, const MCInst &MCI) {24 switch (MCI.getOpcode()) {25 case X86::MFENCE:26 Inst.setLoadBarrier(true);27 Inst.setStoreBarrier(true);28 break;29 case X86::LFENCE:30 Inst.setLoadBarrier(true);31 break;32 case X86::SFENCE:33 Inst.setStoreBarrier(true);34 break;35 }36}37 38void X86InstrPostProcess::useStackEngine(Instruction &Inst, const MCInst &MCI) {39 // TODO(boomanaiden154): We currently do not handle PUSHF/POPF because we40 // have not done the necessary benchmarking to see if they are also41 // optimized by the stack engine.42 // TODO: We currently just remove all RSP writes from stack operations. This43 // is not fully correct because we do not model sync uops which will44 // delay subsequent rsp using non-stack instructions.45 if (X86::isPOP(MCI.getOpcode()) || X86::isPUSH(MCI.getOpcode())) {46 auto *StackRegisterDef =47 llvm::find_if(Inst.getDefs(), [](const WriteState &State) {48 return State.getRegisterID() == X86::RSP;49 });50 assert(51 StackRegisterDef != Inst.getDefs().end() &&52 "Expected push instruction to implicitly use stack pointer register.");53 Inst.getDefs().erase(StackRegisterDef);54 }55}56 57void X86InstrPostProcess::postProcessInstruction(Instruction &Inst,58 const MCInst &MCI) {59 // Set IsALoadBarrier and IsAStoreBarrier flags.60 setMemBarriers(Inst, MCI);61 useStackEngine(Inst, MCI);62}63 64} // namespace mca65} // namespace llvm66 67using namespace llvm;68using namespace mca;69 70static InstrPostProcess *createX86InstrPostProcess(const MCSubtargetInfo &STI,71 const MCInstrInfo &MCII) {72 return new X86InstrPostProcess(STI, MCII);73}74 75/// Extern function to initialize the targets for the X86 backend76 77extern "C" LLVM_C_ABI void LLVMInitializeX86TargetMCA() {78 TargetRegistry::RegisterInstrPostProcess(getTheX86_32Target(),79 createX86InstrPostProcess);80 TargetRegistry::RegisterInstrPostProcess(getTheX86_64Target(),81 createX86InstrPostProcess);82}83