942 lines · cpp
1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides X86 specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#include "X86MCTargetDesc.h"14#include "TargetInfo/X86TargetInfo.h"15#include "X86ATTInstPrinter.h"16#include "X86BaseInfo.h"17#include "X86IntelInstPrinter.h"18#include "X86MCAsmInfo.h"19#include "X86TargetStreamer.h"20#include "llvm-c/Visibility.h"21#include "llvm/ADT/APInt.h"22#include "llvm/DebugInfo/CodeView/CodeView.h"23#include "llvm/MC/MCDwarf.h"24#include "llvm/MC/MCInstrAnalysis.h"25#include "llvm/MC/MCInstrInfo.h"26#include "llvm/MC/MCRegisterInfo.h"27#include "llvm/MC/MCStreamer.h"28#include "llvm/MC/MCSubtargetInfo.h"29#include "llvm/MC/TargetRegistry.h"30#include "llvm/Support/ErrorHandling.h"31#include "llvm/TargetParser/Host.h"32#include "llvm/TargetParser/Triple.h"33 34using namespace llvm;35 36#define GET_REGINFO_MC_DESC37#include "X86GenRegisterInfo.inc"38 39#define GET_INSTRINFO_MC_DESC40#define GET_INSTRINFO_MC_HELPERS41#define ENABLE_INSTR_PREDICATE_VERIFIER42#include "X86GenInstrInfo.inc"43 44#define GET_SUBTARGETINFO_MC_DESC45#include "X86GenSubtargetInfo.inc"46 47std::string X86_MC::ParseX86Triple(const Triple &TT) {48 std::string FS;49 // SSE2 should default to enabled in 64-bit mode, but can be turned off50 // explicitly.51 if (TT.isX86_64())52 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";53 else if (TT.getEnvironment() != Triple::CODE16)54 FS = "-64bit-mode,+32bit-mode,-16bit-mode";55 else56 FS = "-64bit-mode,-32bit-mode,+16bit-mode";57 58 if (TT.isX32())59 FS += ",+x32";60 61 return FS;62}63 64unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {65 if (TT.isX86_64())66 return DWARFFlavour::X86_64;67 68 if (TT.isOSDarwin())69 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;70 if (TT.isOSCygMing())71 // Unsupported by now, just quick fallback72 return DWARFFlavour::X86_32_Generic;73 return DWARFFlavour::X86_32_Generic;74}75 76bool X86_MC::hasLockPrefix(const MCInst &MI) {77 return MI.getFlags() & X86::IP_HAS_LOCK;78}79 80static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) {81 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);82 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);83 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID];84 85 return (Base.isReg() && Base.getReg() && RC.contains(Base.getReg())) ||86 (Index.isReg() && Index.getReg() && RC.contains(Index.getReg()));87}88 89bool X86_MC::is16BitMemOperand(const MCInst &MI, unsigned Op,90 const MCSubtargetInfo &STI) {91 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);92 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);93 94 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && !Base.getReg() &&95 Index.isReg() && !Index.getReg())96 return true;97 return isMemOperand(MI, Op, X86::GR16RegClassID);98}99 100bool X86_MC::is32BitMemOperand(const MCInst &MI, unsigned Op) {101 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);102 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg);103 if (Base.isReg() && Base.getReg() == X86::EIP) {104 assert(Index.isReg() && !Index.getReg() && "Invalid eip-based address");105 return true;106 }107 if (Index.isReg() && Index.getReg() == X86::EIZ)108 return true;109 return isMemOperand(MI, Op, X86::GR32RegClassID);110}111 112#ifndef NDEBUG113bool X86_MC::is64BitMemOperand(const MCInst &MI, unsigned Op) {114 return isMemOperand(MI, Op, X86::GR64RegClassID);115}116#endif117 118bool X86_MC::needsAddressSizeOverride(const MCInst &MI,119 const MCSubtargetInfo &STI,120 int MemoryOperand, uint64_t TSFlags) {121 uint64_t AdSize = TSFlags & X86II::AdSizeMask;122 bool Is16BitMode = STI.hasFeature(X86::Is16Bit);123 bool Is32BitMode = STI.hasFeature(X86::Is32Bit);124 bool Is64BitMode = STI.hasFeature(X86::Is64Bit);125 if ((Is16BitMode && AdSize == X86II::AdSize32) ||126 (Is32BitMode && AdSize == X86II::AdSize16) ||127 (Is64BitMode && AdSize == X86II::AdSize32))128 return true;129 uint64_t Form = TSFlags & X86II::FormMask;130 switch (Form) {131 default:132 break;133 case X86II::RawFrmDstSrc: {134 MCRegister siReg = MI.getOperand(1).getReg();135 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||136 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||137 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&138 "SI and DI register sizes do not match");139 return (!Is32BitMode && siReg == X86::ESI) ||140 (Is32BitMode && siReg == X86::SI);141 }142 case X86II::RawFrmSrc: {143 MCRegister siReg = MI.getOperand(0).getReg();144 return (!Is32BitMode && siReg == X86::ESI) ||145 (Is32BitMode && siReg == X86::SI);146 }147 case X86II::RawFrmDst: {148 MCRegister siReg = MI.getOperand(0).getReg();149 return (!Is32BitMode && siReg == X86::EDI) ||150 (Is32BitMode && siReg == X86::DI);151 }152 }153 154 // Determine where the memory operand starts, if present.155 if (MemoryOperand < 0)156 return false;157 158 if (STI.hasFeature(X86::Is64Bit)) {159 assert(!is16BitMemOperand(MI, MemoryOperand, STI));160 return is32BitMemOperand(MI, MemoryOperand);161 }162 if (STI.hasFeature(X86::Is32Bit)) {163 assert(!is64BitMemOperand(MI, MemoryOperand));164 return is16BitMemOperand(MI, MemoryOperand, STI);165 }166 assert(STI.hasFeature(X86::Is16Bit));167 assert(!is64BitMemOperand(MI, MemoryOperand));168 return !is16BitMemOperand(MI, MemoryOperand, STI);169}170 171void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {172 // FIXME: TableGen these.173 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {174 unsigned SEH = MRI->getEncodingValue(Reg);175 MRI->mapLLVMRegToSEHReg(Reg, SEH);176 }177 178 // Mapping from CodeView to MC register id.179 static const struct {180 codeview::RegisterId CVReg;181 MCPhysReg Reg;182 } RegMap[] = {183 {codeview::RegisterId::AL, X86::AL},184 {codeview::RegisterId::CL, X86::CL},185 {codeview::RegisterId::DL, X86::DL},186 {codeview::RegisterId::BL, X86::BL},187 {codeview::RegisterId::AH, X86::AH},188 {codeview::RegisterId::CH, X86::CH},189 {codeview::RegisterId::DH, X86::DH},190 {codeview::RegisterId::BH, X86::BH},191 {codeview::RegisterId::AX, X86::AX},192 {codeview::RegisterId::CX, X86::CX},193 {codeview::RegisterId::DX, X86::DX},194 {codeview::RegisterId::BX, X86::BX},195 {codeview::RegisterId::SP, X86::SP},196 {codeview::RegisterId::BP, X86::BP},197 {codeview::RegisterId::SI, X86::SI},198 {codeview::RegisterId::DI, X86::DI},199 {codeview::RegisterId::EAX, X86::EAX},200 {codeview::RegisterId::ECX, X86::ECX},201 {codeview::RegisterId::EDX, X86::EDX},202 {codeview::RegisterId::EBX, X86::EBX},203 {codeview::RegisterId::ESP, X86::ESP},204 {codeview::RegisterId::EBP, X86::EBP},205 {codeview::RegisterId::ESI, X86::ESI},206 {codeview::RegisterId::EDI, X86::EDI},207 208 {codeview::RegisterId::EFLAGS, X86::EFLAGS},209 210 {codeview::RegisterId::ST0, X86::ST0},211 {codeview::RegisterId::ST1, X86::ST1},212 {codeview::RegisterId::ST2, X86::ST2},213 {codeview::RegisterId::ST3, X86::ST3},214 {codeview::RegisterId::ST4, X86::ST4},215 {codeview::RegisterId::ST5, X86::ST5},216 {codeview::RegisterId::ST6, X86::ST6},217 {codeview::RegisterId::ST7, X86::ST7},218 219 {codeview::RegisterId::ST0, X86::FP0},220 {codeview::RegisterId::ST1, X86::FP1},221 {codeview::RegisterId::ST2, X86::FP2},222 {codeview::RegisterId::ST3, X86::FP3},223 {codeview::RegisterId::ST4, X86::FP4},224 {codeview::RegisterId::ST5, X86::FP5},225 {codeview::RegisterId::ST6, X86::FP6},226 {codeview::RegisterId::ST7, X86::FP7},227 228 {codeview::RegisterId::MM0, X86::MM0},229 {codeview::RegisterId::MM1, X86::MM1},230 {codeview::RegisterId::MM2, X86::MM2},231 {codeview::RegisterId::MM3, X86::MM3},232 {codeview::RegisterId::MM4, X86::MM4},233 {codeview::RegisterId::MM5, X86::MM5},234 {codeview::RegisterId::MM6, X86::MM6},235 {codeview::RegisterId::MM7, X86::MM7},236 237 {codeview::RegisterId::XMM0, X86::XMM0},238 {codeview::RegisterId::XMM1, X86::XMM1},239 {codeview::RegisterId::XMM2, X86::XMM2},240 {codeview::RegisterId::XMM3, X86::XMM3},241 {codeview::RegisterId::XMM4, X86::XMM4},242 {codeview::RegisterId::XMM5, X86::XMM5},243 {codeview::RegisterId::XMM6, X86::XMM6},244 {codeview::RegisterId::XMM7, X86::XMM7},245 246 {codeview::RegisterId::XMM8, X86::XMM8},247 {codeview::RegisterId::XMM9, X86::XMM9},248 {codeview::RegisterId::XMM10, X86::XMM10},249 {codeview::RegisterId::XMM11, X86::XMM11},250 {codeview::RegisterId::XMM12, X86::XMM12},251 {codeview::RegisterId::XMM13, X86::XMM13},252 {codeview::RegisterId::XMM14, X86::XMM14},253 {codeview::RegisterId::XMM15, X86::XMM15},254 255 {codeview::RegisterId::SIL, X86::SIL},256 {codeview::RegisterId::DIL, X86::DIL},257 {codeview::RegisterId::BPL, X86::BPL},258 {codeview::RegisterId::SPL, X86::SPL},259 {codeview::RegisterId::RAX, X86::RAX},260 {codeview::RegisterId::RBX, X86::RBX},261 {codeview::RegisterId::RCX, X86::RCX},262 {codeview::RegisterId::RDX, X86::RDX},263 {codeview::RegisterId::RSI, X86::RSI},264 {codeview::RegisterId::RDI, X86::RDI},265 {codeview::RegisterId::RBP, X86::RBP},266 {codeview::RegisterId::RSP, X86::RSP},267 {codeview::RegisterId::R8, X86::R8},268 {codeview::RegisterId::R9, X86::R9},269 {codeview::RegisterId::R10, X86::R10},270 {codeview::RegisterId::R11, X86::R11},271 {codeview::RegisterId::R12, X86::R12},272 {codeview::RegisterId::R13, X86::R13},273 {codeview::RegisterId::R14, X86::R14},274 {codeview::RegisterId::R15, X86::R15},275 {codeview::RegisterId::R8B, X86::R8B},276 {codeview::RegisterId::R9B, X86::R9B},277 {codeview::RegisterId::R10B, X86::R10B},278 {codeview::RegisterId::R11B, X86::R11B},279 {codeview::RegisterId::R12B, X86::R12B},280 {codeview::RegisterId::R13B, X86::R13B},281 {codeview::RegisterId::R14B, X86::R14B},282 {codeview::RegisterId::R15B, X86::R15B},283 {codeview::RegisterId::R8W, X86::R8W},284 {codeview::RegisterId::R9W, X86::R9W},285 {codeview::RegisterId::R10W, X86::R10W},286 {codeview::RegisterId::R11W, X86::R11W},287 {codeview::RegisterId::R12W, X86::R12W},288 {codeview::RegisterId::R13W, X86::R13W},289 {codeview::RegisterId::R14W, X86::R14W},290 {codeview::RegisterId::R15W, X86::R15W},291 {codeview::RegisterId::R8D, X86::R8D},292 {codeview::RegisterId::R9D, X86::R9D},293 {codeview::RegisterId::R10D, X86::R10D},294 {codeview::RegisterId::R11D, X86::R11D},295 {codeview::RegisterId::R12D, X86::R12D},296 {codeview::RegisterId::R13D, X86::R13D},297 {codeview::RegisterId::R14D, X86::R14D},298 {codeview::RegisterId::R15D, X86::R15D},299 {codeview::RegisterId::AMD64_YMM0, X86::YMM0},300 {codeview::RegisterId::AMD64_YMM1, X86::YMM1},301 {codeview::RegisterId::AMD64_YMM2, X86::YMM2},302 {codeview::RegisterId::AMD64_YMM3, X86::YMM3},303 {codeview::RegisterId::AMD64_YMM4, X86::YMM4},304 {codeview::RegisterId::AMD64_YMM5, X86::YMM5},305 {codeview::RegisterId::AMD64_YMM6, X86::YMM6},306 {codeview::RegisterId::AMD64_YMM7, X86::YMM7},307 {codeview::RegisterId::AMD64_YMM8, X86::YMM8},308 {codeview::RegisterId::AMD64_YMM9, X86::YMM9},309 {codeview::RegisterId::AMD64_YMM10, X86::YMM10},310 {codeview::RegisterId::AMD64_YMM11, X86::YMM11},311 {codeview::RegisterId::AMD64_YMM12, X86::YMM12},312 {codeview::RegisterId::AMD64_YMM13, X86::YMM13},313 {codeview::RegisterId::AMD64_YMM14, X86::YMM14},314 {codeview::RegisterId::AMD64_YMM15, X86::YMM15},315 {codeview::RegisterId::AMD64_YMM16, X86::YMM16},316 {codeview::RegisterId::AMD64_YMM17, X86::YMM17},317 {codeview::RegisterId::AMD64_YMM18, X86::YMM18},318 {codeview::RegisterId::AMD64_YMM19, X86::YMM19},319 {codeview::RegisterId::AMD64_YMM20, X86::YMM20},320 {codeview::RegisterId::AMD64_YMM21, X86::YMM21},321 {codeview::RegisterId::AMD64_YMM22, X86::YMM22},322 {codeview::RegisterId::AMD64_YMM23, X86::YMM23},323 {codeview::RegisterId::AMD64_YMM24, X86::YMM24},324 {codeview::RegisterId::AMD64_YMM25, X86::YMM25},325 {codeview::RegisterId::AMD64_YMM26, X86::YMM26},326 {codeview::RegisterId::AMD64_YMM27, X86::YMM27},327 {codeview::RegisterId::AMD64_YMM28, X86::YMM28},328 {codeview::RegisterId::AMD64_YMM29, X86::YMM29},329 {codeview::RegisterId::AMD64_YMM30, X86::YMM30},330 {codeview::RegisterId::AMD64_YMM31, X86::YMM31},331 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},332 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},333 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},334 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},335 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},336 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},337 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},338 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},339 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},340 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},341 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},342 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},343 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},344 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},345 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},346 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},347 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},348 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},349 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},350 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},351 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},352 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},353 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},354 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},355 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},356 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},357 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},358 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},359 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},360 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},361 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},362 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},363 {codeview::RegisterId::AMD64_K0, X86::K0},364 {codeview::RegisterId::AMD64_K1, X86::K1},365 {codeview::RegisterId::AMD64_K2, X86::K2},366 {codeview::RegisterId::AMD64_K3, X86::K3},367 {codeview::RegisterId::AMD64_K4, X86::K4},368 {codeview::RegisterId::AMD64_K5, X86::K5},369 {codeview::RegisterId::AMD64_K6, X86::K6},370 {codeview::RegisterId::AMD64_K7, X86::K7},371 {codeview::RegisterId::AMD64_XMM16, X86::XMM16},372 {codeview::RegisterId::AMD64_XMM17, X86::XMM17},373 {codeview::RegisterId::AMD64_XMM18, X86::XMM18},374 {codeview::RegisterId::AMD64_XMM19, X86::XMM19},375 {codeview::RegisterId::AMD64_XMM20, X86::XMM20},376 {codeview::RegisterId::AMD64_XMM21, X86::XMM21},377 {codeview::RegisterId::AMD64_XMM22, X86::XMM22},378 {codeview::RegisterId::AMD64_XMM23, X86::XMM23},379 {codeview::RegisterId::AMD64_XMM24, X86::XMM24},380 {codeview::RegisterId::AMD64_XMM25, X86::XMM25},381 {codeview::RegisterId::AMD64_XMM26, X86::XMM26},382 {codeview::RegisterId::AMD64_XMM27, X86::XMM27},383 {codeview::RegisterId::AMD64_XMM28, X86::XMM28},384 {codeview::RegisterId::AMD64_XMM29, X86::XMM29},385 {codeview::RegisterId::AMD64_XMM30, X86::XMM30},386 {codeview::RegisterId::AMD64_XMM31, X86::XMM31},387 388 };389 for (const auto &I : RegMap)390 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));391}392 393MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,394 StringRef CPU, StringRef FS) {395 std::string ArchFS = X86_MC::ParseX86Triple(TT);396 assert(!ArchFS.empty() && "Failed to parse X86 triple");397 if (!FS.empty())398 ArchFS = (Twine(ArchFS) + "," + FS).str();399 400 if (CPU.empty())401 CPU = "generic";402 403 return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);404}405 406static MCInstrInfo *createX86MCInstrInfo() {407 MCInstrInfo *X = new MCInstrInfo();408 InitX86MCInstrInfo(X);409 return X;410}411 412static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {413 unsigned RA = TT.isX86_64() ? X86::RIP // Should have dwarf #16.414 : X86::EIP; // Should have dwarf #8.415 416 MCRegisterInfo *X = new MCRegisterInfo();417 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),418 X86_MC::getDwarfRegFlavour(TT, true), RA);419 X86_MC::initLLVMToSEHAndCVRegMapping(X);420 return X;421}422 423static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,424 const Triple &TheTriple,425 const MCTargetOptions &Options) {426 bool is64Bit = TheTriple.isX86_64();427 428 MCAsmInfo *MAI;429 if (TheTriple.isOSBinFormatMachO()) {430 if (is64Bit)431 MAI = new X86_64MCAsmInfoDarwin(TheTriple);432 else433 MAI = new X86MCAsmInfoDarwin(TheTriple);434 } else if (TheTriple.isOSBinFormatELF()) {435 // Force the use of an ELF container.436 MAI = new X86ELFMCAsmInfo(TheTriple);437 } else if (TheTriple.isWindowsMSVCEnvironment() ||438 TheTriple.isWindowsCoreCLREnvironment() || TheTriple.isUEFI()) {439 if (Options.getAssemblyLanguage().equals_insensitive("masm"))440 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple);441 else442 MAI = new X86MCAsmInfoMicrosoft(TheTriple);443 } else if (TheTriple.isOSCygMing() ||444 TheTriple.isWindowsItaniumEnvironment()) {445 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);446 } else {447 // The default is ELF.448 MAI = new X86ELFMCAsmInfo(TheTriple);449 }450 451 // Initialize initial frame state.452 // Calculate amount of bytes used for return address storing453 int stackGrowth = is64Bit ? -8 : -4;454 455 // Initial state of the frame pointer is esp+stackGrowth.456 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;457 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(458 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);459 MAI->addInitialFrameState(Inst);460 461 // Add return address to move list462 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;463 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(464 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);465 MAI->addInitialFrameState(Inst2);466 467 return MAI;468}469 470static MCInstPrinter *createX86MCInstPrinter(const Triple &T,471 unsigned SyntaxVariant,472 const MCAsmInfo &MAI,473 const MCInstrInfo &MII,474 const MCRegisterInfo &MRI) {475 if (SyntaxVariant == 0)476 return new X86ATTInstPrinter(MAI, MII, MRI);477 if (SyntaxVariant == 1)478 return new X86IntelInstPrinter(MAI, MII, MRI);479 return nullptr;480}481 482static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,483 MCContext &Ctx) {484 // Default to the stock relocation info.485 return llvm::createMCRelocationInfo(TheTriple, Ctx);486}487 488namespace llvm {489namespace X86_MC {490 491class X86MCInstrAnalysis : public MCInstrAnalysis {492 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;493 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;494 ~X86MCInstrAnalysis() override = default;495 496public:497 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}498 499#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS500#include "X86GenSubtargetInfo.inc"501 502 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,503 APInt &Mask) const override;504 std::vector<std::pair<uint64_t, uint64_t>>505 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,506 const MCSubtargetInfo &STI) const override;507 508 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,509 uint64_t &Target) const override;510 std::optional<uint64_t>511 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,512 uint64_t Addr, uint64_t Size) const override;513 std::optional<uint64_t>514 getMemoryOperandRelocationOffset(const MCInst &Inst,515 uint64_t Size) const override;516};517 518#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS519#include "X86GenSubtargetInfo.inc"520 521bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,522 const MCInst &Inst,523 APInt &Mask) const {524 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());525 unsigned NumDefs = Desc.getNumDefs();526 unsigned NumImplicitDefs = Desc.implicit_defs().size();527 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&528 "Unexpected number of bits in the mask!");529 530 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;531 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;532 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;533 534 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);535 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);536 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);537 538 auto ClearsSuperReg = [=](MCRegister RegID) {539 // On X86-64, a general purpose integer register is viewed as a 64-bit540 // register internal to the processor.541 // An update to the lower 32 bits of a 64 bit integer register is542 // architecturally defined to zero extend the upper 32 bits.543 if (GR32RC.contains(RegID))544 return true;545 546 // Early exit if this instruction has no vex/evex/xop prefix.547 if (!HasEVEX && !HasVEX && !HasXOP)548 return false;549 550 // All VEX and EVEX encoded instructions are defined to zero the high bits551 // of the destination register up to VLMAX (i.e. the maximum vector register552 // width pertaining to the instruction).553 // We assume the same behavior for XOP instructions too.554 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);555 };556 557 Mask.clearAllBits();558 for (unsigned I = 0, E = NumDefs; I < E; ++I) {559 const MCOperand &Op = Inst.getOperand(I);560 if (ClearsSuperReg(Op.getReg()))561 Mask.setBit(I);562 }563 564 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {565 const MCPhysReg Reg = Desc.implicit_defs()[I];566 if (ClearsSuperReg(Reg))567 Mask.setBit(NumDefs + I);568 }569 570 return Mask.getBoolValue();571}572 573static std::vector<std::pair<uint64_t, uint64_t>>574findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {575 // Do a lightweight parsing of PLT entries.576 std::vector<std::pair<uint64_t, uint64_t>> Result;577 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {578 // Recognize a jmp.579 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) {580 // The jmp instruction at the beginning of each PLT entry jumps to the581 // address of the base of the .got.plt section plus the immediate.582 // Set the 1 << 32 bit to let ELFObjectFileBase::getPltEntries convert the583 // offset to an address. Imm may be a negative int32_t if the GOT entry is584 // in .got.585 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);586 Result.emplace_back(PltSectionVA + Byte, Imm | (uint64_t(1) << 32));587 Byte += 6;588 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {589 // The jmp instruction at the beginning of each PLT entry jumps to the590 // immediate.591 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);592 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));593 Byte += 6;594 } else595 Byte++;596 }597 return Result;598}599 600static std::vector<std::pair<uint64_t, uint64_t>>601findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) {602 // Do a lightweight parsing of PLT entries.603 std::vector<std::pair<uint64_t, uint64_t>> Result;604 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) {605 // Recognize a jmp.606 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) {607 // The jmp instruction at the beginning of each PLT entry jumps to the608 // address of the next instruction plus the immediate.609 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2);610 Result.push_back(611 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm));612 Byte += 6;613 } else614 Byte++;615 }616 return Result;617}618 619std::vector<std::pair<uint64_t, uint64_t>>620X86MCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,621 ArrayRef<uint8_t> PltContents,622 const MCSubtargetInfo &STI) const {623 const Triple &TargetTriple = STI.getTargetTriple();624 switch (TargetTriple.getArch()) {625 case Triple::x86:626 return findX86PltEntries(PltSectionVA, PltContents);627 case Triple::x86_64:628 return findX86_64PltEntries(PltSectionVA, PltContents);629 default:630 return {};631 }632}633 634bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,635 uint64_t Size, uint64_t &Target) const {636 if (Inst.getNumOperands() == 0 ||637 Info->get(Inst.getOpcode()).operands()[0].OperandType !=638 MCOI::OPERAND_PCREL)639 return false;640 Target = Addr + Size + Inst.getOperand(0).getImm();641 return true;642}643 644std::optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(645 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,646 uint64_t Size) const {647 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());648 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);649 if (MemOpStart == -1)650 return std::nullopt;651 MemOpStart += X86II::getOperandBias(MCID);652 653 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);654 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);655 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);656 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);657 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);658 if (SegReg.getReg() || IndexReg.getReg() || ScaleAmt.getImm() != 1 ||659 !Disp.isImm())660 return std::nullopt;661 662 // RIP-relative addressing.663 if (BaseReg.getReg() == X86::RIP)664 return Addr + Size + Disp.getImm();665 666 return std::nullopt;667}668 669std::optional<uint64_t>670X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,671 uint64_t Size) const {672 if (Inst.getOpcode() != X86::LEA64r)673 return std::nullopt;674 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());675 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);676 if (MemOpStart == -1)677 return std::nullopt;678 MemOpStart += X86II::getOperandBias(MCID);679 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);680 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);681 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);682 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);683 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);684 // Must be a simple rip-relative address.685 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() || IndexReg.getReg() ||686 ScaleAmt.getImm() != 1 || !Disp.isImm())687 return std::nullopt;688 // rip-relative ModR/M immediate is 32 bits.689 assert(Size > 4 && "invalid instruction size for rip-relative lea");690 return Size - 4;691}692 693} // end of namespace X86_MC694 695} // end of namespace llvm696 697static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {698 return new X86_MC::X86MCInstrAnalysis(Info);699}700 701// Force static initialization.702extern "C" LLVM_C_ABI void LLVMInitializeX86TargetMC() {703 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {704 // Register the MC asm info.705 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);706 707 // Register the MC instruction info.708 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);709 710 // Register the MC register info.711 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);712 713 // Register the MC subtarget info.714 TargetRegistry::RegisterMCSubtargetInfo(*T,715 X86_MC::createX86MCSubtargetInfo);716 717 // Register the MC instruction analyzer.718 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);719 720 // Register the code emitter.721 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);722 723 // Register the obj target streamer.724 TargetRegistry::RegisterObjectTargetStreamer(*T,725 createX86ObjectTargetStreamer);726 727 // Register the asm target streamer.728 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer);729 730 // Register the null streamer.731 TargetRegistry::RegisterNullTargetStreamer(*T, createX86NullTargetStreamer);732 733 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);734 TargetRegistry::RegisterELFStreamer(*T, createX86ELFStreamer);735 736 // Register the MCInstPrinter.737 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);738 739 // Register the MC relocation info.740 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);741 }742 743 // Register the asm backend.744 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),745 createX86_32AsmBackend);746 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),747 createX86_64AsmBackend);748}749 750MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size,751 bool High) {752#define DEFAULT_NOREG \753 default: \754 return X86::NoRegister;755#define SUB_SUPER(R1, R2, R3, R4, R) \756 case X86::R1: \757 case X86::R2: \758 case X86::R3: \759 case X86::R4: \760 return X86::R;761#define A_SUB_SUPER(R) \762 case X86::AH: \763 SUB_SUPER(AL, AX, EAX, RAX, R)764#define D_SUB_SUPER(R) \765 case X86::DH: \766 SUB_SUPER(DL, DX, EDX, RDX, R)767#define C_SUB_SUPER(R) \768 case X86::CH: \769 SUB_SUPER(CL, CX, ECX, RCX, R)770#define B_SUB_SUPER(R) \771 case X86::BH: \772 SUB_SUPER(BL, BX, EBX, RBX, R)773#define SI_SUB_SUPER(R) SUB_SUPER(SIL, SI, ESI, RSI, R)774#define DI_SUB_SUPER(R) SUB_SUPER(DIL, DI, EDI, RDI, R)775#define BP_SUB_SUPER(R) SUB_SUPER(BPL, BP, EBP, RBP, R)776#define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R)777#define NO_SUB_SUPER(NO, REG) \778 SUB_SUPER(R##NO##B, R##NO##W, R##NO##D, R##NO, REG)779#define NO_SUB_SUPER_B(NO) NO_SUB_SUPER(NO, R##NO##B)780#define NO_SUB_SUPER_W(NO) NO_SUB_SUPER(NO, R##NO##W)781#define NO_SUB_SUPER_D(NO) NO_SUB_SUPER(NO, R##NO##D)782#define NO_SUB_SUPER_Q(NO) NO_SUB_SUPER(NO, R##NO)783 switch (Size) {784 default:785 llvm_unreachable("illegal register size");786 case 8:787 if (High) {788 switch (Reg.id()) {789 DEFAULT_NOREG790 A_SUB_SUPER(AH)791 D_SUB_SUPER(DH)792 C_SUB_SUPER(CH)793 B_SUB_SUPER(BH)794 }795 } else {796 switch (Reg.id()) {797 DEFAULT_NOREG798 A_SUB_SUPER(AL)799 D_SUB_SUPER(DL)800 C_SUB_SUPER(CL)801 B_SUB_SUPER(BL)802 SI_SUB_SUPER(SIL)803 DI_SUB_SUPER(DIL)804 BP_SUB_SUPER(BPL)805 SP_SUB_SUPER(SPL)806 NO_SUB_SUPER_B(8)807 NO_SUB_SUPER_B(9)808 NO_SUB_SUPER_B(10)809 NO_SUB_SUPER_B(11)810 NO_SUB_SUPER_B(12)811 NO_SUB_SUPER_B(13)812 NO_SUB_SUPER_B(14)813 NO_SUB_SUPER_B(15)814 NO_SUB_SUPER_B(16)815 NO_SUB_SUPER_B(17)816 NO_SUB_SUPER_B(18)817 NO_SUB_SUPER_B(19)818 NO_SUB_SUPER_B(20)819 NO_SUB_SUPER_B(21)820 NO_SUB_SUPER_B(22)821 NO_SUB_SUPER_B(23)822 NO_SUB_SUPER_B(24)823 NO_SUB_SUPER_B(25)824 NO_SUB_SUPER_B(26)825 NO_SUB_SUPER_B(27)826 NO_SUB_SUPER_B(28)827 NO_SUB_SUPER_B(29)828 NO_SUB_SUPER_B(30)829 NO_SUB_SUPER_B(31)830 }831 }832 case 16:833 switch (Reg.id()) {834 DEFAULT_NOREG835 A_SUB_SUPER(AX)836 D_SUB_SUPER(DX)837 C_SUB_SUPER(CX)838 B_SUB_SUPER(BX)839 SI_SUB_SUPER(SI)840 DI_SUB_SUPER(DI)841 BP_SUB_SUPER(BP)842 SP_SUB_SUPER(SP)843 NO_SUB_SUPER_W(8)844 NO_SUB_SUPER_W(9)845 NO_SUB_SUPER_W(10)846 NO_SUB_SUPER_W(11)847 NO_SUB_SUPER_W(12)848 NO_SUB_SUPER_W(13)849 NO_SUB_SUPER_W(14)850 NO_SUB_SUPER_W(15)851 NO_SUB_SUPER_W(16)852 NO_SUB_SUPER_W(17)853 NO_SUB_SUPER_W(18)854 NO_SUB_SUPER_W(19)855 NO_SUB_SUPER_W(20)856 NO_SUB_SUPER_W(21)857 NO_SUB_SUPER_W(22)858 NO_SUB_SUPER_W(23)859 NO_SUB_SUPER_W(24)860 NO_SUB_SUPER_W(25)861 NO_SUB_SUPER_W(26)862 NO_SUB_SUPER_W(27)863 NO_SUB_SUPER_W(28)864 NO_SUB_SUPER_W(29)865 NO_SUB_SUPER_W(30)866 NO_SUB_SUPER_W(31)867 }868 case 32:869 switch (Reg.id()) {870 DEFAULT_NOREG871 A_SUB_SUPER(EAX)872 D_SUB_SUPER(EDX)873 C_SUB_SUPER(ECX)874 B_SUB_SUPER(EBX)875 SI_SUB_SUPER(ESI)876 DI_SUB_SUPER(EDI)877 BP_SUB_SUPER(EBP)878 SP_SUB_SUPER(ESP)879 NO_SUB_SUPER_D(8)880 NO_SUB_SUPER_D(9)881 NO_SUB_SUPER_D(10)882 NO_SUB_SUPER_D(11)883 NO_SUB_SUPER_D(12)884 NO_SUB_SUPER_D(13)885 NO_SUB_SUPER_D(14)886 NO_SUB_SUPER_D(15)887 NO_SUB_SUPER_D(16)888 NO_SUB_SUPER_D(17)889 NO_SUB_SUPER_D(18)890 NO_SUB_SUPER_D(19)891 NO_SUB_SUPER_D(20)892 NO_SUB_SUPER_D(21)893 NO_SUB_SUPER_D(22)894 NO_SUB_SUPER_D(23)895 NO_SUB_SUPER_D(24)896 NO_SUB_SUPER_D(25)897 NO_SUB_SUPER_D(26)898 NO_SUB_SUPER_D(27)899 NO_SUB_SUPER_D(28)900 NO_SUB_SUPER_D(29)901 NO_SUB_SUPER_D(30)902 NO_SUB_SUPER_D(31)903 }904 case 64:905 switch (Reg.id()) {906 DEFAULT_NOREG907 A_SUB_SUPER(RAX)908 D_SUB_SUPER(RDX)909 C_SUB_SUPER(RCX)910 B_SUB_SUPER(RBX)911 SI_SUB_SUPER(RSI)912 DI_SUB_SUPER(RDI)913 BP_SUB_SUPER(RBP)914 SP_SUB_SUPER(RSP)915 NO_SUB_SUPER_Q(8)916 NO_SUB_SUPER_Q(9)917 NO_SUB_SUPER_Q(10)918 NO_SUB_SUPER_Q(11)919 NO_SUB_SUPER_Q(12)920 NO_SUB_SUPER_Q(13)921 NO_SUB_SUPER_Q(14)922 NO_SUB_SUPER_Q(15)923 NO_SUB_SUPER_Q(16)924 NO_SUB_SUPER_Q(17)925 NO_SUB_SUPER_Q(18)926 NO_SUB_SUPER_Q(19)927 NO_SUB_SUPER_Q(20)928 NO_SUB_SUPER_Q(21)929 NO_SUB_SUPER_Q(22)930 NO_SUB_SUPER_Q(23)931 NO_SUB_SUPER_Q(24)932 NO_SUB_SUPER_Q(25)933 NO_SUB_SUPER_Q(26)934 NO_SUB_SUPER_Q(27)935 NO_SUB_SUPER_Q(28)936 NO_SUB_SUPER_Q(29)937 NO_SUB_SUPER_Q(30)938 NO_SUB_SUPER_Q(31)939 }940 }941}942