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1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This is a target description file for the Intel i386 architecture, referred10// to here as the "X86" architecture.11//12//===----------------------------------------------------------------------===//13 14// Get the target-independent interfaces which we are implementing...15//16include "llvm/Target/Target.td"17 18//===----------------------------------------------------------------------===//19// X86 Subtarget state20//21// disregarding specific ABI / programming model22def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true",23 "64-bit mode (x86_64)">;24def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true",25 "32-bit mode (80386)">;26def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",27 "16-bit mode (i8086)">;28def IsX32 : SubtargetFeature<"x32", "IsX32", "true",29 "64-bit with ILP32 programming model (e.g. x32 ABI)">;30 31//===----------------------------------------------------------------------===//32// X86 Subtarget ISA features33//===----------------------------------------------------------------------===//34 35def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",36 "Enable X87 float instructions">;37 38def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true",39 "Enable NOPL instruction (generally pentium pro+)">;40 41def FeatureCMOV : SubtargetFeature<"cmov","HasCMOV", "true",42 "Enable conditional move instructions">;43 44def FeatureCX8 : SubtargetFeature<"cx8", "HasCX8", "true",45 "Support CMPXCHG8B instructions">;46 47def FeatureCRC32 : SubtargetFeature<"crc32", "HasCRC32", "true",48 "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">;49 50def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",51 "Support POPCNT instruction">;52 53def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",54 "Support fxsave/fxrestore instructions">;55 56def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",57 "Support xsave instructions">;58 59def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",60 "Support xsaveopt instructions",61 [FeatureXSAVE]>;62 63def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",64 "Support xsavec instructions",65 [FeatureXSAVE]>;66 67def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",68 "Support xsaves instructions",69 [FeatureXSAVE]>;70 71def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",72 "Enable SSE instructions">;73def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",74 "Enable SSE2 instructions",75 [FeatureSSE1]>;76def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",77 "Enable SSE3 instructions",78 [FeatureSSE2]>;79def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",80 "Enable SSSE3 instructions",81 [FeatureSSE3]>;82def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",83 "Enable SSE 4.1 instructions",84 [FeatureSSSE3]>;85def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",86 "Enable SSE 4.2 instructions",87 [FeatureSSE41]>;88// The MMX subtarget feature is separate from the rest of the SSE features89// because it's important (for odd compatibility reasons) to be able to90// turn it off explicitly while allowing SSE+ to be on.91def FeatureMMX : SubtargetFeature<"mmx","HasMMX", "true",92 "Enable MMX instructions">;93// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied94// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)95// without disabling 64-bit mode. Nothing should imply this feature bit. It96// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.97def FeatureX86_64 : SubtargetFeature<"64bit", "HasX86_64", "true",98 "Support 64-bit instructions">;99def FeatureCX16 : SubtargetFeature<"cx16", "HasCX16", "true",100 "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",101 [FeatureCX8]>;102def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",103 "Support SSE 4a instructions",104 [FeatureSSE3]>;105 106def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",107 "Enable AVX instructions",108 [FeatureSSE42]>;109def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",110 "Enable AVX2 instructions",111 [FeatureAVX]>;112def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",113 "Enable three-operand fused multiple-add",114 [FeatureAVX]>;115def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",116 "Support 16-bit floating point conversion instructions",117 [FeatureAVX]>;118// Deprecated feature. Keep it here to suppress warnings in old IRs.119def FeatureEVEX512 : SubtargetFeature<"evex512", "HasEVEX512", "true",120 "Support ZMM and 64-bit mask instructions">;121def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512",122 "Enable AVX-512 instructions",123 [FeatureAVX2, FeatureFMA, FeatureF16C]>;124def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",125 "Enable AVX-512 Conflict Detection Instructions",126 [FeatureAVX512]>;127def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",128 "true", "Enable AVX-512 Population Count Instructions",129 [FeatureAVX512]>;130def FeaturePREFETCHI : SubtargetFeature<"prefetchi", "HasPREFETCHI",131 "true",132 "Prefetch instruction with T0 or T1 Hint">;133def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",134 "Enable AVX-512 Doubleword and Quadword Instructions",135 [FeatureAVX512]>;136def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",137 "Enable AVX-512 Byte and Word Instructions",138 [FeatureAVX512]>;139def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",140 "Enable AVX-512 Vector Length eXtensions",141 [FeatureAVX512]>;142def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",143 "Enable AVX-512 Vector Byte Manipulation Instructions",144 [FeatureBWI]>;145def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",146 "Enable AVX-512 further Vector Byte Manipulation Instructions",147 [FeatureBWI]>;148def FeatureAVXIFMA : SubtargetFeature<"avxifma", "HasAVXIFMA", "true",149 "Enable AVX-IFMA",150 [FeatureAVX2]>;151def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true",152 "Enable AVX-512 Integer Fused Multiple-Add",153 [FeatureAVX512]>;154def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",155 "Enable protection keys">;156def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true",157 "Enable AVX-512 Vector Neural Network Instructions",158 [FeatureAVX512]>;159def FeatureAVXVNNI : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true",160 "Support AVX_VNNI encoding",161 [FeatureAVX2]>;162def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true",163 "Support bfloat16 floating point",164 [FeatureBWI]>;165def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",166 "Enable AVX-512 Bit Algorithms",167 [FeatureBWI]>;168def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect",169 "HasVP2INTERSECT", "true",170 "Enable AVX-512 vp2intersect",171 [FeatureAVX512]>;172def FeatureFP16 : SubtargetFeature<"avx512fp16", "HasFP16", "true",173 "Support 16-bit floating point",174 [FeatureBWI]>;175def FeatureAVXVNNIINT8 : SubtargetFeature<"avxvnniint8",176 "HasAVXVNNIINT8", "true",177 "Enable AVX-VNNI-INT8",178 [FeatureAVX2]>;179def FeatureAVXVNNIINT16 : SubtargetFeature<"avxvnniint16",180 "HasAVXVNNIINT16", "true",181 "Enable AVX-VNNI-INT16",182 [FeatureAVX2]>;183def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",184 "Enable packed carry-less multiplication instructions",185 [FeatureSSE2]>;186def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true",187 "Enable Galois Field Arithmetic Instructions",188 [FeatureSSE2]>;189def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",190 "Enable vpclmulqdq instructions",191 [FeatureAVX, FeaturePCLMUL]>;192def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",193 "Enable four-operand fused multiple-add",194 [FeatureAVX, FeatureSSE4A]>;195def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",196 "Enable XOP instructions",197 [FeatureFMA4]>;198def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",199 "HasSSEUnalignedMem", "true",200 "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">;201def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",202 "Enable AES instructions",203 [FeatureSSE2]>;204def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true",205 "Promote selected AES instructions to AVX512/AVX registers",206 [FeatureAVX2, FeatureAES]>;207def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",208 "Enable TBM instructions">;209def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true",210 "Enable LWP instructions">;211def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",212 "Support MOVBE instruction">;213def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",214 "Support RDRAND instruction">;215def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",216 "Support FS/GS Base instructions">;217def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",218 "Support LZCNT instruction">;219def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",220 "Support BMI instructions">;221def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",222 "Support BMI2 instructions">;223def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",224 "Support RTM instructions">;225def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",226 "Support ADX instructions">;227def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",228 "Enable SHA instructions",229 [FeatureSSE2]>;230def FeatureSHA512 : SubtargetFeature<"sha512", "HasSHA512", "true",231 "Support SHA512 instructions",232 [FeatureAVX2]>;233// Processor supports CET SHSTK - Control-Flow Enforcement Technology234// using Shadow Stack235def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",236 "Support CET Shadow-Stack instructions">;237def FeatureSM3 : SubtargetFeature<"sm3", "HasSM3", "true",238 "Support SM3 instructions",239 [FeatureAVX]>;240def FeatureSM4 : SubtargetFeature<"sm4", "HasSM4", "true",241 "Support SM4 instructions",242 [FeatureAVX2]>;243def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",244 "Support PRFCHW instructions">;245def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",246 "Support RDSEED instruction">;247def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",248 "Support LAHF and SAHF instructions in 64-bit mode">;249def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",250 "Enable MONITORX/MWAITX timer functionality">;251def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true",252 "Enable Cache Line Zero">;253def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",254 "Enable Cache Line Demote">;255def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",256 "Support ptwrite instruction">;257def FeatureAMXTILE : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",258 "Support AMX-TILE instructions">;259def FeatureAMXINT8 : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",260 "Support AMX-INT8 instructions",261 [FeatureAMXTILE]>;262def FeatureAMXBF16 : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",263 "Support AMX-BF16 instructions",264 [FeatureAMXTILE]>;265def FeatureAMXFP16 : SubtargetFeature<"amx-fp16", "HasAMXFP16", "true",266 "Support AMX amx-fp16 instructions",267 [FeatureAMXTILE]>;268def FeatureAMXCOMPLEX : SubtargetFeature<"amx-complex", "HasAMXCOMPLEX", "true",269 "Support AMX-COMPLEX instructions",270 [FeatureAMXTILE]>;271def FeatureAMXFP8 : SubtargetFeature<"amx-fp8", "HasAMXFP8", "true",272 "Support AMX-FP8 instructions",273 [FeatureAMXTILE]>;274def FeatureAMXMOVRS : SubtargetFeature<"amx-movrs", "HasAMXMOVRS", "true",275 "Support AMX-MOVRS instructions",276 [FeatureAMXTILE]>;277def FeatureAMXAVX512 : SubtargetFeature<"amx-avx512",278 "HasAMXAVX512", "true",279 "Support AMX-AVX512 instructions",280 [FeatureAMXTILE]>;281def FeatureAMXTF32 : SubtargetFeature<"amx-tf32", "HasAMXTF32", "true",282 "Support AMX-TF32 instructions",283 [FeatureAMXTILE]>;284def FeatureCMPCCXADD : SubtargetFeature<"cmpccxadd", "HasCMPCCXADD", "true",285 "Support CMPCCXADD instructions">;286def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true",287 "Support RAO-INT instructions",288 []>;289def FeatureAVXNECONVERT : SubtargetFeature<"avxneconvert", "HasAVXNECONVERT", "true",290 "Support AVX-NE-CONVERT instructions",291 [FeatureAVX2]>;292def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",293 "Invalidate Process-Context Identifier">;294def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",295 "Enable Software Guard Extensions">;296def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",297 "Flush A Cache Line Optimized">;298def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",299 "Cache Line Write Back">;300def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",301 "Write Back No Invalidate">;302def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",303 "Support RDPID instructions">;304def FeatureRDPRU : SubtargetFeature<"rdpru", "HasRDPRU", "true",305 "Support RDPRU instructions">;306def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",307 "Wait and pause enhancements">;308def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",309 "Has ENQCMD instructions">;310def FeatureKL : SubtargetFeature<"kl", "HasKL", "true",311 "Support Key Locker kl Instructions",312 [FeatureSSE2]>;313def FeatureWIDEKL : SubtargetFeature<"widekl", "HasWIDEKL", "true",314 "Support Key Locker wide Instructions",315 [FeatureKL]>;316def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true",317 "Has hreset instruction">;318def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",319 "Has serialize instruction">;320def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",321 "Support TSXLDTRK instructions">;322def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",323 "Has UINTR Instructions">;324def FeatureUSERMSR : SubtargetFeature<"usermsr", "HasUSERMSR", "true",325 "Support USERMSR instructions">;326def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",327 "platform configuration instruction">;328def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",329 "Support movdiri instruction (direct store integer)">;330def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",331 "Support movdir64b instruction (direct store 64 bytes)">;332def FeatureAVX10_1 : SubtargetFeature<"avx10.1", "HasAVX10_1", "true",333 "Support AVX10.1 instruction",334 [FeatureCDI, FeatureVBMI, FeatureIFMA, FeatureVNNI,335 FeatureBF16, FeatureVPOPCNTDQ, FeatureVBMI2, FeatureBITALG,336 FeatureFP16, FeatureVLX, FeatureDQI]>;337// Deprecated feature. Keep it here to suppress warnings in old IRs.338def FeatureAVX10_1_512 : SubtargetFeature<"avx10.1-512", "HasAVX10_1_512", "true",339 "Support AVX10.1 instruction",340 [FeatureAVX10_1]>;341def FeatureAVX10_2 : SubtargetFeature<"avx10.2", "HasAVX10_2", "true",342 "Support AVX10.2 instruction",343 [FeatureAVX10_1]>;344// Deprecated feature. Keep it here to suppress warnings in old IRs.345def FeatureAVX10_2_512 : SubtargetFeature<"avx10.2-512", "HasAVX10_2_512", "true",346 "Support AVX10.2 instruction",347 [FeatureAVX10_2]>;348def FeatureEGPR : SubtargetFeature<"egpr", "HasEGPR", "true",349 "Support extended general purpose register">;350def FeaturePush2Pop2 : SubtargetFeature<"push2pop2", "HasPush2Pop2", "true",351 "Support PUSH2/POP2 instructions">;352def FeaturePPX : SubtargetFeature<"ppx", "HasPPX", "true",353 "Support Push-Pop Acceleration">;354def FeatureNDD : SubtargetFeature<"ndd", "HasNDD", "true",355 "Support non-destructive destination">;356def FeatureCCMP : SubtargetFeature<"ccmp", "HasCCMP", "true",357 "Support conditional cmp & test instructions">;358def FeatureNF : SubtargetFeature<"nf", "HasNF", "true",359 "Support status flags update suppression">;360// FeatureCF is not enabled by default for APXF and targets that support APXF361// due to performance reason, though it is part of APXF. Users need to enable it362// manually.363def FeatureCF : SubtargetFeature<"cf", "HasCF", "true",364 "Support conditional faulting">;365def FeatureZU : SubtargetFeature<"zu", "HasZU", "true",366 "Support zero-upper SETcc/IMUL">;367def FeatureUseGPR32InInlineAsm368 : SubtargetFeature<"inline-asm-use-gpr32", "UseInlineAsmGPR32", "true",369 "Enable use of GPR32 in inline assembly for APX">;370def FeatureMOVRS : SubtargetFeature<"movrs", "HasMOVRS", "true",371 "Enable MOVRS", []>;372 373// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka374// "string operations"). See "REP String Enhancement" in the Intel Software375// Development Manual. This feature essentially means that REP MOVSB will copy376// using the largest available size instead of copying bytes one by one, making377// it at least as fast as REPMOVS{W,D,Q}.378def FeatureERMSB379 : SubtargetFeature<380 "ermsb", "HasERMSB", "true",381 "REP MOVS/STOS are fast">;382 383// Icelake and newer processors have Fast Short REP MOV.384def FeatureFSRM385 : SubtargetFeature<386 "fsrm", "HasFSRM", "true",387 "REP MOVSB of short lengths is faster">;388 389def FeatureSoftFloat390 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",391 "Use software floating point features">;392 393//===----------------------------------------------------------------------===//394// X86 Subtarget Security Mitigation features395//===----------------------------------------------------------------------===//396 397// Lower indirect calls using a special construct called a `retpoline` to398// mitigate potential Spectre v2 attacks against them.399def FeatureRetpolineIndirectCalls400 : SubtargetFeature<401 "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",402 "Remove speculation of indirect calls from the generated code">;403 404// Lower indirect branches and switches either using conditional branch trees405// or using a special construct called a `retpoline` to mitigate potential406// Spectre v2 attacks against them.407def FeatureRetpolineIndirectBranches408 : SubtargetFeature<409 "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",410 "Remove speculation of indirect branches from the generated code">;411 412// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and413// `retpoline-indirect-branches` above.414def FeatureRetpoline415 : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",416 "Remove speculation of indirect branches from the "417 "generated code, either by avoiding them entirely or "418 "lowering them with a speculation blocking construct",419 [FeatureRetpolineIndirectCalls,420 FeatureRetpolineIndirectBranches]>;421 422// Rely on external thunks for the emitted retpoline calls. This allows users423// to provide their own custom thunk definitions in highly specialized424// environments such as a kernel that does boot-time hot patching.425def FeatureRetpolineExternalThunk426 : SubtargetFeature<427 "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",428 "When lowering an indirect call or branch using a `retpoline`, rely "429 "on the specified user provided thunk rather than emitting one "430 "ourselves. Only has effect when combined with some other retpoline "431 "feature", [FeatureRetpolineIndirectCalls]>;432 433// Mitigate LVI attacks against indirect calls/branches and call returns434def FeatureLVIControlFlowIntegrity435 : SubtargetFeature<436 "lvi-cfi", "UseLVIControlFlowIntegrity", "true",437 "Prevent indirect calls/branches from using a memory operand, and "438 "precede all indirect calls/branches from a register with an "439 "LFENCE instruction to serialize control flow. Also decompose RET "440 "instructions into a POP+LFENCE+JMP sequence.">;441 442// Enable SESES to mitigate speculative execution attacks443def FeatureSpeculativeExecutionSideEffectSuppression444 : SubtargetFeature<445 "seses", "UseSpeculativeExecutionSideEffectSuppression", "true",446 "Prevent speculative execution side channel timing attacks by "447 "inserting a speculation barrier before memory reads, memory writes, "448 "and conditional branches. Implies LVI Control Flow integrity.",449 [FeatureLVIControlFlowIntegrity]>;450 451// Mitigate LVI attacks against data loads452def FeatureLVILoadHardening453 : SubtargetFeature<454 "lvi-load-hardening", "UseLVILoadHardening", "true",455 "Insert LFENCE instructions to prevent data speculatively injected "456 "into loads from being used maliciously.">;457 458def FeatureTaggedGlobals459 : SubtargetFeature<460 "tagged-globals", "AllowTaggedGlobals", "true",461 "Use an instruction sequence for taking the address of a global "462 "that allows a memory tag in the upper address bits.">;463 464// Control codegen mitigation against Straight Line Speculation vulnerability.465def FeatureHardenSlsRet466 : SubtargetFeature<467 "harden-sls-ret", "HardenSlsRet", "true",468 "Harden against straight line speculation across RET instructions.">;469 470def FeatureHardenSlsIJmp471 : SubtargetFeature<472 "harden-sls-ijmp", "HardenSlsIJmp", "true",473 "Harden against straight line speculation across indirect JMP instructions.">;474 475//===----------------------------------------------------------------------===//476// X86 Subtarget Tuning features477//===----------------------------------------------------------------------===//478def TuningPreferMovmskOverVTest : SubtargetFeature<"prefer-movmsk-over-vtest",479 "PreferMovmskOverVTest", "true",480 "Prefer movmsk over vtest instruction">;481 482def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",483 "SHLD instruction is slow">;484 485def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",486 "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)">;487 488def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",489 "true",490 "PMADDWD is slower than PMULLD">;491 492// FIXME: This should not apply to CPUs that do not have SSE.493def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",494 "IsUnalignedMem16Slow", "true",495 "Slow unaligned 16-byte memory access">;496 497def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",498 "IsUnalignedMem32Slow", "true",499 "Slow unaligned 32-byte memory access">;500 501def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",502 "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">;503 504// True if 8-bit divisions are significantly faster than505// 32-bit divisions and should be used when possible.506def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",507 "HasSlowDivide32", "true",508 "Use 8-bit divide for positive values less than 256">;509 510// True if 32-bit divides are significantly faster than511// 64-bit divisions and should be used when possible.512def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",513 "HasSlowDivide64", "true",514 "Use 32-bit divide for positive values less than 2^32">;515 516def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",517 "PadShortFunctions", "true",518 "Pad short functions (to prevent a stall when returning too early)">;519 520// On some processors, instructions that implicitly take two memory operands are521// slow. In practice, this means that CALL, PUSH, and POP with memory operands522// should be avoided in favor of a MOV + register CALL/PUSH/POP.523def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",524 "SlowTwoMemOps", "true",525 "Two memory operand instructions are slow">;526 527// True if the LEA instruction inputs have to be ready at address generation528// (AG) time.529def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true",530 "LEA instruction needs inputs at AG stage">;531 532def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",533 "LEA instruction with certain arguments is slow">;534 535// True if the LEA instruction has all three source operands: base, index,536// and offset or if the LEA instruction uses base and index registers where537// the base is EBP, RBP,or R13538def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",539 "LEA instruction with 3 ops or certain registers is slow">;540 541// True if INC and DEC instructions are slow when writing to flags542def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",543 "INC and DEC instructions are slower than ADD and SUB">;544 545def TuningPOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",546 "HasPOPCNTFalseDeps", "true",547 "POPCNT has a false dependency on dest register">;548 549def TuningLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",550 "HasLZCNTFalseDeps", "true",551 "LZCNT/TZCNT have a false dependency on dest register">;552 553def TuningMULCFalseDeps : SubtargetFeature<"false-deps-mulc",554 "HasMULCFalseDeps", "true",555 "VF[C]MULCPH/SH has a false dependency on dest register">;556 557def TuningPERMFalseDeps : SubtargetFeature<"false-deps-perm",558 "HasPERMFalseDeps", "true",559 "VPERMD/Q/PS/PD has a false dependency on dest register">;560 561def TuningRANGEFalseDeps : SubtargetFeature<"false-deps-range",562 "HasRANGEFalseDeps", "true",563 "VRANGEPD/PS/SD/SS has a false dependency on dest register">;564 565def TuningGETMANTFalseDeps : SubtargetFeature<"false-deps-getmant",566 "HasGETMANTFalseDeps", "true",567 "VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a"568 " false dependency on dest register">;569 570def TuningMULLQFalseDeps : SubtargetFeature<"false-deps-mullq",571 "HasMULLQFalseDeps", "true",572 "VPMULLQ has a false dependency on dest register">;573 574def TuningSBBDepBreaking : SubtargetFeature<"sbb-dep-breaking",575 "HasSBBDepBreaking", "true",576 "SBB with same register has no source dependency">;577 578// On recent X86 (port bound) processors, its preferable to combine to a single shuffle579// using a variable mask over multiple fixed shuffles.580def TuningFastVariableCrossLaneShuffle581 : SubtargetFeature<"fast-variable-crosslane-shuffle",582 "HasFastVariableCrossLaneShuffle",583 "true", "Cross-lane shuffles with variable masks are fast">;584def TuningFastVariablePerLaneShuffle585 : SubtargetFeature<"fast-variable-perlane-shuffle",586 "HasFastVariablePerLaneShuffle",587 "true", "Per-lane shuffles with variable masks are fast">;588 589// Goldmont / Tremont (atom in general) has no bypass delay590def TuningNoDomainDelay : SubtargetFeature<"no-bypass-delay",591 "NoDomainDelay","true",592 "Has no bypass delay when using the 'wrong' domain">;593 594// Many processors (Nehalem+ on Intel) have no bypass delay when595// using the wrong mov type.596def TuningNoDomainDelayMov : SubtargetFeature<"no-bypass-delay-mov",597 "NoDomainDelayMov","true",598 "Has no bypass delay when using the 'wrong' mov type">;599 600// Newer processors (Skylake+ on Intel) have no bypass delay when601// using the wrong blend type.602def TuningNoDomainDelayBlend : SubtargetFeature<"no-bypass-delay-blend",603 "NoDomainDelayBlend","true",604 "Has no bypass delay when using the 'wrong' blend type">;605 606// Newer processors (Haswell+ on Intel) have no bypass delay when607// using the wrong shuffle type.608def TuningNoDomainDelayShuffle : SubtargetFeature<"no-bypass-delay-shuffle",609 "NoDomainDelayShuffle","true",610 "Has no bypass delay when using the 'wrong' shuffle type">;611 612// Prefer lowering shuffles on AVX512 targets (e.g. Skylake Server) to613// imm shifts/rotate if they can use more ports than regular shuffles.614def TuningPreferShiftShuffle : SubtargetFeature<"faster-shift-than-shuffle",615 "PreferLowerShuffleAsShift", "true",616 "Shifts are faster (or as fast) as shuffle">;617 618def TuningFastImmVectorShift : SubtargetFeature<"tuning-fast-imm-vector-shift",619 "FastImmVectorShift", "true",620 "Vector shifts are fast (2/cycle) as opposed to slow (1/cycle)">;621 622// On some X86 processors, a vzeroupper instruction should be inserted after623// using ymm/zmm registers before executing code that may use SSE instructions.624def TuningInsertVZEROUPPER625 : SubtargetFeature<"vzeroupper",626 "InsertVZEROUPPER",627 "true", "Should insert vzeroupper instructions">;628 629// TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency630// than the corresponding NR code. TuningFastVectorFSQRT should be enabled if631// vector FSQRT has higher throughput than the corresponding NR code.632// The idea is that throughput bound code is likely to be vectorized, so for633// vectorized code we should care about the throughput of SQRT operations.634// But if the code is scalar that probably means that the code has some kind of635// dependency and we should care more about reducing the latency.636 637// True if hardware SQRTSS instruction is at least as fast (latency) as638// RSQRTSS followed by a Newton-Raphson iteration.639def TuningFastScalarFSQRT640 : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",641 "true", "Scalar SQRT is fast (disable Newton-Raphson)">;642// True if hardware SQRTPS/VSQRTPS instructions are at least as fast643// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.644def TuningFastVectorFSQRT645 : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",646 "true", "Vector SQRT is fast (disable Newton-Raphson)">;647 648// If lzcnt has equivalent latency/throughput to most simple integer ops, it can649// be used to replace test/set sequences.650def TuningFastLZCNT651 : SubtargetFeature<652 "fast-lzcnt", "HasFastLZCNT", "true",653 "LZCNT instructions are as fast as most simple integer ops">;654 655// If the target can efficiently decode NOPs upto 7-bytes in length.656def TuningFast7ByteNOP657 : SubtargetFeature<658 "fast-7bytenop", "HasFast7ByteNOP", "true",659 "Target can quickly decode up to 7 byte NOPs">;660 661// If the target can efficiently decode NOPs upto 11-bytes in length.662def TuningFast11ByteNOP663 : SubtargetFeature<664 "fast-11bytenop", "HasFast11ByteNOP", "true",665 "Target can quickly decode up to 11 byte NOPs">;666 667// If the target can efficiently decode NOPs upto 15-bytes in length.668def TuningFast15ByteNOP669 : SubtargetFeature<670 "fast-15bytenop", "HasFast15ByteNOP", "true",671 "Target can quickly decode up to 15 byte NOPs">;672 673// Sandy Bridge and newer processors can use SHLD with the same source on both674// inputs to implement rotate to avoid the partial flag update of the normal675// rotate instructions.676def TuningFastSHLDRotate677 : SubtargetFeature<678 "fast-shld-rotate", "HasFastSHLDRotate", "true",679 "SHLD can be used as a faster rotate">;680 681// Bulldozer and newer processors can merge CMP/TEST (but not other682// instructions) with conditional branches.683def TuningBranchFusion684 : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",685 "CMP/TEST can be fused with conditional branches">;686 687// Sandy Bridge and newer processors have many instructions that can be688// fused with conditional branches and pass through the CPU as a single689// operation.690def TuningMacroFusion691 : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",692 "Various instructions can be fused with conditional branches">;693 694// Gather is available since Haswell (AVX2 set). So technically, we can695// generate Gathers on all AVX2 processors. But the overhead on HSW is high.696// Skylake Client processor has faster Gathers than HSW and performance is697// similar to Skylake Server (AVX-512).698def TuningFastGather699 : SubtargetFeature<"fast-gather", "HasFastGather", "true",700 "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">;701 702// Generate vpdpwssd instead of vpmaddwd+vpaddd sequence.703def TuningFastDPWSSD704 : SubtargetFeature<705 "fast-dpwssd", "HasFastDPWSSD", "true",706 "Prefer vpdpwssd instruction over vpmaddwd+vpaddd instruction sequence">;707 708def TuningPreferNoGather709 : SubtargetFeature<"prefer-no-gather", "PreferGather", "false",710 "Prefer no gather instructions">;711def TuningPreferNoScatter712 : SubtargetFeature<"prefer-no-scatter", "PreferScatter", "false",713 "Prefer no scatter instructions">;714 715def TuningPrefer128Bit716 : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",717 "Prefer 128-bit AVX instructions">;718 719def TuningPrefer256Bit720 : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",721 "Prefer 256-bit AVX instructions">;722 723def TuningAllowLight256Bit724 : SubtargetFeature<"allow-light-256-bit", "AllowLight256Bit", "true",725 "Enable generation of 256-bit load/stores even if we prefer 128-bit">;726 727def TuningPreferMaskRegisters728 : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true",729 "Prefer AVX512 mask registers over PTEST/MOVMSK">;730 731def TuningFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",732 "Indicates that the BEXTR instruction is implemented as a single uop "733 "with good throughput">;734 735// Combine vector math operations with shuffles into horizontal math736// instructions if a CPU implements horizontal operations (introduced with737// SSE3) with better latency/throughput than the alternative sequence.738def TuningFastHorizontalOps739 : SubtargetFeature<740 "fast-hops", "HasFastHorizontalOps", "true",741 "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "742 "normal vector instructions with shuffles">;743 744def TuningFastScalarShiftMasks745 : SubtargetFeature<746 "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",747 "Prefer a left/right scalar logical shift pair over a shift+and pair">;748 749def TuningFastVectorShiftMasks750 : SubtargetFeature<751 "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",752 "Prefer a left/right vector logical shift pair over a shift+and pair">;753 754def TuningFastMOVBE755 : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true",756 "Prefer a movbe over a single-use load + bswap / single-use bswap + store">;757 758def TuningFastImm16759 : SubtargetFeature<"fast-imm16", "HasFastImm16", "true",760 "Prefer a i16 instruction with i16 immediate over extension to i32">;761 762def TuningUseSLMArithCosts763 : SubtargetFeature<"use-slm-arith-costs", "UseSLMArithCosts", "true",764 "Use Silvermont specific arithmetic costs">;765 766def TuningUseGLMDivSqrtCosts767 : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",768 "Use Goldmont specific floating point div/sqrt costs">;769 770// Starting with Redwood Cove architecture, the branch has branch taken hint771// (i.e., instruction prefix 3EH).772def TuningBranchHint: SubtargetFeature<"branch-hint", "HasBranchHint", "true",773 "Target has branch hint feature">;774 775//===----------------------------------------------------------------------===//776// X86 CPU Families777// TODO: Remove these - use general tuning features to determine codegen.778//===----------------------------------------------------------------------===//779 780// Bonnell781def ProcIntelAtom : SubtargetFeature<"", "IsAtom", "true", "Is Intel Atom processor">;782 783//===----------------------------------------------------------------------===//784// Register File Description785//===----------------------------------------------------------------------===//786 787include "X86RegisterInfo.td"788include "X86RegisterBanks.td"789 790//===----------------------------------------------------------------------===//791// Instruction Descriptions792//===----------------------------------------------------------------------===//793 794include "X86Schedule.td"795include "X86InstrInfo.td"796include "X86SchedPredicates.td"797 798defm : RemapAllTargetPseudoPointerOperands<x86_ptr_rc>;799 800def X86InstrInfo : InstrInfo;801 802//===----------------------------------------------------------------------===//803// X86 Scheduler Models804//===----------------------------------------------------------------------===//805 806include "X86ScheduleAtom.td"807include "X86SchedSandyBridge.td"808include "X86SchedHaswell.td"809include "X86SchedBroadwell.td"810include "X86ScheduleSLM.td"811include "X86ScheduleZnver1.td"812include "X86ScheduleZnver2.td"813include "X86ScheduleZnver3.td"814include "X86ScheduleZnver4.td"815include "X86ScheduleBdVer2.td"816include "X86ScheduleBtVer2.td"817include "X86SchedSkylakeClient.td"818include "X86SchedSkylakeServer.td"819include "X86SchedIceLake.td"820include "X86SchedAlderlakeP.td"821include "X86SchedLunarlakeP.td"822include "X86SchedSapphireRapids.td"823 824//===----------------------------------------------------------------------===//825// X86 Processor Feature Lists826//===----------------------------------------------------------------------===//827 828def ProcessorFeatures {829 // x86-64 micro-architecture levels: x86-64 and x86-64-v[234]830 list<SubtargetFeature> X86_64V1Features = [831 FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX, FeatureSSE2,832 FeatureFXSR, FeatureNOPL, FeatureX86_64,833 ];834 list<SubtargetFeature> X86_64V1Tuning = [835 TuningMacroFusion,836 TuningSlow3OpsLEA,837 TuningSlowDivide64,838 TuningSlowIncDec,839 TuningInsertVZEROUPPER840 ];841 842 list<SubtargetFeature> X86_64V2Features = !listconcat(X86_64V1Features, [843 FeatureCX16, FeatureLAHFSAHF64, FeatureCRC32, FeaturePOPCNT,844 FeatureSSE42845 ]);846 list<SubtargetFeature> X86_64V2Tuning = [847 TuningMacroFusion,848 TuningSlow3OpsLEA,849 TuningSlowDivide64,850 TuningSlowUAMem32,851 TuningFastScalarFSQRT,852 TuningFastSHLDRotate,853 TuningFast15ByteNOP,854 TuningPOPCNTFalseDeps,855 TuningInsertVZEROUPPER856 ];857 858 list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [859 FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT,860 FeatureMOVBE, FeatureXSAVE861 ]);862 list<SubtargetFeature> X86_64V3Tuning = [863 TuningMacroFusion,864 TuningSlow3OpsLEA,865 TuningSlowDivide64,866 TuningFastScalarFSQRT,867 TuningFastSHLDRotate,868 TuningFast15ByteNOP,869 TuningFastVariableCrossLaneShuffle,870 TuningFastVariablePerLaneShuffle,871 TuningPOPCNTFalseDeps,872 TuningLZCNTFalseDeps,873 TuningInsertVZEROUPPER,874 TuningAllowLight256Bit875 ];876 877 list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [878 FeatureBWI,879 FeatureCDI,880 FeatureDQI,881 FeatureVLX,882 ]);883 list<SubtargetFeature> X86_64V4Tuning = [884 TuningMacroFusion,885 TuningSlow3OpsLEA,886 TuningSlowDivide64,887 TuningFastScalarFSQRT,888 TuningFastVectorFSQRT,889 TuningFastSHLDRotate,890 TuningFast15ByteNOP,891 TuningFastVariableCrossLaneShuffle,892 TuningFastVariablePerLaneShuffle,893 TuningPrefer256Bit,894 TuningFastGather,895 TuningPOPCNTFalseDeps,896 TuningInsertVZEROUPPER,897 TuningAllowLight256Bit898 ];899 900 // Nehalem901 list<SubtargetFeature> NHMFeatures = X86_64V2Features;902 list<SubtargetFeature> NHMTuning = [TuningMacroFusion,903 TuningSlowDivide64,904 TuningInsertVZEROUPPER,905 TuningNoDomainDelayMov];906 907 // Westmere908 list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];909 list<SubtargetFeature> WSMTuning = NHMTuning;910 list<SubtargetFeature> WSMFeatures =911 !listconcat(NHMFeatures, WSMAdditionalFeatures);912 913 // Sandybridge914 list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,915 FeatureXSAVE,916 FeatureXSAVEOPT];917 list<SubtargetFeature> SNBTuning = [TuningMacroFusion,918 TuningSlow3OpsLEA,919 TuningSlowDivide64,920 TuningSlowUAMem32,921 TuningFastScalarFSQRT,922 TuningFastSHLDRotate,923 TuningFast15ByteNOP,924 TuningPOPCNTFalseDeps,925 TuningInsertVZEROUPPER,926 TuningNoDomainDelayMov];927 list<SubtargetFeature> SNBFeatures =928 !listconcat(WSMFeatures, SNBAdditionalFeatures);929 930 // Ivybridge931 list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,932 FeatureF16C,933 FeatureFSGSBase];934 list<SubtargetFeature> IVBTuning = SNBTuning;935 list<SubtargetFeature> IVBFeatures =936 !listconcat(SNBFeatures, IVBAdditionalFeatures);937 938 // Haswell939 list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,940 FeatureBMI,941 FeatureBMI2,942 FeatureERMSB,943 FeatureFMA,944 FeatureINVPCID,945 FeatureLZCNT,946 FeatureMOVBE];947 list<SubtargetFeature> HSWTuning = [TuningMacroFusion,948 TuningSlow3OpsLEA,949 TuningSlowDivide64,950 TuningFastScalarFSQRT,951 TuningFastSHLDRotate,952 TuningFast15ByteNOP,953 TuningFastVariableCrossLaneShuffle,954 TuningFastVariablePerLaneShuffle,955 TuningPOPCNTFalseDeps,956 TuningLZCNTFalseDeps,957 TuningInsertVZEROUPPER,958 TuningAllowLight256Bit,959 TuningNoDomainDelayMov,960 TuningNoDomainDelayShuffle];961 list<SubtargetFeature> HSWFeatures =962 !listconcat(IVBFeatures, HSWAdditionalFeatures);963 964 // Broadwell965 list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,966 FeatureRDSEED,967 FeaturePRFCHW];968 list<SubtargetFeature> BDWTuning = HSWTuning;969 list<SubtargetFeature> BDWFeatures =970 !listconcat(HSWFeatures, BDWAdditionalFeatures);971 972 // Skylake973 list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,974 FeatureXSAVEC,975 FeatureXSAVES,976 FeatureCLFLUSHOPT];977 list<SubtargetFeature> SKLTuning = [TuningFastGather,978 TuningMacroFusion,979 TuningSlow3OpsLEA,980 TuningSlowDivide64,981 TuningFastScalarFSQRT,982 TuningFastVectorFSQRT,983 TuningFastSHLDRotate,984 TuningFast15ByteNOP,985 TuningFastVariableCrossLaneShuffle,986 TuningFastVariablePerLaneShuffle,987 TuningPOPCNTFalseDeps,988 TuningInsertVZEROUPPER,989 TuningAllowLight256Bit,990 TuningNoDomainDelayMov,991 TuningNoDomainDelayShuffle,992 TuningNoDomainDelayBlend];993 list<SubtargetFeature> SKLFeatures =994 !listconcat(BDWFeatures, SKLAdditionalFeatures);995 996 // Skylake-AVX512997 list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES,998 FeatureXSAVEC,999 FeatureXSAVES,1000 FeatureCLFLUSHOPT,1001 FeatureAVX512,1002 FeatureCDI,1003 FeatureDQI,1004 FeatureBWI,1005 FeatureVLX,1006 FeaturePKU,1007 FeatureCLWB];1008 list<SubtargetFeature> SKXTuning = [TuningFastGather,1009 TuningMacroFusion,1010 TuningSlow3OpsLEA,1011 TuningSlowDivide64,1012 TuningFastScalarFSQRT,1013 TuningFastVectorFSQRT,1014 TuningFastSHLDRotate,1015 TuningFast15ByteNOP,1016 TuningFastVariableCrossLaneShuffle,1017 TuningFastVariablePerLaneShuffle,1018 TuningPrefer256Bit,1019 TuningPOPCNTFalseDeps,1020 TuningInsertVZEROUPPER,1021 TuningAllowLight256Bit,1022 TuningPreferShiftShuffle,1023 TuningNoDomainDelayMov,1024 TuningNoDomainDelayShuffle,1025 TuningNoDomainDelayBlend,1026 TuningFastImmVectorShift];1027 list<SubtargetFeature> SKXFeatures =1028 !listconcat(BDWFeatures, SKXAdditionalFeatures);1029 1030 // Cascadelake1031 list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];1032 list<SubtargetFeature> CLXTuning = SKXTuning;1033 list<SubtargetFeature> CLXFeatures =1034 !listconcat(SKXFeatures, CLXAdditionalFeatures);1035 1036 // Cooperlake1037 list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];1038 list<SubtargetFeature> CPXTuning = SKXTuning;1039 list<SubtargetFeature> CPXFeatures =1040 !listconcat(CLXFeatures, CPXAdditionalFeatures);1041 1042 // Cannonlake1043 list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,1044 FeatureCDI,1045 FeatureDQI,1046 FeatureBWI,1047 FeatureVLX,1048 FeaturePKU,1049 FeatureVBMI,1050 FeatureIFMA,1051 FeatureSHA];1052 list<SubtargetFeature> CNLTuning = [TuningFastGather,1053 TuningMacroFusion,1054 TuningSlow3OpsLEA,1055 TuningSlowDivide64,1056 TuningFastScalarFSQRT,1057 TuningFastVectorFSQRT,1058 TuningFastSHLDRotate,1059 TuningFast15ByteNOP,1060 TuningFastVariableCrossLaneShuffle,1061 TuningFastVariablePerLaneShuffle,1062 TuningPrefer256Bit,1063 TuningInsertVZEROUPPER,1064 TuningAllowLight256Bit,1065 TuningNoDomainDelayMov,1066 TuningNoDomainDelayShuffle,1067 TuningNoDomainDelayBlend,1068 TuningFastImmVectorShift];1069 list<SubtargetFeature> CNLFeatures =1070 !listconcat(SKLFeatures, CNLAdditionalFeatures);1071 1072 // Icelake1073 list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,1074 FeatureVAES,1075 FeatureVBMI2,1076 FeatureVNNI,1077 FeatureVPCLMULQDQ,1078 FeatureVPOPCNTDQ,1079 FeatureGFNI,1080 FeatureRDPID,1081 FeatureFSRM];1082 list<SubtargetFeature> ICLTuning = [TuningFastGather,1083 TuningMacroFusion,1084 TuningSlowDivide64,1085 TuningFastScalarFSQRT,1086 TuningFastVectorFSQRT,1087 TuningFastSHLDRotate,1088 TuningFast15ByteNOP,1089 TuningFastVariableCrossLaneShuffle,1090 TuningFastVariablePerLaneShuffle,1091 TuningPrefer256Bit,1092 TuningInsertVZEROUPPER,1093 TuningAllowLight256Bit,1094 TuningNoDomainDelayMov,1095 TuningNoDomainDelayShuffle,1096 TuningNoDomainDelayBlend,1097 TuningFastImmVectorShift];1098 list<SubtargetFeature> ICLFeatures =1099 !listconcat(CNLFeatures, ICLAdditionalFeatures);1100 1101 // Icelake Server1102 list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG,1103 FeatureCLWB,1104 FeatureWBNOINVD];1105 list<SubtargetFeature> ICXTuning = ICLTuning;1106 list<SubtargetFeature> ICXFeatures =1107 !listconcat(ICLFeatures, ICXAdditionalFeatures);1108 1109 // Tigerlake1110 list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,1111 FeatureCLWB,1112 FeatureMOVDIRI,1113 FeatureMOVDIR64B,1114 FeatureSHSTK];1115 list<SubtargetFeature> TGLTuning = ICLTuning;1116 list<SubtargetFeature> TGLFeatures =1117 !listconcat(ICLFeatures, TGLAdditionalFeatures );1118 1119 // Sapphirerapids1120 list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,1121 FeatureAMXINT8,1122 FeatureAMXBF16,1123 FeatureBF16,1124 FeatureSERIALIZE,1125 FeatureCLDEMOTE,1126 FeatureWAITPKG,1127 FeaturePTWRITE,1128 FeatureFP16,1129 FeatureAVXVNNI,1130 FeatureTSXLDTRK,1131 FeatureENQCMD,1132 FeatureSHSTK,1133 FeatureMOVDIRI,1134 FeatureMOVDIR64B,1135 FeatureUINTR];1136 list<SubtargetFeature> SPRAdditionalTuning = [TuningMULCFalseDeps,1137 TuningPERMFalseDeps,1138 TuningRANGEFalseDeps,1139 TuningGETMANTFalseDeps,1140 TuningMULLQFalseDeps];1141 list<SubtargetFeature> SPRTuning = !listconcat(ICXTuning, SPRAdditionalTuning);1142 list<SubtargetFeature> SPRFeatures =1143 !listconcat(ICXFeatures, SPRAdditionalFeatures);1144 1145 // Graniterapids1146 list<SubtargetFeature> GNRAdditionalFeatures = [FeatureAMXFP16,1147 FeaturePREFETCHI];1148 list<SubtargetFeature> GNRFeatures =1149 !listconcat(SPRFeatures, GNRAdditionalFeatures);1150 list<SubtargetFeature> GNRAdditionalTuning = [TuningBranchHint];1151 list<SubtargetFeature> GNRTuning = !listconcat(SPRTuning, GNRAdditionalTuning);1152 1153 // Graniterapids D1154 list<SubtargetFeature> GNRDAdditionalFeatures = [FeatureAMXCOMPLEX];1155 list<SubtargetFeature> GNRDFeatures =1156 !listconcat(GNRFeatures, GNRDAdditionalFeatures);1157 1158 // Diamond Rapids1159 list<SubtargetFeature> DMRAdditionalFeatures = [FeatureAVX10_2,1160 FeatureSM4,1161 FeatureCMPCCXADD,1162 FeatureAVXIFMA,1163 FeatureAVXNECONVERT,1164 FeatureAVXVNNIINT8,1165 FeatureAVXVNNIINT16,1166 FeatureSHA512,1167 FeatureSM3,1168 FeatureEGPR,1169 FeatureZU,1170 FeatureCCMP,1171 FeaturePush2Pop2,1172 FeaturePPX,1173 FeatureNDD,1174 FeatureNF,1175 FeatureMOVRS,1176 FeatureAMXMOVRS,1177 FeatureAMXAVX512,1178 FeatureAMXFP8,1179 FeatureAMXTF32];1180 list<SubtargetFeature> DMRFeatures =1181 !listconcat(GNRDFeatures, DMRAdditionalFeatures);1182 1183 // Atom1184 list<SubtargetFeature> AtomFeatures = [FeatureX87,1185 FeatureCX8,1186 FeatureCMOV,1187 FeatureMMX,1188 FeatureSSSE3,1189 FeatureFXSR,1190 FeatureNOPL,1191 FeatureX86_64,1192 FeatureCX16,1193 FeatureMOVBE,1194 FeatureLAHFSAHF64];1195 list<SubtargetFeature> AtomTuning = [ProcIntelAtom,1196 TuningSlowUAMem16,1197 TuningLEAForSP,1198 TuningSlowDivide32,1199 TuningSlowDivide64,1200 TuningSlowTwoMemOps,1201 TuningFastImm16,1202 TuningLEAUsesAG,1203 TuningPadShortFunctions,1204 TuningInsertVZEROUPPER,1205 TuningNoDomainDelay];1206 1207 // Silvermont1208 list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,1209 FeatureCRC32,1210 FeaturePOPCNT,1211 FeaturePCLMUL,1212 FeaturePRFCHW,1213 FeatureRDRAND];1214 list<SubtargetFeature> SLMTuning = [TuningUseSLMArithCosts,1215 TuningSlowTwoMemOps,1216 TuningSlowLEA,1217 TuningSlowIncDec,1218 TuningSlowDivide64,1219 TuningSlowPMULLD,1220 TuningFast7ByteNOP,1221 TuningFastMOVBE,1222 TuningFastImm16,1223 TuningPOPCNTFalseDeps,1224 TuningInsertVZEROUPPER,1225 TuningNoDomainDelay];1226 list<SubtargetFeature> SLMFeatures =1227 !listconcat(AtomFeatures, SLMAdditionalFeatures);1228 1229 // Goldmont1230 list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,1231 FeatureSHA,1232 FeatureRDSEED,1233 FeatureXSAVE,1234 FeatureXSAVEOPT,1235 FeatureXSAVEC,1236 FeatureXSAVES,1237 FeatureCLFLUSHOPT,1238 FeatureFSGSBase];1239 list<SubtargetFeature> GLMTuning = [TuningUseGLMDivSqrtCosts,1240 TuningSlowTwoMemOps,1241 TuningSlowLEA,1242 TuningSlowIncDec,1243 TuningFastMOVBE,1244 TuningFastImm16,1245 TuningPOPCNTFalseDeps,1246 TuningInsertVZEROUPPER,1247 TuningNoDomainDelay];1248 list<SubtargetFeature> GLMFeatures =1249 !listconcat(SLMFeatures, GLMAdditionalFeatures);1250 1251 // Goldmont Plus1252 list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,1253 FeatureRDPID];1254 list<SubtargetFeature> GLPTuning = [TuningUseGLMDivSqrtCosts,1255 TuningSlowTwoMemOps,1256 TuningSlowLEA,1257 TuningSlowIncDec,1258 TuningFastMOVBE,1259 TuningFastImm16,1260 TuningInsertVZEROUPPER,1261 TuningNoDomainDelay];1262 list<SubtargetFeature> GLPFeatures =1263 !listconcat(GLMFeatures, GLPAdditionalFeatures);1264 1265 // Tremont1266 list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,1267 FeatureGFNI];1268 list<SubtargetFeature> TRMTuning = GLPTuning;1269 list<SubtargetFeature> TRMFeatures =1270 !listconcat(GLPFeatures, TRMAdditionalFeatures);1271 1272 // Alderlake1273 list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE,1274 FeaturePCONFIG,1275 FeatureSHSTK,1276 FeatureWIDEKL,1277 FeatureINVPCID,1278 FeatureADX,1279 FeatureFMA,1280 FeatureVAES,1281 FeatureVPCLMULQDQ,1282 FeatureF16C,1283 FeatureBMI,1284 FeatureBMI2,1285 FeatureLZCNT,1286 FeatureAVXVNNI,1287 FeaturePKU,1288 FeatureHRESET,1289 FeatureMOVDIRI,1290 FeatureMOVDIR64B,1291 FeatureWAITPKG];1292 list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps,1293 TuningPreferMovmskOverVTest,1294 TuningFastImmVectorShift];1295 list<SubtargetFeature> ADLRemoveTuning = [TuningPOPCNTFalseDeps];1296 list<SubtargetFeature> ADLTuning =1297 !listremove(!listconcat(SKLTuning, ADLAdditionalTuning), ADLRemoveTuning);1298 list<SubtargetFeature> ADLFeatures =1299 !listconcat(TRMFeatures, ADLAdditionalFeatures);1300 1301 // Gracemont1302 list<SubtargetFeature> GRTTuning = [TuningMacroFusion,1303 TuningSlow3OpsLEA,1304 TuningFastScalarFSQRT,1305 TuningFastVectorFSQRT,1306 TuningFast15ByteNOP,1307 TuningFastVariablePerLaneShuffle,1308 TuningPOPCNTFalseDeps,1309 TuningInsertVZEROUPPER];1310 1311 // Arrowlake1312 list<SubtargetFeature> ARLAdditionalFeatures = [FeatureCMPCCXADD,1313 FeatureAVXIFMA,1314 FeatureAVXNECONVERT,1315 FeatureENQCMD,1316 FeatureUINTR,1317 FeatureAVXVNNIINT8];1318 list<SubtargetFeature> ARLFeatures =1319 !listconcat(ADLFeatures, ARLAdditionalFeatures);1320 1321 // Sierraforest1322 list<SubtargetFeature> SRFAdditionalFeatures = [FeatureCLDEMOTE];1323 list<SubtargetFeature> SRFFeatures =1324 !listconcat(ARLFeatures, SRFAdditionalFeatures);1325 1326 // Arrowlake S1327 list<SubtargetFeature> ARLSAdditionalFeatures = [FeatureAVXVNNIINT16,1328 FeatureSHA512,1329 FeatureSM3,1330 FeatureSM4];1331 list<SubtargetFeature> ARLSFeatures =1332 !listconcat(ARLFeatures, ARLSAdditionalFeatures);1333 1334 // Pantherlake1335 list<SubtargetFeature> PTLFeatures =1336 !listremove(ARLSFeatures, [FeatureWIDEKL]);1337 1338 // Novalake1339 list<SubtargetFeature> NVLAdditionalFeatures = [FeatureAVX10_2,1340 FeatureMOVRS,1341 FeatureEGPR,1342 FeaturePush2Pop2,1343 FeaturePPX,1344 FeatureNF,1345 FeatureNDD,1346 FeatureZU,1347 FeatureCCMP,1348 FeaturePREFETCHI];1349 list<SubtargetFeature> NVLFeatures =1350 !listconcat(PTLFeatures, NVLAdditionalFeatures);1351 1352 // Clearwaterforest1353 list<SubtargetFeature> CWFAdditionalFeatures = [FeaturePREFETCHI,1354 FeatureAVXVNNIINT16,1355 FeatureSHA512,1356 FeatureSM3,1357 FeatureSM4,1358 FeatureUSERMSR];1359 list<SubtargetFeature> CWFFeatures =1360 !listremove(!listconcat(SRFFeatures, CWFAdditionalFeatures), [FeatureWIDEKL]);1361 1362 // Knights Landing1363 list<SubtargetFeature> KNLFeatures = [FeatureX87,1364 FeatureCX8,1365 FeatureCMOV,1366 FeatureMMX,1367 FeatureFXSR,1368 FeatureNOPL,1369 FeatureX86_64,1370 FeatureCX16,1371 FeatureCRC32,1372 FeaturePOPCNT,1373 FeaturePCLMUL,1374 FeatureXSAVE,1375 FeatureXSAVEOPT,1376 FeatureLAHFSAHF64,1377 FeatureAES,1378 FeatureRDRAND,1379 FeatureF16C,1380 FeatureFSGSBase,1381 FeatureAVX512,1382 FeatureCDI,1383 FeatureADX,1384 FeatureRDSEED,1385 FeatureMOVBE,1386 FeatureLZCNT,1387 FeatureBMI,1388 FeatureBMI2,1389 FeatureFMA,1390 FeaturePRFCHW];1391 list<SubtargetFeature> KNLTuning = [TuningSlowDivide64,1392 TuningSlow3OpsLEA,1393 TuningSlowIncDec,1394 TuningSlowTwoMemOps,1395 TuningPreferMaskRegisters,1396 TuningFastGather,1397 TuningFastMOVBE,1398 TuningFastImm16,1399 TuningSlowPMADDWD];1400 // TODO Add AVX5124FMAPS/AVX5124VNNIW features1401 list<SubtargetFeature> KNMFeatures =1402 !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);1403 1404 // Barcelona1405 list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,1406 FeatureCX8,1407 FeatureSSE4A,1408 FeatureFXSR,1409 FeatureNOPL,1410 FeatureCX16,1411 FeaturePRFCHW,1412 FeatureLZCNT,1413 FeaturePOPCNT,1414 FeatureLAHFSAHF64,1415 FeatureCMOV,1416 FeatureX86_64];1417 list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks,1418 TuningSlowDivide64,1419 TuningSlowSHLD,1420 TuningSBBDepBreaking,1421 TuningInsertVZEROUPPER];1422 1423 // Bobcat1424 list<SubtargetFeature> BtVer1Features = [FeatureX87,1425 FeatureCX8,1426 FeatureCMOV,1427 FeatureMMX,1428 FeatureSSSE3,1429 FeatureSSE4A,1430 FeatureFXSR,1431 FeatureNOPL,1432 FeatureX86_64,1433 FeatureCX16,1434 FeaturePRFCHW,1435 FeatureLZCNT,1436 FeaturePOPCNT,1437 FeatureLAHFSAHF64];1438 list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP,1439 TuningFastScalarShiftMasks,1440 TuningFastVectorShiftMasks,1441 TuningSlowDivide64,1442 TuningSlowSHLD,1443 TuningFastImm16,1444 TuningSBBDepBreaking,1445 TuningInsertVZEROUPPER];1446 1447 // Jaguar1448 list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,1449 FeatureAES,1450 FeatureCRC32,1451 FeaturePCLMUL,1452 FeatureBMI,1453 FeatureF16C,1454 FeatureMOVBE,1455 FeatureXSAVE,1456 FeatureXSAVEOPT];1457 list<SubtargetFeature> BtVer2Tuning = [TuningFastLZCNT,1458 TuningFastBEXTR,1459 TuningFastHorizontalOps,1460 TuningFast15ByteNOP,1461 TuningFastScalarShiftMasks,1462 TuningFastVectorShiftMasks,1463 TuningFastMOVBE,1464 TuningFastImm16,1465 TuningSBBDepBreaking,1466 TuningSlowDivide64,1467 TuningSlowSHLD];1468 list<SubtargetFeature> BtVer2Features =1469 !listconcat(BtVer1Features, BtVer2AdditionalFeatures);1470 1471 // Bulldozer1472 list<SubtargetFeature> BdVer1Features = [FeatureX87,1473 FeatureCX8,1474 FeatureCMOV,1475 FeatureXOP,1476 FeatureX86_64,1477 FeatureCX16,1478 FeatureAES,1479 FeatureCRC32,1480 FeaturePRFCHW,1481 FeaturePCLMUL,1482 FeatureMMX,1483 FeatureFXSR,1484 FeatureNOPL,1485 FeatureLZCNT,1486 FeaturePOPCNT,1487 FeatureXSAVE,1488 FeatureLWP,1489 FeatureLAHFSAHF64];1490 list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD,1491 TuningSlowDivide64,1492 TuningFast11ByteNOP,1493 TuningFastScalarShiftMasks,1494 TuningBranchFusion,1495 TuningSBBDepBreaking,1496 TuningInsertVZEROUPPER];1497 1498 // PileDriver1499 list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,1500 FeatureBMI,1501 FeatureTBM,1502 FeatureFMA];1503 list<SubtargetFeature> BdVer2AdditionalTuning = [TuningFastBEXTR,1504 TuningFastMOVBE];1505 list<SubtargetFeature> BdVer2Tuning =1506 !listconcat(BdVer1Tuning, BdVer2AdditionalTuning);1507 list<SubtargetFeature> BdVer2Features =1508 !listconcat(BdVer1Features, BdVer2AdditionalFeatures);1509 1510 // Steamroller1511 list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,1512 FeatureFSGSBase];1513 list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning;1514 list<SubtargetFeature> BdVer3Features =1515 !listconcat(BdVer2Features, BdVer3AdditionalFeatures);1516 1517 // Excavator1518 list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,1519 FeatureBMI2,1520 FeatureMOVBE,1521 FeatureRDRAND,1522 FeatureMWAITX];1523 list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning;1524 list<SubtargetFeature> BdVer4Features =1525 !listconcat(BdVer3Features, BdVer4AdditionalFeatures);1526 1527 1528 // AMD Zen Processors common ISAs1529 list<SubtargetFeature> ZNFeatures = [FeatureADX,1530 FeatureAES,1531 FeatureAVX2,1532 FeatureBMI,1533 FeatureBMI2,1534 FeatureCLFLUSHOPT,1535 FeatureCLZERO,1536 FeatureCMOV,1537 FeatureX86_64,1538 FeatureCX16,1539 FeatureCRC32,1540 FeatureF16C,1541 FeatureFMA,1542 FeatureFSGSBase,1543 FeatureFXSR,1544 FeatureNOPL,1545 FeatureLAHFSAHF64,1546 FeatureLZCNT,1547 FeatureMMX,1548 FeatureMOVBE,1549 FeatureMWAITX,1550 FeaturePCLMUL,1551 FeaturePOPCNT,1552 FeaturePRFCHW,1553 FeatureRDRAND,1554 FeatureRDSEED,1555 FeatureSHA,1556 FeatureSSE4A,1557 FeatureX87,1558 FeatureXSAVE,1559 FeatureXSAVEC,1560 FeatureXSAVEOPT,1561 FeatureXSAVES];1562 list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,1563 TuningFastBEXTR,1564 TuningFast15ByteNOP,1565 TuningBranchFusion,1566 TuningFastScalarFSQRT,1567 TuningFastVectorFSQRT,1568 TuningFastScalarShiftMasks,1569 TuningFastVariablePerLaneShuffle,1570 TuningFastMOVBE,1571 TuningFastImm16,1572 TuningSlowDivide64,1573 TuningSlowSHLD,1574 TuningSBBDepBreaking,1575 TuningInsertVZEROUPPER,1576 TuningAllowLight256Bit];1577 list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,1578 FeatureRDPID,1579 FeatureRDPRU,1580 FeatureWBNOINVD];1581 list<SubtargetFeature> ZN2Tuning = ZNTuning;1582 list<SubtargetFeature> ZN2Features =1583 !listconcat(ZNFeatures, ZN2AdditionalFeatures);1584 list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,1585 FeatureINVPCID,1586 FeaturePKU,1587 FeatureVAES,1588 FeatureVPCLMULQDQ];1589 list<SubtargetFeature> ZN3AdditionalTuning = [TuningMacroFusion];1590 list<SubtargetFeature> ZN3Tuning =1591 !listremove(!listconcat(ZN2Tuning, ZN3AdditionalTuning), [TuningSlowSHLD]);1592 list<SubtargetFeature> ZN3Features =1593 !listconcat(ZN2Features, ZN3AdditionalFeatures);1594 1595 list<SubtargetFeature> ZN4AdditionalTuning = [TuningFastDPWSSD];1596 list<SubtargetFeature> ZN4Tuning =1597 !listconcat(ZN3Tuning, ZN4AdditionalTuning);1598 list<SubtargetFeature> ZN4AdditionalFeatures = [FeatureAVX512,1599 FeatureCDI,1600 FeatureDQI,1601 FeatureBWI,1602 FeatureVLX,1603 FeatureVBMI,1604 FeatureVBMI2,1605 FeatureIFMA,1606 FeatureVNNI,1607 FeatureBITALG,1608 FeatureGFNI,1609 FeatureBF16,1610 FeatureSHSTK,1611 FeatureVPOPCNTDQ];1612 list<SubtargetFeature> ZN4Features =1613 !listconcat(ZN3Features, ZN4AdditionalFeatures);1614 1615 list<SubtargetFeature> ZN5Tuning = ZN4Tuning;1616 list<SubtargetFeature> ZN5AdditionalFeatures = [FeatureMOVDIRI,1617 FeatureMOVDIR64B,1618 FeatureVP2INTERSECT,1619 FeaturePREFETCHI,1620 FeatureAVXVNNI1621 ];1622 list<SubtargetFeature> ZN5Features =1623 !listconcat(ZN4Features, ZN5AdditionalFeatures);1624}1625 1626//===----------------------------------------------------------------------===//1627// X86 processors supported.1628//===----------------------------------------------------------------------===//1629 1630class Proc<string Name, list<SubtargetFeature> Features,1631 list<SubtargetFeature> TuneFeatures>1632 : ProcessorModel<Name, GenericModel, Features, TuneFeatures>;1633 1634class ProcModel<string Name, SchedMachineModel Model,1635 list<SubtargetFeature> Features,1636 list<SubtargetFeature> TuneFeatures>1637 : ProcessorModel<Name, Model, Features, TuneFeatures>;1638 1639// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled1640// if i386/i486 is specifically requested.1641// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget1642// constructor checks that any CPU used in 64-bit mode has FeatureX86_641643// enabled. It has no effect on code generation.1644// NOTE: As a default tuning, "generic" aims to produce code optimized for the1645// most common X86 processors. The tunings might be changed over time. It is1646// recommended to use "tune-cpu"="x86-64" in function attribute for consistency.1647def : ProcModel<"generic", SandyBridgeModel,1648 [FeatureX87, FeatureCX8, FeatureX86_64],1649 [TuningSlow3OpsLEA,1650 TuningSlowDivide64,1651 TuningMacroFusion,1652 TuningFastScalarFSQRT,1653 TuningFast15ByteNOP,1654 TuningInsertVZEROUPPER]>;1655 1656def : Proc<"i386", [FeatureX87],1657 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1658def : Proc<"i486", [FeatureX87],1659 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1660def : Proc<"i586", [FeatureX87, FeatureCX8],1661 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1662def : Proc<"pentium", [FeatureX87, FeatureCX8],1663 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1664foreach P = ["pentium-mmx", "pentium_mmx"] in {1665 def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX],1666 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1667}1668def : Proc<"i686", [FeatureX87, FeatureCX8, FeatureCMOV],1669 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1670foreach P = ["pentiumpro", "pentium_pro"] in {1671 def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, FeatureNOPL],1672 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1673}1674foreach P = ["pentium2", "pentium_ii"] in {1675 def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX, FeatureCMOV,1676 FeatureFXSR, FeatureNOPL],1677 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1678}1679foreach P = ["pentium3", "pentium3m", "pentium_iii_no_xmm_regs", "pentium_iii"] in {1680 def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX,1681 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],1682 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1683}1684 1685// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.1686// The intent is to enable it for pentium4 which is the current default1687// processor in a vanilla 32-bit clang compilation when no specific1688// architecture is specified. This generally gives a nice performance1689// increase on silvermont, with largely neutral behavior on other1690// contemporary large core processors.1691// pentium-m, pentium4m, prescott and nocona are included as a preventative1692// measure to avoid performance surprises, in case clang's default cpu1693// changes slightly.1694 1695foreach P = ["pentium_m", "pentium-m"] in {1696def : ProcModel<P, GenericPostRAModel,1697 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,1698 FeatureFXSR, FeatureNOPL, FeatureCMOV],1699 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1700}1701 1702foreach P = ["pentium4", "pentium4m", "pentium_4"] in {1703 def : ProcModel<P, GenericPostRAModel,1704 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,1705 FeatureFXSR, FeatureNOPL, FeatureCMOV],1706 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1707}1708 1709// Intel Quark.1710def : Proc<"lakemont", [FeatureCX8],1711 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1712 1713// Intel Core Duo.1714def : ProcModel<"yonah", SandyBridgeModel,1715 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,1716 FeatureFXSR, FeatureNOPL, FeatureCMOV],1717 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1718 1719// NetBurst.1720foreach P = ["prescott", "pentium_4_sse3"] in {1721 def : ProcModel<P, GenericPostRAModel,1722 [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,1723 FeatureFXSR, FeatureNOPL, FeatureCMOV],1724 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1725}1726def : ProcModel<"nocona", GenericPostRAModel, [1727 FeatureX87,1728 FeatureCX8,1729 FeatureCMOV,1730 FeatureMMX,1731 FeatureSSE3,1732 FeatureFXSR,1733 FeatureNOPL,1734 FeatureX86_64,1735 FeatureCX16,1736],1737[1738 TuningSlowUAMem16,1739 TuningInsertVZEROUPPER1740]>;1741 1742// Intel Core 2 Solo/Duo.1743foreach P = ["core2", "core_2_duo_ssse3"] in {1744def : ProcModel<P, SandyBridgeModel, [1745 FeatureX87,1746 FeatureCX8,1747 FeatureCMOV,1748 FeatureMMX,1749 FeatureSSSE3,1750 FeatureFXSR,1751 FeatureNOPL,1752 FeatureX86_64,1753 FeatureCX16,1754 FeatureLAHFSAHF641755],1756[1757 TuningMacroFusion,1758 TuningSlowUAMem16,1759 TuningInsertVZEROUPPER1760]>;1761}1762foreach P = ["penryn", "core_2_duo_sse4_1"] in {1763def : ProcModel<P, SandyBridgeModel, [1764 FeatureX87,1765 FeatureCX8,1766 FeatureCMOV,1767 FeatureMMX,1768 FeatureSSE41,1769 FeatureFXSR,1770 FeatureNOPL,1771 FeatureX86_64,1772 FeatureCX16,1773 FeatureLAHFSAHF641774],1775[1776 TuningMacroFusion,1777 TuningSlowUAMem16,1778 TuningInsertVZEROUPPER1779]>;1780}1781 1782// Atom CPUs.1783foreach P = ["bonnell", "atom"] in {1784 def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,1785 ProcessorFeatures.AtomTuning>;1786}1787 1788foreach P = ["silvermont", "slm", "atom_sse4_2"] in {1789 def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures,1790 ProcessorFeatures.SLMTuning>;1791}1792 1793def : ProcModel<"atom_sse4_2_movbe", SLMModel, ProcessorFeatures.GLMFeatures,1794 ProcessorFeatures.SLMTuning>;1795def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,1796 ProcessorFeatures.GLMTuning>;1797foreach P = ["goldmont_plus", "goldmont-plus"] in {1798 def : ProcModel<P, SLMModel, ProcessorFeatures.GLPFeatures,1799 ProcessorFeatures.GLPTuning>;1800}1801def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,1802 ProcessorFeatures.TRMTuning>;1803 1804// "Arrandale" along with corei3 and corei51805foreach P = ["nehalem", "corei7", "core_i7_sse4_2"] in {1806 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,1807 ProcessorFeatures.NHMTuning>;1808}1809 1810// Westmere is the corei3/i5/i7 path from nehalem to sandybridge1811foreach P = ["westmere", "core_aes_pclmulqdq"] in {1812 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.WSMFeatures,1813 ProcessorFeatures.WSMTuning>;1814}1815 1816foreach P = ["sandybridge", "corei7-avx", "core_2nd_gen_avx"] in {1817 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures,1818 ProcessorFeatures.SNBTuning>;1819}1820 1821foreach P = ["ivybridge", "core-avx-i", "core_3rd_gen_avx"] in {1822 def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures,1823 ProcessorFeatures.IVBTuning>;1824}1825 1826foreach P = ["haswell", "core-avx2", "core_4th_gen_avx", "core_4th_gen_avx_tsx"] in {1827 def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures,1828 ProcessorFeatures.HSWTuning>;1829}1830 1831foreach P = ["broadwell", "core_5th_gen_avx", "core_5th_gen_avx_tsx"] in {1832 def : ProcModel<P, BroadwellModel, ProcessorFeatures.BDWFeatures,1833 ProcessorFeatures.BDWTuning>;1834}1835 1836def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures,1837 ProcessorFeatures.SKLTuning>;1838 1839// FIXME: define KNL scheduler model1840foreach P = ["knl", "mic_avx512"] in {1841 def : ProcModel<P, HaswellModel, ProcessorFeatures.KNLFeatures,1842 ProcessorFeatures.KNLTuning>;1843}1844def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures,1845 ProcessorFeatures.KNLTuning>;1846 1847foreach P = ["skylake-avx512", "skx", "skylake_avx512"] in {1848 def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures,1849 ProcessorFeatures.SKXTuning>;1850}1851 1852def : ProcModel<"cascadelake", SkylakeServerModel,1853 ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>;1854def : ProcModel<"cooperlake", SkylakeServerModel,1855 ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;1856def : ProcModel<"cannonlake", SkylakeServerModel,1857 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;1858foreach P = ["icelake-client", "icelake_client"] in {1859def : ProcModel<P, IceLakeModel,1860 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;1861}1862def : ProcModel<"rocketlake", IceLakeModel,1863 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;1864foreach P = ["icelake-server", "icelake_server"] in {1865def : ProcModel<P, IceLakeModel,1866 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;1867}1868def : ProcModel<"tigerlake", IceLakeModel,1869 ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;1870def : ProcModel<"sapphirerapids", SapphireRapidsModel,1871 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;1872def : ProcModel<"alderlake", AlderlakePModel,1873 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;1874// FIXME: Use Gracemont Schedule Model when it is ready.1875def : ProcModel<"gracemont", AlderlakePModel,1876 ProcessorFeatures.ADLFeatures, ProcessorFeatures.GRTTuning>;1877foreach P = ["sierraforest", "grandridge"] in {1878 def : ProcModel<P, AlderlakePModel, ProcessorFeatures.SRFFeatures,1879 ProcessorFeatures.GRTTuning>;1880}1881def : ProcModel<"raptorlake", AlderlakePModel,1882 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;1883def : ProcModel<"meteorlake", AlderlakePModel,1884 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;1885def : ProcModel<"arrowlake", AlderlakePModel,1886 ProcessorFeatures.ARLFeatures, ProcessorFeatures.ADLTuning>;1887foreach P = ["arrowlake-s", "arrowlake_s"] in {1888def : ProcModel<P, AlderlakePModel,1889 ProcessorFeatures.ARLSFeatures, ProcessorFeatures.ADLTuning>;1890}1891def : ProcModel<"lunarlake", LunarlakePModel, ProcessorFeatures.ARLSFeatures,1892 ProcessorFeatures.ADLTuning>;1893foreach P = ["pantherlake", "wildcatlake"] in {1894def : ProcModel<P, AlderlakePModel,1895 ProcessorFeatures.PTLFeatures, ProcessorFeatures.ADLTuning>;1896}1897def : ProcModel<"novalake", AlderlakePModel, ProcessorFeatures.NVLFeatures,1898 ProcessorFeatures.ADLTuning>;1899 1900def : ProcModel<"clearwaterforest", AlderlakePModel,1901 ProcessorFeatures.CWFFeatures, ProcessorFeatures.ADLTuning>;1902def : ProcModel<"emeraldrapids", SapphireRapidsModel,1903 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;1904def : ProcModel<"graniterapids", SapphireRapidsModel,1905 ProcessorFeatures.GNRFeatures, ProcessorFeatures.GNRTuning>;1906foreach P = ["graniterapids-d", "graniterapids_d"] in {1907def : ProcModel<P, SapphireRapidsModel,1908 ProcessorFeatures.GNRDFeatures, ProcessorFeatures.GNRTuning>;1909}1910def : ProcModel<"diamondrapids", SapphireRapidsModel,1911 ProcessorFeatures.DMRFeatures, ProcessorFeatures.GNRTuning>;1912 1913// AMD CPUs.1914 1915def : Proc<"k6", [FeatureX87, FeatureCX8, FeatureMMX],1916 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1917def : Proc<"k6-2", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],1918 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1919def : Proc<"k6-3", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],1920 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1921 1922foreach P = ["athlon", "athlon-tbird"] in {1923 def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX, FeaturePRFCHW,1924 FeatureNOPL],1925 [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1926}1927 1928foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {1929 def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV,1930 FeatureSSE1, FeatureMMX, FeaturePRFCHW, FeatureFXSR, FeatureNOPL],1931 [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1932}1933 1934foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {1935 def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2, FeatureMMX, FeaturePRFCHW,1936 FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV],1937 [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,1938 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;1939}1940 1941foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {1942 def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3, FeatureMMX, FeaturePRFCHW,1943 FeatureFXSR, FeatureNOPL, FeatureCX16, FeatureCMOV,1944 FeatureX86_64],1945 [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,1946 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;1947}1948 1949foreach P = ["amdfam10", "barcelona"] in {1950 def : Proc<P, ProcessorFeatures.BarcelonaFeatures,1951 ProcessorFeatures.BarcelonaTuning>;1952}1953 1954// Bobcat1955def : Proc<"btver1", ProcessorFeatures.BtVer1Features,1956 ProcessorFeatures.BtVer1Tuning>;1957// Jaguar1958def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features,1959 ProcessorFeatures.BtVer2Tuning>;1960 1961// Bulldozer1962def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features,1963 ProcessorFeatures.BdVer1Tuning>;1964// Piledriver1965def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features,1966 ProcessorFeatures.BdVer2Tuning>;1967// Steamroller1968// NOTE: BdVer2Model is only an approx model for Steamroller.1969def : ProcModel<"bdver3", BdVer2Model, ProcessorFeatures.BdVer3Features,1970 ProcessorFeatures.BdVer3Tuning>;1971// Excavator1972// NOTE: Znver1Model is only an approx model for Excavator (with AVX2).1973def : ProcModel<"bdver4", Znver1Model, ProcessorFeatures.BdVer4Features,1974 ProcessorFeatures.BdVer4Tuning>;1975 1976def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,1977 ProcessorFeatures.ZNTuning>;1978def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,1979 ProcessorFeatures.ZN2Tuning>;1980def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,1981 ProcessorFeatures.ZN3Tuning>;1982def : ProcModel<"znver4", Znver4Model, ProcessorFeatures.ZN4Features,1983 ProcessorFeatures.ZN4Tuning>;1984def : ProcModel<"znver5", Znver4Model, ProcessorFeatures.ZN5Features,1985 ProcessorFeatures.ZN5Tuning>;1986 1987def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],1988 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1989 1990def : Proc<"winchip-c6", [FeatureX87, FeatureMMX],1991 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1992def : Proc<"winchip2", [FeatureX87, FeatureMMX, FeaturePRFCHW],1993 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1994def : Proc<"c3", [FeatureX87, FeatureMMX, FeaturePRFCHW],1995 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1996def : Proc<"c3-2", [FeatureX87, FeatureCX8, FeatureMMX,1997 FeatureSSE1, FeatureFXSR, FeatureCMOV],1998 [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;1999 2000// We also provide a generic 64-bit specific x86 processor model which tries to2001// be good for modern chips without enabling instruction set encodings past the2002// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and2003// modern 64-bit x86 chip, and enables features that are generally beneficial.2004//2005// We currently use the Sandy Bridge model as the default scheduling model as2006// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which2007// covers a huge swath of x86 processors. If there are specific scheduling2008// knobs which need to be tuned differently for AMD chips, we might consider2009// forming a common base for them.2010def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,2011 ProcessorFeatures.X86_64V1Tuning>;2012// Close to Sandybridge.2013def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features,2014 ProcessorFeatures.X86_64V2Tuning>;2015// Close to Haswell.2016def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,2017 ProcessorFeatures.X86_64V3Tuning>;2018// Close to the AVX-512 level implemented by Xeon Scalable Processors.2019def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features,2020 ProcessorFeatures.X86_64V4Tuning>;2021 2022//===----------------------------------------------------------------------===//2023// Calling Conventions2024//===----------------------------------------------------------------------===//2025 2026include "X86CallingConv.td"2027 2028 2029//===----------------------------------------------------------------------===//2030// Assembly Parser2031//===----------------------------------------------------------------------===//2032 2033def ATTAsmParserVariant : AsmParserVariant {2034 int Variant = 0;2035 2036 // Variant name.2037 string Name = "att";2038 2039 // Discard comments in assembly strings.2040 string CommentDelimiter = "#";2041 2042 // Recognize hard coded registers.2043 string RegisterPrefix = "%";2044}2045 2046def IntelAsmParserVariant : AsmParserVariant {2047 int Variant = 1;2048 2049 // Variant name.2050 string Name = "intel";2051 2052 // Discard comments in assembly strings.2053 string CommentDelimiter = ";";2054 2055 // Recognize hard coded registers.2056 string RegisterPrefix = "";2057}2058 2059//===----------------------------------------------------------------------===//2060// Assembly Printers2061//===----------------------------------------------------------------------===//2062 2063// The X86 target supports two different syntaxes for emitting machine code.2064// This is controlled by the -x86-asm-syntax={att|intel}2065def ATTAsmWriter : AsmWriter {2066 string AsmWriterClassName = "ATTInstPrinter";2067 int Variant = 0;2068}2069def IntelAsmWriter : AsmWriter {2070 string AsmWriterClassName = "IntelInstPrinter";2071 int Variant = 1;2072}2073 2074def X86 : Target {2075 // Information about the instructions...2076 let InstructionSet = X86InstrInfo;2077 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];2078 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];2079 let AllowRegisterRenaming = 1;2080}2081 2082//===----------------------------------------------------------------------===//2083// Pfm Counters2084//===----------------------------------------------------------------------===//2085 2086include "X86PfmCounters.td"2087