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1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This describes the calling conventions for the X86-32 and X86-6410// architectures.11//12//===----------------------------------------------------------------------===//13 14/// CCIfSubtarget - Match if the current subtarget has a feature F.15class CCIfSubtarget<string F, CCAction A>16 : CCIf<!strconcat("State.getMachineFunction()."17 "getSubtarget<X86Subtarget>().", F),18 A>;19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F.21class CCIfNotSubtarget<string F, CCAction A>22 : CCIf<!strconcat("!State.getMachineFunction()."23 "getSubtarget<X86Subtarget>().", F),24 A>;25 26/// CCIfRegCallv4 - Match if RegCall ABIv4 is respected.27class CCIfRegCallv4<CCAction A>28 : CCIf<"State.getMachineFunction().getFunction().getParent()->getModuleFlag(\"RegCallv4\")!=nullptr",29 A>;30 31/// CCIfIsVarArgOnWin - Match if isVarArg on Windows 32bits.32class CCIfIsVarArgOnWin<CCAction A>33 : CCIf<"State.isVarArg() && "34 "State.getMachineFunction().getSubtarget().getTargetTriple()."35 "isWindowsMSVCEnvironment()",36 A>;37 38// Register classes for RegCall39class RC_X86_RegCall {40 list<Register> GPR_8 = [];41 list<Register> GPR_16 = [];42 list<Register> GPR_32 = [];43 list<Register> GPR_64 = [];44 list<Register> FP_CALL = [FP0];45 list<Register> FP_RET = [FP0, FP1];46 list<Register> XMM = [];47 list<Register> YMM = [];48 list<Register> ZMM = [];49}50 51// RegCall register classes for 32 bits52def RC_X86_32_RegCall : RC_X86_RegCall {53 let GPR_8 = [AL, CL, DL, DIL, SIL];54 let GPR_16 = [AX, CX, DX, DI, SI];55 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];56 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []57 ///< \todo Fix AssignToReg to enable empty lists58 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];59 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7];60 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7];61}62 63// RegCall register classes for 32 bits if it respect regcall ABI v.464// Change in __regcall ABI v.4: don't use EAX as a spare register is65// needed to code virtual call thunk,66def RC_X86_32_RegCallv4_Win : RC_X86_RegCall {67 let GPR_8 = [CL, DL, DIL, SIL];68 let GPR_16 = [CX, DX, DI, SI];69 let GPR_32 = [ECX, EDX, EDI, ESI];70 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []71 ///< \todo Fix AssignToReg to enable empty lists72 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];73 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7];74 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7];75}76 77class RC_X86_64_RegCall : RC_X86_RegCall {78 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,79 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15];80 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,81 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15];82 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7,83 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15];84}85 86def RC_X86_64_RegCall_Win : RC_X86_64_RegCall {87 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B];88 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W];89 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D];90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];91}92 93// On Windows 64 we don't want to use R13 - it is reserved for94// largely aligned stack.95// Change in __regcall ABI v.4: additionally don't use R10 as a96// a spare register is needed to code virtual call thunk.97//98def RC_X86_64_RegCallv4_Win : RC_X86_64_RegCall {99 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R11B, R12B, R14B, R15B];100 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R11W, R12W, R14W, R15W];101 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R11D, R12D, R14D, R15D];102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];103}104 105def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall {106 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B];107 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W];108 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D];109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];110}111 112// X86-64 Intel regcall calling convention.113multiclass X86_RegCall_base<RC_X86_RegCall RC> {114def CC_#NAME : CallingConv<[115 // Handles byval parameters.116 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>,117 CCIfByVal<CCPassByVal<4, 4>>,118 119 // Promote i1/i8/i16/v1i1 arguments to i32.120 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,121 122 // Promote v8i1/v16i1/v32i1 arguments to i32.123 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,124 125 // bool, char, int, enum, long, pointer --> GPR126 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,127 128 // long long, __int64 --> GPR129 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,130 131 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)132 CCIfType<[v64i1], CCPromoteToType<i64>>,133 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 134 CCAssignToReg<RC.GPR_64>>>,135 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 136 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,137 138 // float, double, float128 --> XMM139 // In the case of SSE disabled --> save to stack140 CCIfType<[f32, f64, f128], 141 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,142 143 // long double --> FP144 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>,145 146 // __m128, __m128i, __m128d --> XMM147 // In the case of SSE disabled --> save to stack148 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 149 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,150 151 // __m256, __m256i, __m256d --> YMM152 // In the case of SSE disabled --> save to stack153 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 154 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,155 156 // __m512, __m512i, __m512d --> ZMM157 // In the case of SSE disabled --> save to stack158 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 159 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>,160 161 // If no register was found -> assign to stack162 163 // In 64 bit, assign 64/32 bit values to 8 byte stack164 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 165 CCAssignToStack<8, 8>>>,166 167 // In 32 bit, assign 64/32 bit values to 8/4 byte stack168 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,169 CCIfType<[i64, f64], CCAssignToStack<8, 4>>,170 171 // float 128 get stack slots whose size and alignment depends 172 // on the subtarget.173 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,174 175 // Vectors get 16-byte stack slots that are 16-byte aligned.176 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 177 CCAssignToStack<16, 16>>,178 179 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.180 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 181 CCAssignToStack<32, 32>>,182 183 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.184 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],185 CCAssignToStack<64, 64>>186]>;187 188def RetCC_#NAME : CallingConv<[189 // Promote i1, v1i1, v8i1 arguments to i8.190 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,191 192 // Promote v16i1 arguments to i16.193 CCIfType<[v16i1], CCPromoteToType<i16>>,194 195 // Promote v32i1 arguments to i32.196 CCIfType<[v32i1], CCPromoteToType<i32>>,197 198 // bool, char, int, enum, long, pointer --> GPR199 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>,200 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>,201 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,202 203 // long long, __int64 --> GPR204 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,205 206 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)207 CCIfType<[v64i1], CCPromoteToType<i64>>,208 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 209 CCAssignToReg<RC.GPR_64>>>,210 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 211 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,212 213 // long double --> FP214 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>,215 216 // float, double, float128 --> XMM217 CCIfType<[f32, f64, f128], 218 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,219 220 // __m128, __m128i, __m128d --> XMM221 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 222 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,223 224 // __m256, __m256i, __m256d --> YMM225 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 226 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,227 228 // __m512, __m512i, __m512d --> ZMM229 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 230 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>>231]>;232}233 234//===----------------------------------------------------------------------===//235// Return Value Calling Conventions236//===----------------------------------------------------------------------===//237 238// Return-value conventions common to all X86 CC's.239def RetCC_X86Common : CallingConv<[240 // Scalar values are returned in AX first, then DX. For i8, the ABI241 // requires the values to be in AL and AH, however this code uses AL and DL242 // instead. This is because using AH for the second register conflicts with243 // the way LLVM does multiple return values -- a return of {i16,i8} would end244 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI245 // for functions that return two i8 values are currently expected to pack the246 // values into an i16 (which uses AX, and thus AL:AH).247 //248 // For code that doesn't care about the ABI, we allow returning more than two249 // integer values in registers.250 CCIfType<[v1i1], CCPromoteToType<i8>>,251 CCIfType<[i1], CCPromoteToType<i8>>,252 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,253 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,254 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,255 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,256 257 // Boolean vectors of AVX-512 are returned in SIMD registers.258 // The call from AVX to AVX-512 function should work,259 // since the boolean types in AVX/AVX2 are promoted by default.260 CCIfType<[v2i1], CCPromoteToType<v2i64>>,261 CCIfType<[v4i1], CCPromoteToType<v4i32>>,262 CCIfType<[v8i1], CCPromoteToType<v8i16>>,263 CCIfType<[v16i1], CCPromoteToType<v16i8>>,264 CCIfType<[v32i1], CCPromoteToType<v32i8>>,265 CCIfType<[v64i1], CCPromoteToType<v64i8>>,266 267 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3268 // can only be used by ABI non-compliant code. If the target doesn't have XMM269 // registers, it won't have vector types.270 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],271 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,272 273 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3274 // can only be used by ABI non-compliant code. This vector type is only275 // supported while using the AVX target feature.276 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64],277 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,278 279 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3280 // can only be used by ABI non-compliant code. This vector type is only281 // supported while using the AVX-512 target feature.282 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v32bf16, v16f32, v8f64],283 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,284 285 // Long double types are always returned in FP0 (even with SSE),286 // except on Win64 and UEFI64.287 CCIfNotSubtarget<"isTargetWin64()",288 CCIfNotSubtarget<"isTargetUEFI64()",289 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>>>290]>;291 292// X86-32 C return-value convention.293def RetCC_X86_32_C : CallingConv<[294 // The X86-32 calling convention returns FP values in FP0, unless marked295 // with "inreg" (used here to distinguish one kind of reg from another,296 // weirdly; this is really the sse-regparm calling convention) in which297 // case they use XMM0, otherwise it is the same as the common X86 calling298 // conv.299 CCIfInReg<CCIfSubtarget<"hasSSE2()",300 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,301 CCIfSubtarget<"hasX87()",302 CCIfType<[f32, f64], CCAssignToReg<[FP0, FP1]>>>,303 CCIfNotSubtarget<"hasX87()",304 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>,305 CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>,306 CCDelegateTo<RetCC_X86Common>307]>;308 309// X86-32 FastCC return-value convention.310def RetCC_X86_32_Fast : CallingConv<[311 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has312 // SSE2.313 // This can happen when a float, 2 x float, or 3 x float vector is split by314 // target lowering, and is returned in 1-3 sse regs.315 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,316 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,317 318 // For integers, ECX can be used as an extra return register319 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,320 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,321 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,322 323 // Otherwise, it is the same as the common X86 calling convention.324 CCDelegateTo<RetCC_X86Common>325]>;326 327// Intel_OCL_BI return-value convention.328def RetCC_Intel_OCL_BI : CallingConv<[329 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.330 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],331 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,332 333 // 256-bit FP vectors334 // No more than 4 registers335 CCIfType<[v8f32, v4f64, v8i32, v4i64],336 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,337 338 // 512-bit FP vectors339 CCIfType<[v16f32, v8f64, v16i32, v8i64],340 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,341 342 // i32, i64 in the standard way343 CCDelegateTo<RetCC_X86Common>344]>;345 346// X86-32 HiPE return-value convention.347def RetCC_X86_32_HiPE : CallingConv<[348 // Promote all types to i32349 CCIfType<[i8, i16], CCPromoteToType<i32>>,350 351 // Return: HP, P, VAL1, VAL2352 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>353]>;354 355// X86-32 Vectorcall return-value convention.356def RetCC_X86_32_VectorCall : CallingConv<[357 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3.358 CCIfType<[f32, f64, f128],359 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,360 361 // Return integers in the standard way.362 CCDelegateTo<RetCC_X86Common>363]>;364 365// X86-64 C return-value convention.366def RetCC_X86_64_C : CallingConv<[367 // The X86-64 calling convention always returns FP values in XMM0.368 CCIfType<[f16], CCAssignToReg<[XMM0, XMM1]>>,369 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,370 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,371 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>,372 373 // Pointers are always returned in full 64-bit registers.374 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>,375 376 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,377 378 CCDelegateTo<RetCC_X86Common>379]>;380 381// X86-Win64 C return-value convention.382def RetCC_X86_Win64_C : CallingConv<[383 // GCC returns FP values in RAX on Win64.384 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,385 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,386 387 // Otherwise, everything is the same as 'normal' X86-64 C CC.388 CCDelegateTo<RetCC_X86_64_C>389]>;390 391// X86-64 vectorcall return-value convention.392def RetCC_X86_64_Vectorcall : CallingConv<[393 // Vectorcall calling convention always returns FP values in XMMs.394 CCIfType<[f32, f64, f128], 395 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,396 397 // Otherwise, everything is the same as Windows X86-64 C CC.398 CCDelegateTo<RetCC_X86_Win64_C>399]>;400 401// X86-64 HiPE return-value convention.402def RetCC_X86_64_HiPE : CallingConv<[403 // Promote all types to i64404 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,405 406 // Return: HP, P, VAL1, VAL2407 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>408]>;409 410def RetCC_X86_64_Swift : CallingConv<[411 412 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,413 414 // For integers, ECX, R8D can be used as extra return registers.415 CCIfType<[v1i1], CCPromoteToType<i8>>,416 CCIfType<[i1], CCPromoteToType<i8>>,417 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>,418 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>,419 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>,420 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,421 422 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values.423 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,424 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,425 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,426 427 CCDelegateTo<RetCC_X86Common>428]>;429 430// X86-64 AnyReg return-value convention. No explicit register is specified for431// the return-value. The register allocator is allowed and expected to choose432// any free register.433//434// This calling convention is currently only supported by the stackmap and435// patchpoint intrinsics. All other uses will result in an assert on Debug436// builds. On Release builds we fallback to the X86 C calling convention.437def RetCC_X86_64_AnyReg : CallingConv<[438 CCCustom<"CC_X86_AnyReg_Error">439]>;440 441 442defm X86_32_RegCall :443 X86_RegCall_base<RC_X86_32_RegCall>;444defm X86_32_RegCallv4_Win :445 X86_RegCall_base<RC_X86_32_RegCallv4_Win>; 446defm X86_Win64_RegCall :447 X86_RegCall_base<RC_X86_64_RegCall_Win>;448defm X86_Win64_RegCallv4 :449 X86_RegCall_base<RC_X86_64_RegCallv4_Win>;450defm X86_SysV64_RegCall :451 X86_RegCall_base<RC_X86_64_RegCall_SysV>;452 453// This is the root return-value convention for the X86-32 backend.454def RetCC_X86_32 : CallingConv<[455 // If FastCC, use RetCC_X86_32_Fast.456 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,457 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>,458 // CFGuard_Check never returns a value so does not need a RetCC.459 // If HiPE, use RetCC_X86_32_HiPE.460 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,461 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>,462 CCIfCC<"CallingConv::X86_RegCall",463 CCIfSubtarget<"isTargetWin32()", CCIfRegCallv4<CCDelegateTo<RetCC_X86_32_RegCallv4_Win>>>>,464 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>,465 466 // Otherwise, use RetCC_X86_32_C.467 CCDelegateTo<RetCC_X86_32_C>468]>;469 470// This is the root return-value convention for the X86-64 backend.471def RetCC_X86_64 : CallingConv<[472 // HiPE uses RetCC_X86_64_HiPE473 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,474 475 // Handle AnyReg calls.476 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,477 478 // Handle Swift calls.479 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>,480 CCIfCC<"CallingConv::SwiftTail", CCDelegateTo<RetCC_X86_64_Swift>>,481 482 // Handle explicit CC selection483 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>,484 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,485 486 // Handle Vectorcall CC487 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>,488 489 CCIfCC<"CallingConv::X86_RegCall",490 CCIfSubtarget<"isTargetWin64()", CCIfRegCallv4<CCDelegateTo<RetCC_X86_Win64_RegCallv4>>>>,491 492 CCIfCC<"CallingConv::X86_RegCall",493 CCIfSubtarget<"isTargetWin64()",494 CCDelegateTo<RetCC_X86_Win64_RegCall>>>,495 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>,496 497 // Mingw64 and native Win64 use Win64 CC498 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,499 500 // UEFI64 uses Win64 CC501 CCIfSubtarget<"isTargetUEFI64()", CCDelegateTo<RetCC_X86_Win64_C>>,502 503 // Otherwise, drop to normal X86-64 CC504 CCDelegateTo<RetCC_X86_64_C>505]>;506 507// This is the return-value convention used for the entire X86 backend.508let Entry = 1 in509def RetCC_X86 : CallingConv<[510 511 // Check if this is the Intel OpenCL built-ins calling convention512 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,513 514 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,515 CCDelegateTo<RetCC_X86_32>516]>;517 518//===----------------------------------------------------------------------===//519// X86-64 Argument Calling Conventions520//===----------------------------------------------------------------------===//521 522def CC_X86_64_C : CallingConv<[523 // Handles byval parameters.524 CCIfByVal<CCPassByVal<8, 8>>,525 526 // Promote i1/i8/i16/v1i1 arguments to i32.527 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,528 529 // The 'nest' parameter, if any, is passed in R10.530 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,531 CCIfNest<CCAssignToReg<[R10]>>,532 533 // Pass SwiftSelf in a callee saved register.534 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,535 536 // A SwiftError is passed in R12.537 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,538 539 // Pass SwiftAsync in an otherwise callee saved register so that calls to540 // normal functions don't need to save it somewhere.541 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>,542 543 // For Swift Calling Conventions, pass sret in %rax.544 CCIfCC<"CallingConv::Swift",545 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,546 CCIfCC<"CallingConv::SwiftTail",547 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,548 549 // Pointers are always passed in full 64-bit registers.550 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>,551 552 // The first 6 integer arguments are passed in integer registers.553 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,554 555 // i128 can be either passed in two i64 registers, or on the stack, but556 // not split across register and stack. Handle this with a custom function.557 CCIfType<[i64],558 CCIfConsecutiveRegs<CCCustom<"CC_X86_64_I128">>>,559 560 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,561 562 // Boolean vectors of AVX-512 are passed in SIMD registers.563 // The call from AVX to AVX-512 function should work,564 // since the boolean types in AVX/AVX2 are promoted by default.565 CCIfType<[v2i1], CCPromoteToType<v2i64>>,566 CCIfType<[v4i1], CCPromoteToType<v4i32>>,567 CCIfType<[v8i1], CCPromoteToType<v8i16>>,568 CCIfType<[v16i1], CCPromoteToType<v16i8>>,569 CCIfType<[v32i1], CCPromoteToType<v32i8>>,570 CCIfType<[v64i1], CCPromoteToType<v64i8>>,571 572 // The first 8 FP/Vector arguments are passed in XMM registers.573 CCIfType<[f16, f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],574 CCIfSubtarget<"hasSSE1()",575 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,576 577 // The first 8 256-bit vector arguments are passed in YMM registers, unless578 // this is a vararg function.579 // FIXME: This isn't precisely correct; the x86-64 ABI document says that580 // fixed arguments to vararg functions are supposed to be passed in581 // registers. Actually modeling that would be a lot of work, though.582 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64],583 CCIfSubtarget<"hasAVX()",584 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,585 YMM4, YMM5, YMM6, YMM7]>>>>,586 587 // The first 8 512-bit vector arguments are passed in ZMM registers.588 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v32bf16, v16f32, v8f64],589 CCIfSubtarget<"hasAVX512()",590 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,591 592 // Integer/FP values get stored in stack slots that are 8 bytes in size and593 // 8-byte aligned if there are no more registers to hold them.594 CCIfType<[i32, i64, f16, f32, f64], CCAssignToStack<8, 8>>,595 596 // Long doubles get stack slots whose size and alignment depends on the597 // subtarget.598 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,599 600 // Vectors get 16-byte stack slots that are 16-byte aligned.601 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64], CCAssignToStack<16, 16>>,602 603 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.604 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64],605 CCAssignToStack<32, 32>>,606 607 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.608 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v32bf16, v16f32, v8f64],609 CCAssignToStack<64, 64>>610]>;611 612// Calling convention used on Win64613def CC_X86_Win64_C : CallingConv<[614 // FIXME: Handle varargs.615 616 // Byval aggregates are passed by pointer617 CCIfByVal<CCPassIndirect<i64>>,618 619 // Promote i1/v1i1 arguments to i8.620 CCIfType<[i1, v1i1], CCPromoteToType<i8>>,621 622 // The 'nest' parameter, if any, is passed in R10.623 CCIfNest<CCAssignToReg<[R10]>>,624 625 // A SwiftError is passed in R12.626 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,627 628 // Pass SwiftSelf in a callee saved register.629 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,630 631 // Pass SwiftAsync in an otherwise callee saved register so that calls to632 // normal functions don't need to save it somewhere.633 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>,634 635 // The 'CFGuardTarget' parameter, if any, is passed in RAX.636 CCIfCFGuardTarget<CCAssignToReg<[RAX]>>,637 638 // 128 bit vectors are passed by pointer639 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64], CCPassIndirect<i64>>,640 641 // 256 bit vectors are passed by pointer642 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64], CCPassIndirect<i64>>,643 644 // 512 bit vectors are passed by pointer645 CCIfType<[v64i8, v32i16, v16i32, v32f16, v32bf16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,646 647 // Float types larger than 64-bits (long double and fp128) are passed by pointer648 CCIfType<[f80], CCPassIndirect<i64>>,649 CCIfType<[f128], CCPassIndirect<i64>>,650 651 // If SSE was disabled, pass FP values smaller than 64-bits as integers in652 // GPRs or on the stack.653 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,654 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,655 656 // The first 4 FP/Vector arguments are passed in XMM registers.657 CCIfType<[f16, f32, f64],658 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],659 [RCX , RDX , R8 , R9 ]>>,660 661 // The first 4 integer arguments are passed in integer registers.662 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ],663 [XMM0, XMM1, XMM2, XMM3]>>,664 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ],665 [XMM0, XMM1, XMM2, XMM3]>>,666 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],667 [XMM0, XMM1, XMM2, XMM3]>>,668 669 // Do not pass the sret argument in RCX, the Win64 thiscall calling670 // convention requires "this" to be passed in RCX.671 CCIfCC<"CallingConv::X86_ThisCall",672 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],673 [XMM1, XMM2, XMM3]>>>>,674 675 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],676 [XMM0, XMM1, XMM2, XMM3]>>,677 678 // Integer/FP values get stored in stack slots that are 8 bytes in size and679 // 8-byte aligned if there are no more registers to hold them.680 CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>>681]>;682 683def CC_X86_Win64_VectorCall : CallingConv<[684 CCCustom<"CC_X86_64_VectorCall">,685 686 // Delegate to fastcall to handle integer types.687 CCDelegateTo<CC_X86_Win64_C>688]>;689 690 691def CC_X86_64_GHC : CallingConv<[692 // Promote i8/i16/i32 arguments to i64.693 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,694 695 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim696 CCIfType<[i64],697 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,698 699 // Pass in STG registers: F1, F2, F3, F4, D1, D2700 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],701 CCIfSubtarget<"hasSSE1()",702 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,703 // AVX704 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],705 CCIfSubtarget<"hasAVX()",706 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>,707 // AVX-512708 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],709 CCIfSubtarget<"hasAVX512()",710 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>>711]>;712 713def CC_X86_64_HiPE : CallingConv<[714 // Promote i8/i16/i32 arguments to i64.715 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,716 717 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3718 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,719 720 // Integer/FP values get stored in stack slots that are 8 bytes in size and721 // 8-byte aligned if there are no more registers to hold them.722 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>723]>;724 725// No explicit register is specified for the AnyReg calling convention. The726// register allocator may assign the arguments to any free register.727//728// This calling convention is currently only supported by the stackmap and729// patchpoint intrinsics. All other uses will result in an assert on Debug730// builds. On Release builds we fallback to the X86 C calling convention.731def CC_X86_64_AnyReg : CallingConv<[732 CCCustom<"CC_X86_AnyReg_Error">733]>;734 735//===----------------------------------------------------------------------===//736// X86 C Calling Convention737//===----------------------------------------------------------------------===//738 739/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector740/// values are spilled on the stack.741def CC_X86_32_Vector_Common : CallingConv<[742 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.743 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],744 CCAssignToStack<16, 16>>,745 746 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.747 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64],748 CCAssignToStack<32, 32>>,749 750 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.751 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v32bf16, v16f32, v8f64],752 CCAssignToStack<64, 64>>753]>;754 755/// CC_X86_Win32_Vector - In X86 Win32 calling conventions, extra vector756/// values are spilled on the stack.757def CC_X86_Win32_Vector : CallingConv<[758 // Other SSE vectors get 16-byte stack slots that are 4-byte aligned.759 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],760 CCAssignToStack<16, 4>>,761 762 // 256-bit AVX vectors get 32-byte stack slots that are 4-byte aligned.763 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64],764 CCAssignToStack<32, 4>>,765 766 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 4-byte aligned.767 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v32bf16, v16f32, v8f64],768 CCAssignToStack<64, 4>>769]>;770 771// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in772// vector registers773def CC_X86_32_Vector_Standard : CallingConv<[774 // SSE vector arguments are passed in XMM registers.775 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],776 CCAssignToReg<[XMM0, XMM1, XMM2]>>>,777 778 // AVX 256-bit vector arguments are passed in YMM registers.779 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64],780 CCIfSubtarget<"hasAVX()",781 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>,782 783 // AVX 512-bit vector arguments are passed in ZMM registers.784 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v32bf16, v16f32, v8f64],785 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>,786 787 CCIfIsVarArgOnWin<CCDelegateTo<CC_X86_Win32_Vector>>,788 CCDelegateTo<CC_X86_32_Vector_Common>789]>;790 791// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in792// vector registers.793def CC_X86_32_Vector_Darwin : CallingConv<[794 // SSE vector arguments are passed in XMM registers.795 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],796 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,797 798 // AVX 256-bit vector arguments are passed in YMM registers.799 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v16bf16, v8f32, v4f64],800 CCIfSubtarget<"hasAVX()",801 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,802 803 // AVX 512-bit vector arguments are passed in ZMM registers.804 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v32bf16, v16f32, v8f64],805 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,806 807 CCDelegateTo<CC_X86_32_Vector_Common>808]>;809 810/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP811/// values are spilled on the stack.812def CC_X86_32_Common : CallingConv<[813 // Handles byval/preallocated parameters.814 CCIfByVal<CCPassByVal<4, 4>>,815 CCIfPreallocated<CCPassByVal<4, 4>>,816 817 // The first 3 float or double arguments, if marked 'inreg' and if the call818 // is not a vararg call and if SSE2 is available, are passed in SSE registers.819 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],820 CCIfSubtarget<"hasSSE2()",821 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,822 823 CCIfNotVarArg<CCIfInReg<CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,824 825 CCIfType<[f16], CCAssignToStack<4, 4>>,826 827 // Integer/Float values get stored in stack slots that are 4 bytes in828 // size and 4-byte aligned.829 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,830 831 // Doubles get 8-byte slots that are 4-byte aligned.832 CCIfType<[f64], CCAssignToStack<8, 4>>,833 834 // Long doubles get slots whose size and alignment depends on the subtarget.835 CCIfSubtarget<"isTargetDarwin()", CCIfType<[f80], CCAssignToStack<0, 4>>>,836 CCIfType<[f80], CCAssignToStack<0, 0>>,837 838 // Boolean vectors of AVX-512 are passed in SIMD registers.839 // The call from AVX to AVX-512 function should work,840 // since the boolean types in AVX/AVX2 are promoted by default.841 CCIfType<[v2i1], CCPromoteToType<v2i64>>,842 CCIfType<[v4i1], CCPromoteToType<v4i32>>,843 CCIfType<[v8i1], CCPromoteToType<v8i16>>,844 CCIfType<[v16i1], CCPromoteToType<v16i8>>,845 CCIfType<[v32i1], CCPromoteToType<v32i8>>,846 CCIfType<[v64i1], CCPromoteToType<v64i8>>,847 848 // Darwin passes vectors in a form that differs from the i386 psABI849 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,850 851 // Otherwise, drop to 'normal' X86-32 CC852 CCDelegateTo<CC_X86_32_Vector_Standard>853]>;854 855def CC_X86_32_C : CallingConv<[856 // Promote i1/i8/i16/v1i1 arguments to i32.857 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,858 859 // The 'nest' parameter, if any, is passed in ECX.860 CCIfNest<CCAssignToReg<[ECX]>>,861 862 // i128 and fp128 need to be passed on the stack with a higher alignment than863 // their legal types. Handle this with a custom function.864 CCIfType<[i32],865 CCIfConsecutiveRegs<CCCustom<"CC_X86_32_I128_FP128">>>,866 867 // On swifttailcc pass swiftself in ECX.868 CCIfCC<"CallingConv::SwiftTail",869 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[ECX]>>>>,870 871 // The first 3 integer arguments, if marked 'inreg' and if the call is not872 // a vararg call, are passed in integer registers.873 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,874 875 // Otherwise, same as everything else.876 CCDelegateTo<CC_X86_32_Common>877]>;878 879def CC_X86_32_MCU : CallingConv<[880 // Handles byval parameters. Note that, like FastCC, we can't rely on881 // the delegation to CC_X86_32_Common because that happens after code that882 // puts arguments in registers.883 CCIfByVal<CCPassByVal<4, 4>>,884 885 // Promote i1/i8/i16/v1i1 arguments to i32.886 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,887 888 // If the call is not a vararg call, some arguments may be passed889 // in integer registers.890 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>,891 892 // Otherwise, same as everything else.893 CCDelegateTo<CC_X86_32_Common>894]>;895 896def CC_X86_32_FastCall : CallingConv<[897 // Promote i1 to i8.898 CCIfType<[i1], CCPromoteToType<i8>>,899 900 // The 'nest' parameter, if any, is passed in EAX.901 CCIfNest<CCAssignToReg<[EAX]>>,902 903 // The first 2 integer arguments are passed in ECX/EDX904 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>,905 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>,906 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,907 908 // Otherwise, same as everything else.909 CCDelegateTo<CC_X86_32_Common>910]>;911 912def CC_X86_Win32_VectorCall : CallingConv<[913 // Pass floating point in XMMs914 CCCustom<"CC_X86_32_VectorCall">,915 916 // Delegate to fastcall to handle integer types.917 CCDelegateTo<CC_X86_32_FastCall>918]>;919 920def CC_X86_32_ThisCall_Common : CallingConv<[921 // The first integer argument is passed in ECX922 CCIfType<[i32], CCAssignToReg<[ECX]>>,923 924 // Otherwise, same as everything else.925 CCDelegateTo<CC_X86_32_Common>926]>;927 928def CC_X86_32_ThisCall_Mingw : CallingConv<[929 // Promote i1/i8/i16/v1i1 arguments to i32.930 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,931 932 CCDelegateTo<CC_X86_32_ThisCall_Common>933]>;934 935def CC_X86_32_ThisCall_Win : CallingConv<[936 // Promote i1/i8/i16/v1i1 arguments to i32.937 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,938 939 // Pass sret arguments indirectly through stack.940 CCIfSRet<CCAssignToStack<4, 4>>,941 942 CCDelegateTo<CC_X86_32_ThisCall_Common>943]>;944 945def CC_X86_32_ThisCall : CallingConv<[946 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,947 CCDelegateTo<CC_X86_32_ThisCall_Win>948]>;949 950def CC_X86_32_FastCC : CallingConv<[951 // Handles byval parameters. Note that we can't rely on the delegation952 // to CC_X86_32_Common for this because that happens after code that953 // puts arguments in registers.954 CCIfByVal<CCPassByVal<4, 4>>,955 956 // Promote i1/i8/i16/v1i1 arguments to i32.957 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,958 959 // The 'nest' parameter, if any, is passed in EAX.960 CCIfNest<CCAssignToReg<[EAX]>>,961 962 // The first 2 integer arguments are passed in ECX/EDX963 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,964 965 // The first 3 float or double arguments, if the call is not a vararg966 // call and if SSE2 is available, are passed in SSE registers.967 CCIfNotVarArg<CCIfType<[f32,f64],968 CCIfSubtarget<"hasSSE2()",969 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,970 971 // Doubles get 8-byte slots that are 8-byte aligned.972 CCIfType<[f64], CCAssignToStack<8, 8>>,973 974 // Otherwise, same as everything else.975 CCDelegateTo<CC_X86_32_Common>976]>;977 978def CC_X86_Win32_CFGuard_Check : CallingConv<[979 // The CFGuard check call takes exactly one integer argument980 // (i.e. the target function address), which is passed in ECX.981 CCIfType<[i32], CCAssignToReg<[ECX]>>982]>;983 984def CC_X86_32_GHC : CallingConv<[985 // Promote i8/i16 arguments to i32.986 CCIfType<[i8, i16], CCPromoteToType<i32>>,987 988 // Pass in STG registers: Base, Sp, Hp, R1989 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>990]>;991 992def CC_X86_32_HiPE : CallingConv<[993 // Promote i8/i16 arguments to i32.994 CCIfType<[i8, i16], CCPromoteToType<i32>>,995 996 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2997 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,998 999 // Integer/Float values get stored in stack slots that are 4 bytes in1000 // size and 4-byte aligned.1001 CCIfType<[i32, f32], CCAssignToStack<4, 4>>1002]>;1003 1004// X86-64 Intel OpenCL built-ins calling convention.1005def CC_Intel_OCL_BI : CallingConv<[1006 1007 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,1008 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,1009 1010 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,1011 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,1012 1013 CCIfType<[i32], CCAssignToStack<4, 4>>,1014 1015 // The SSE vector arguments are passed in XMM registers.1016 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],1017 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,1018 1019 // The 256-bit vector arguments are passed in YMM registers.1020 CCIfType<[v8f32, v4f64, v8i32, v4i64],1021 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,1022 1023 // The 512-bit vector arguments are passed in ZMM registers.1024 CCIfType<[v16f32, v8f64, v16i32, v8i64],1025 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,1026 1027 // Pass masks in mask registers1028 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,1029 1030 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,1031 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,1032 CCDelegateTo<CC_X86_32_C>1033]>;1034 1035def CC_X86_64_Preserve_None : CallingConv<[1036 // We don't preserve general registers, so all of them can be used to pass1037 // arguments except1038 // - RBP frame pointer1039 // - R10 'nest' parameter1040 // - RBX base pointer1041 // - R16 - R31 these are not available everywhere1042 // Use non-volatile registers first, so functions using this convention can1043 // call "normal" functions without saving and restoring incoming values:1044 CCIfType<[i32], CCAssignToReg<[R12D, R13D, R14D, R15D, EDI, ESI,1045 EDX, ECX, R8D, R9D, R11D, EAX]>>,1046 1047 CCIfType<[i64], CCAssignToReg<[R12, R13, R14, R15, RDI, RSI,1048 RDX, RCX, R8, R9, R11, RAX]>>,1049 1050 // Otherwise it's the same as the regular C calling convention.1051 CCDelegateTo<CC_X86_64_C>1052]>;1053 1054//===----------------------------------------------------------------------===//1055// X86 Root Argument Calling Conventions1056//===----------------------------------------------------------------------===//1057 1058// This is the root argument convention for the X86-32 backend.1059def CC_X86_32 : CallingConv<[1060 // X86_INTR calling convention is valid in MCU target and should override the1061 // MCU calling convention. Thus, this should be checked before isTargetMCU().1062 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>,1063 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>,1064 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,1065 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>,1066 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,1067 CCIfCC<"CallingConv::CFGuard_Check", CCDelegateTo<CC_X86_Win32_CFGuard_Check>>,1068 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,1069 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>,1070 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,1071 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,1072 CCIfCC<"CallingConv::X86_RegCall",1073 CCIfSubtarget<"isTargetWin32()", CCIfRegCallv4<CCDelegateTo<CC_X86_32_RegCallv4_Win>>>>,1074 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>,1075 1076 // Otherwise, drop to normal X86-32 CC1077 CCDelegateTo<CC_X86_32_C>1078]>;1079 1080// This is the root argument convention for the X86-64 backend.1081def CC_X86_64 : CallingConv<[1082 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,1083 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,1084 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,1085 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>,1086 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,1087 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,1088 CCIfCC<"CallingConv::X86_RegCall",1089 CCIfSubtarget<"isTargetWin64()", CCIfRegCallv4<CCDelegateTo<CC_X86_Win64_RegCallv4>>>>,1090 CCIfCC<"CallingConv::X86_RegCall",1091 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>,1092 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>,1093 CCIfCC<"CallingConv::PreserveNone", CCDelegateTo<CC_X86_64_Preserve_None>>,1094 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>,1095 1096 // Mingw64 and native Win64 use Win64 CC1097 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,1098 1099 // UEFI uses Win64 CC1100 CCIfSubtarget<"isTargetUEFI64()", CCDelegateTo<CC_X86_Win64_C>>,1101 1102 // Otherwise, drop to normal X86-64 CC1103 CCDelegateTo<CC_X86_64_C>1104]>;1105 1106// This is the argument convention used for the entire X86 backend.1107let Entry = 1 in1108def CC_X86 : CallingConv<[1109 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,1110 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,1111 CCDelegateTo<CC_X86_32>1112]>;1113 1114//===----------------------------------------------------------------------===//1115// Callee-saved Registers.1116//===----------------------------------------------------------------------===//1117 1118def CSR_NoRegs : CalleeSavedRegs<(add)>;1119 1120def CSR_IPRA_32 : CalleeSavedRegs<(add EBP, ESI)>;1121def CSR_IPRA_64 : CalleeSavedRegs<(add RBP, RBX)>;1122 1123def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;1124def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;1125 1126def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;1127def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>;1128 1129def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;1130def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;1131 1132def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;1133 1134def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE,1135 (sequence "XMM%u", 6, 15))>;1136 1137def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>;1138def CSR_Win64_SwiftTail : CalleeSavedRegs<(sub CSR_Win64, R13, R14)>;1139 1140// The function used by Darwin to obtain the address of a thread-local variable1141// uses rdi to pass a single parameter and rax for the return value. All other1142// GPRs are preserved.1143def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,1144 R8, R9, R10, R11)>;1145 1146// CSRs that are handled by prologue, epilogue.1147def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>;1148 1149// CSRs that are handled explicitly via copies.1150def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>;1151 1152// All GPRs - except r11 and return registers.1153def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,1154 R8, R9, R10)>;1155 1156def CSR_Win64_RT_MostRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,1157 (sequence "XMM%u", 6, 15))>;1158 1159// All registers - except r11 and return registers.1160def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,1161 (sequence "XMM%u", 0, 15))>;1162def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,1163 (sequence "YMM%u", 0, 15))>;1164 1165def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,1166 R11, R12, R13, R14, R15, RBP,1167 (sequence "XMM%u", 0, 15))>;1168 1169def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI,1170 EDI)>;1171def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs,1172 (sequence "XMM%u", 0, 7))>;1173def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs,1174 (sequence "YMM%u", 0, 7))>;1175def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs,1176 (sequence "ZMM%u", 0, 7),1177 (sequence "K%u", 0, 7))>;1178 1179def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>;1180def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9,1181 R10, R11, R12, R13, R14, R15, RBP)>;1182def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,1183 (sequence "YMM%u", 0, 15)),1184 (sequence "XMM%u", 0, 15))>;1185def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,1186 (sequence "ZMM%u", 0, 31),1187 (sequence "K%u", 0, 7)),1188 (sequence "XMM%u", 0, 15))>;1189def CSR_64_NoneRegs : CalleeSavedRegs<(add RBP)>;1190 1191// Standard C + YMM6-151192def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,1193 R13, R14, R15,1194 (sequence "YMM%u", 6, 15))>;1195 1196def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,1197 R12, R13, R14, R15,1198 (sequence "ZMM%u", 6, 21),1199 K4, K5, K6, K7)>;1200//Standard C + XMM 8-151201def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,1202 (sequence "XMM%u", 8, 15))>;1203 1204//Standard C + YMM 8-151205def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,1206 (sequence "YMM%u", 8, 15))>;1207 1208def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15,1209 (sequence "ZMM%u", 16, 31),1210 K4, K5, K6, K7)>;1211 1212// Register calling convention preserves few GPR and XMM8-151213def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;1214def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE,1215 (sequence "XMM%u", 4, 7))>;1216def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, ECX)>;1217def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>;1218def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP,1219 (sequence "R%u", 10, 15))>;1220def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1221 (sequence "XMM%u", 8, 15))>;1222def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP,1223 (sequence "R%u", 12, 15))>;1224def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1225 (sequence "XMM%u", 8, 15))>;1226