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1//===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the instructions that make up the Intel AMX instruction10// set.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// AMX instructions16 17multiclass AMX_TILE_COMMON<string Suffix, Predicate HasEGPR> {18let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {19 let hasSideEffects = 1,20 Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in21 def LDTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),22 "ldtilecfg\t$src",23 [(int_x86_ldtilecfg addr:$src)]>,24 T8, PS;25 let hasSideEffects = 1 in26 def STTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),27 "sttilecfg\t$src",28 [(int_x86_sttilecfg addr:$src)]>,29 T8, PD;30 let mayLoad = 1 in31 def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),32 (ins sibmem:$src),33 "tileloadd\t{$src, $dst|$dst, $src}", []>,34 T8, XD;35 let mayLoad = 1 in36 def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),37 (ins sibmem:$src),38 "tileloaddt1\t{$src, $dst|$dst, $src}", []>,39 T8, PD;40 let mayStore = 1 in41 def TILESTORED#Suffix : I<0x4b, MRMDestMemFSIB, (outs),42 (ins sibmem:$dst, TILE:$src),43 "tilestored\t{$src, $dst|$dst, $src}", []>,44 T8, XS;45}46}47 48let SchedRW = [WriteSystem] in {49 defm "" : AMX_TILE_COMMON<"", NoEGPR>, VEX;50 defm "" : AMX_TILE_COMMON<"_EVEX", HasEGPR>, EVEX, NoCD8;51 52 let Predicates = [HasAMXTILE, In64BitMode] in {53 let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in54 def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),55 "tilerelease", [(int_x86_tilerelease)]>, VEX, T8, PS;56 def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),57 "tilezero\t$dst", []>,58 VEX, T8, XD;59 60 // Pseduo instruction for RA.61 let isPseudo = true, mayLoad = 1, hasSideEffects = 1,62 Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in63 def PLDTILECFGV : PseudoI<(outs), (ins opaquemem:$src), []>;64 let isPseudo = true, mayLoad = 1 in65 def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,66 GR16:$src2,67 opaquemem:$src3), []>;68 let isPseudo = true, mayLoad = 1 in69 def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,70 GR16:$src2,71 opaquemem:$src3), []>;72 let isPseudo = true, mayStore = 1 in73 def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,74 GR16:$src2, opaquemem:$src3,75 TILE:$src4), []>;76 let isPseudo = true, isReMaterializable = 1, isAsCheapAsAMove = 1,77 canFoldAsLoad = 1, usesCustomInserter = 1 in78 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),79 [(set TILE:$dst, (int_x86_tilezero_internal80 GR16:$src1, GR16:$src2))]>;81 82 let usesCustomInserter = 1 in {83 // Pseudo instructions, using immediates instead of tile registers.84 // To be translated to the actual instructions in X86ISelLowering.cpp85 let mayLoad = 1 in86 def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;87 let mayLoad = 1 in88 def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,89 sibmem:$src2), []>;90 let mayStore = 1 in91 def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>;92 def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),93 [(int_x86_tilezero timm:$src)]>;94 }95 } // Predicates96} // SchedRW97 98let Predicates = [HasAMXINT8, In64BitMode] in {99 let SchedRW = [WriteSystem] in {100 let Constraints = "$src1 = $dst" in {101 def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),102 (ins TILE:$src1, TILE:$src2, TILE:$src3),103 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,104 VEX, VVVV, T8, XD;105 def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),106 (ins TILE:$src1, TILE:$src2, TILE:$src3),107 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,108 VEX, VVVV, T8, XS;109 def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),110 (ins TILE:$src1, TILE:$src2, TILE:$src3),111 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,112 VEX, VVVV, T8, PD;113 def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),114 (ins TILE:$src1, TILE:$src2, TILE:$src3),115 "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,116 VEX, VVVV, T8;117 }118 119 // Pseduo instruction for RA.120 let isPseudo = true, Constraints = "$src4 = $dst" in {121 def PTDPBSSDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,122 GR16:$src2, GR16:$src3, TILE:$src4,123 TILE:$src5, TILE:$src6),124 [(set TILE: $dst,125 (int_x86_tdpbssd_internal GR16:$src1, GR16:$src2,126 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;127 def PTDPBSUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,128 GR16:$src2, GR16:$src3, TILE:$src4,129 TILE:$src5, TILE:$src6),130 [(set TILE: $dst,131 (int_x86_tdpbsud_internal GR16:$src1, GR16:$src2,132 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;133 def PTDPBUSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,134 GR16:$src2, GR16:$src3, TILE:$src4,135 TILE:$src5, TILE:$src6),136 [(set TILE: $dst,137 (int_x86_tdpbusd_internal GR16:$src1, GR16:$src2,138 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;139 def PTDPBUUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,140 GR16:$src2, GR16:$src3, TILE:$src4,141 TILE:$src5, TILE:$src6),142 [(set TILE: $dst,143 (int_x86_tdpbuud_internal GR16:$src1, GR16:$src2,144 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;145 }146 147 let usesCustomInserter = 1 in {148 // Pseudo instructions, using immediates instead of tile registers.149 // To be translated to the actual instructions in X86ISelLowering.cpp150 def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,151 u8imm:$src2, u8imm:$src3),152 [(int_x86_tdpbssd timm:$src1,153 timm:$src2, timm:$src3)]>;154 def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1,155 u8imm:$src2, u8imm:$src3),156 [(int_x86_tdpbsud timm:$src1,157 timm:$src2, timm:$src3)]>;158 def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1,159 u8imm:$src2, u8imm:$src3),160 [(int_x86_tdpbusd timm:$src1,161 timm:$src2, timm:$src3)]>;162 def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1,163 u8imm:$src2, u8imm:$src3),164 [(int_x86_tdpbuud timm:$src1,165 timm:$src2, timm:$src3)]>;166 }167 }168} // HasAMXTILE169 170let Predicates = [HasAMXBF16, In64BitMode] in {171 let SchedRW = [WriteSystem] in {172 let Constraints = "$src1 = $dst" in173 def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),174 (ins TILE:$src1, TILE:$src2, TILE:$src3),175 "tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",176 []>, VEX, VVVV, T8, XS;177 178 // Pseduo instruction for RA.179 let isPseudo = true, Constraints = "$src4 = $dst" in180 def PTDPBF16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,181 GR16:$src2, GR16:$src3, TILE:$src4,182 TILE:$src5, TILE:$src6),183 [(set TILE: $dst,184 (int_x86_tdpbf16ps_internal GR16:$src1,185 GR16:$src2, GR16:$src3, TILE:$src4,186 TILE:$src5, TILE:$src6))]>;187 188 let usesCustomInserter = 1 in {189 // Pseudo instructions, using immediates instead of tile registers.190 // To be translated to the actual instructions in X86ISelLowering.cpp191 def PTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1,192 u8imm:$src2, u8imm:$src3),193 [(int_x86_tdpbf16ps timm:$src1,194 timm:$src2, timm:$src3)]>;195 }196 }197} // HasAMXTILE, HasAMXBF16198 199//AMX-FP16200let Predicates = [HasAMXFP16, In64BitMode] in {201 let SchedRW = [WriteSystem] in {202 let Constraints = "$src1 = $dst" in {203 def TDPFP16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),204 (ins TILE:$src1, TILE:$src2, TILE:$src3),205 "tdpfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",206 []>, VEX, VVVV, T8, XD;207 }208 209 // Pseduo instruction for RA.210 let isPseudo = true, Constraints = "$src4 = $dst" in {211 def PTDPFP16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,212 GR16:$src2, GR16:$src3, TILE:$src4,213 TILE:$src5, TILE:$src6),214 [(set TILE: $dst,215 (int_x86_tdpfp16ps_internal GR16:$src1,216 GR16:$src2, GR16:$src3, TILE:$src4,217 TILE:$src5, TILE:$src6))]>;218 }219 220 let usesCustomInserter = 1 in {221 def PTDPFP16PS : PseudoI<(outs), (ins u8imm:$src1,222 u8imm:$src2, u8imm:$src3),223 [(int_x86_tdpfp16ps timm:$src1,224 timm:$src2, timm:$src3)]>;225 }226 }227} // HasAMXTILE, HasAMXFP16228 229let Predicates = [HasAMXCOMPLEX, In64BitMode] in {230 let SchedRW = [WriteSystem] in {231 let Constraints = "$src1 = $dst" in {232 def TCMMIMFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),233 (ins TILE:$src1, TILE:$src2, TILE:$src3),234 "tcmmimfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",235 []>, T8, PD, VEX, VVVV;236 def TCMMRLFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),237 (ins TILE:$src1, TILE:$src2, TILE:$src3),238 "tcmmrlfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",239 []>, VEX, VVVV, WIG, T8;240 241 } // Constraints = "$src1 = $dst"242 243 let Constraints = "$src4 = $dst" in {244 def PTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,245 GR16:$src2, GR16:$src3, TILE:$src4,246 TILE:$src5, TILE:$src6),247 [(set TILE: $dst,248 (int_x86_tcmmimfp16ps_internal GR16:$src1, GR16:$src2,249 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;250 def PTCMMRLFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,251 GR16:$src2, GR16:$src3, TILE:$src4,252 TILE:$src5, TILE:$src6),253 [(set TILE: $dst,254 (int_x86_tcmmrlfp16ps_internal GR16:$src1, GR16:$src2,255 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;256 }257 258 let usesCustomInserter = 1 in {259 def PTCMMIMFP16PS : PseudoI<(outs), (ins u8imm:$src1,260 u8imm:$src2, u8imm:$src3),261 [(int_x86_tcmmimfp16ps timm:$src1,262 timm:$src2, timm:$src3)]>;263 def PTCMMRLFP16PS : PseudoI<(outs), (ins u8imm:$src1,264 u8imm:$src2, u8imm:$src3),265 [(int_x86_tcmmrlfp16ps timm:$src1,266 timm:$src2, timm:$src3)]>;267 }268 } // SchedRW = [WriteSystem]269}270 271// AMX-FP8272let Predicates = [HasAMXFP8, In64BitMode] in {273 let SchedRW = [WriteSystem] in {274 let Constraints = "$src1 = $dst" in {275 class AMX_FP8_BASE<bits<8> Opcode, string Opstr> :276 I<Opcode, MRMSrcReg4VOp3, (outs TILE:$dst),277 (ins TILE:$src1, TILE:$src2, TILE:$src3),278 !strconcat(Opstr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),279 []>, VEX, VVVV;280 }281 282 def TDPBF8PS : AMX_FP8_BASE<0xfd, "tdpbf8ps">, T_MAP5, PS;283 def TDPBHF8PS : AMX_FP8_BASE<0xfd, "tdpbhf8ps">, T_MAP5, XD;284 def TDPHBF8PS : AMX_FP8_BASE<0xfd, "tdphbf8ps">, T_MAP5, XS;285 def TDPHF8PS : AMX_FP8_BASE<0xfd, "tdphf8ps">, T_MAP5, PD;286 287 let usesCustomInserter = 1 in {288 // Pseudo instructions, using immediates instead of tile registers.289 // To be translated to the actual instructions in X86ISelLowering.cpp290 def PTDPBF8PS : PseudoI<(outs),291 (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),292 [(int_x86_tdpbf8ps timm:$src1, timm:$src2,293 timm:$src3)]>;294 def PTDPBHF8PS : PseudoI<(outs),295 (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),296 [(int_x86_tdpbhf8ps timm:$src1, timm:$src2,297 timm:$src3)]>;298 def PTDPHBF8PS : PseudoI<(outs),299 (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),300 [(int_x86_tdphbf8ps timm:$src1, timm:$src2,301 timm:$src3)]>;302 def PTDPHF8PS : PseudoI<(outs),303 (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),304 [(int_x86_tdphf8ps timm:$src1, timm:$src2,305 timm:$src3)]>;306 }307 308 let Constraints = "$src4 = $dst" in {309 def PTDPBF8PSV : PseudoI<(outs TILE:$dst),310 (ins GR16:$src1, GR16:$src2, GR16:$src3,311 TILE:$src4, TILE:$src5, TILE:$src6),312 [(set TILE:$dst,313 (int_x86_tdpbf8ps_internal GR16:$src1,314 GR16:$src2, GR16:$src3, TILE:$src4,315 TILE:$src5, TILE:$src6))]>;316 def PTDPBHF8PSV : PseudoI<(outs TILE:$dst),317 (ins GR16:$src1, GR16:$src2, GR16:$src3,318 TILE:$src4, TILE:$src5, TILE:$src6),319 [(set TILE:$dst,320 (int_x86_tdpbhf8ps_internal GR16:$src1,321 GR16:$src2, GR16:$src3, TILE:$src4,322 TILE:$src5, TILE:$src6))]>;323 def PTDPHBF8PSV : PseudoI<(outs TILE:$dst),324 (ins GR16:$src1, GR16:$src2, GR16:$src3,325 TILE:$src4, TILE:$src5, TILE:$src6),326 [(set TILE:$dst,327 (int_x86_tdphbf8ps_internal GR16:$src1,328 GR16:$src2, GR16:$src3, TILE:$src4,329 TILE:$src5, TILE:$src6))]>;330 def PTDPHF8PSV : PseudoI<(outs TILE:$dst),331 (ins GR16:$src1, GR16:$src2, GR16:$src3,332 TILE:$src4, TILE:$src5, TILE:$src6),333 [(set TILE:$dst,334 (int_x86_tdphf8ps_internal GR16:$src1,335 GR16:$src2, GR16:$src3, TILE:$src4,336 TILE:$src5, TILE:$src6))]>;337 }338 }339}340 341multiclass TILELOADDRS_Base<string suffix> {342 def suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),343 "tileloaddrs\t{$src1, $dst|$dst, $src1}", []>, T8, XD;344 def T1#suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),345 "tileloaddrst1\t{$src1, $dst|$dst, $src1}", []>, T8, PD;346}347 348let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in349 defm TILELOADDRS : TILELOADDRS_Base<"">, VEX;350 351let Predicates = [HasAMXMOVRS, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in352 defm TILELOADDRS : TILELOADDRS_Base<"_EVEX">, EVEX, NoCD8;353 354let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {355 let isPseudo = true, mayLoad = 1 in {356 def PTILELOADDRSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,357 GR16:$src2,358 opaquemem:$src3), []>;359 def PTILELOADDRST1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,360 GR16:$src2,361 opaquemem:$src3), []>;362 }363 364 let usesCustomInserter = 1, mayLoad = 1 in {365 def PTILELOADDRS : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;366 def PTILELOADDRST1 : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;367 }368} // HasAMXMOVRS, In64BitMode369 370multiclass m_tcvtrowd2ps {371 let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {372 let SchedRW = [WriteSystem] in {373 def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),374 (ins TILE:$src1, i32u8imm:$src2),375 "tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",376 []>, TA,XS, EVEX, EVEX_V512;377 def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),378 (ins TILE:$src1, GR32:$src2),379 "tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",380 []>, T8,XS, EVEX, VVVV, EVEX_V512;381 }382 } // HasAMXAVX512, HasAVX10_2, In64BitMode383}384 385defm TCVTROWD2PS : m_tcvtrowd2ps;386 387let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {388 let SchedRW = [WriteSystem] in {389 let usesCustomInserter = 1 in {390 def PTCVTROWD2PSrri : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2),391 [(set VR512:$dst, (int_x86_tcvtrowd2ps timm:$src1, imm:$src2))]>;392 def PTCVTROWD2PSrre : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, GR32:$src2),393 [(set VR512:$dst, (int_x86_tcvtrowd2ps timm:$src1, GR32:$src2))]>;394 }395 396 def PTCVTROWD2PSrriV : PseudoI<(outs VR512:$dst),397 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),398 [(set VR512: $dst,399 (int_x86_tcvtrowd2ps_internal GR16:$src1, GR16:$src2,400 TILE:$src3, imm:$src4))]>;401 def PTCVTROWD2PSrreV : PseudoI<(outs VR512:$dst),402 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),403 [(set VR512: $dst,404 (int_x86_tcvtrowd2ps_internal GR16:$src1, GR16:$src2,405 TILE:$src3, GR32:$src4))]>;406 def PTCVTROWPS2BF16HrriV : PseudoI<(outs VR512:$dst),407 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),408 [(set VR512: $dst,409 (int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,410 TILE:$src3, imm:$src4))]>;411 def PTCVTROWPS2BF16HrreV : PseudoI<(outs VR512:$dst),412 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),413 [(set VR512: $dst,414 (int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,415 TILE:$src3, GR32:$src4))]>;416 def PTCVTROWPS2BF16LrriV : PseudoI<(outs VR512:$dst),417 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),418 [(set VR512: $dst,419 (int_x86_tcvtrowps2bf16l_internal GR16:$src1, GR16:$src2,420 TILE:$src3, imm:$src4))]>;421 def PTCVTROWPS2BF16LrreV : PseudoI<(outs VR512:$dst),422 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),423 [(set VR512: $dst,424 (int_x86_tcvtrowps2bf16l_internal GR16:$src1, GR16:$src2,425 TILE:$src3, GR32:$src4))]>;426 def PTCVTROWPS2PHHrriV : PseudoI<(outs VR512:$dst),427 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),428 [(set VR512: $dst,429 (int_x86_tcvtrowps2phh_internal GR16:$src1, GR16:$src2,430 TILE:$src3, imm:$src4))]>;431 def PTCVTROWPS2PHHrreV : PseudoI<(outs VR512:$dst),432 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),433 [(set VR512: $dst,434 (int_x86_tcvtrowps2phh_internal GR16:$src1, GR16:$src2,435 TILE:$src3, GR32:$src4))]>;436 def PTCVTROWPS2PHLrriV : PseudoI<(outs VR512:$dst),437 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),438 [(set VR512: $dst,439 (int_x86_tcvtrowps2phl_internal GR16:$src1, GR16:$src2,440 TILE:$src3, imm:$src4))]>;441 def PTCVTROWPS2PHLrreV : PseudoI<(outs VR512:$dst),442 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),443 [(set VR512: $dst,444 (int_x86_tcvtrowps2phl_internal GR16:$src1, GR16:$src2,445 TILE:$src3, GR32:$src4))]>;446 }447}448 449multiclass AMXAVX512_BASE<bits<8> Opcode1, bits<8> Opcode2, string Opstr,450 Prefix P1, Prefix P2> {451 let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode], SchedRW = [WriteSystem] in {452 let OpPrefix = P1 in453 def rte : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),454 (ins TILE:$src1, GR32:$src2),455 !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),456 []>, EVEX, VVVV, EVEX_V512, T8;457 let OpPrefix = P2 in458 def rti : Ii8<Opcode2, MRMSrcReg, (outs VR512:$dst),459 (ins TILE:$src1, i32u8imm:$src2),460 !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),461 []>, EVEX, EVEX_V512, TA;462 let usesCustomInserter = 1 in {463 def "P"#NAME#"rre" : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, GR32:$src2),464 [(set VR512:$dst,465 (!cast<Intrinsic>("int_x86_"#Opstr) timm:$src1, GR32:$src2))]>;466 def "P"#NAME#"rri" : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2),467 [(set VR512:$dst,468 (!cast<Intrinsic>("int_x86_"#Opstr) timm:$src1, imm:$src2))]>;469 }470 }471}472 473defm TCVTROWPS2PHH : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2phh", PS, PS>;474defm TCVTROWPS2PHL : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2phl", PD, XD>;475defm TCVTROWPS2BF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2bf16h", XD, XD>;476defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;477 478multiclass AMXAVX512_TILEMOVE<bits<8> Opcode1, bits<8> Opcode2, string Opstr> {479 let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {480 let SchedRW = [WriteSystem] in {481 def rti : Ii8<Opcode1, MRMSrcReg, (outs VR512:$dst),482 (ins TILE:$src1, u8imm:$src2),483 !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),484 []>, TA, PD, EVEX, EVEX_V512;485 def rte : I<Opcode2, MRMSrcReg4VOp3, (outs VR512:$dst),486 (ins TILE:$src1, GR32:$src2),487 !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),488 []>, T8, PD, EVEX, VVVV, EVEX_V512;489 }490 } // HasAMXAVX512, HasAVX10_2, In64BitMode491}492 493defm TILEMOVROW : AMXAVX512_TILEMOVE<0x07, 0x4A, "tilemovrow">;494 495let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {496 let SchedRW = [WriteSystem] in {497 let usesCustomInserter = 1 in {498 def PTILEMOVROWrri : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2),499 [(set VR512:$dst, (int_x86_tilemovrow timm:$src1, imm:$src2))]>;500 def PTILEMOVROWrre : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, GR32:$src2),501 [(set VR512:$dst, (int_x86_tilemovrow timm:$src1, GR32:$src2))]>;502 }503 504 def PTILEMOVROWrriV : PseudoI<(outs VR512:$dst),505 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),506 [(set VR512: $dst,507 (int_x86_tilemovrow_internal GR16:$src1, GR16:$src2,508 TILE:$src3, imm:$src4))]>;509 def PTILEMOVROWrreV : PseudoI<(outs VR512:$dst),510 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),511 [(set VR512: $dst,512 (int_x86_tilemovrow_internal GR16:$src1, GR16:$src2,513 TILE:$src3, GR32:$src4))]>;514 }515}516 517let Predicates = [HasAMXTF32, In64BitMode] in {518 let SchedRW = [WriteSystem] in {519 let Constraints = "$src1 = $dst" in {520 def TMMULTF32PS: I<0x48, MRMSrcReg4VOp3, (outs TILE:$dst),521 (ins TILE:$src1, TILE:$src2, TILE:$src3),522 "tmmultf32ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",523 []>, VEX, VVVV, T8, PD;524 }525 let Constraints = "$src4 = $dst" in {526 def PTMMULTF32PSV : PseudoI<(outs TILE:$dst),527 (ins GR16:$src1, GR16:$src2, GR16:$src3,528 TILE:$src4, TILE:$src5, TILE:$src6),529 [(set TILE:$dst,530 (int_x86_tmmultf32ps_internal GR16:$src1,531 GR16:$src2, GR16:$src3, TILE:$src4,532 TILE:$src5, TILE:$src6))]>;533 }534 let usesCustomInserter = 1 in {535 def PTMMULTF32PS : PseudoI<(outs),536 (ins u8imm:$src1, u8imm:$src2, u8imm:$src3),537 [(int_x86_tmmultf32ps timm:$src1, timm:$src2,538 timm:$src3)]>;539 }540 } // SchedRW = [WriteSystem]541} // HasAMXTF32542