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1//===-- X86InstrAVX10.td - AVX10 Instruction Set -----------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the X86 AVX10 instruction set, defining the10// instructions, and properties of the instructions which are needed for code11// generation, machine code emission, and analysis.12//13//===----------------------------------------------------------------------===//14 15// VNNI FP1616let ExeDomain = SSEPackedSingle in17defm VDPPHPS : avx512_dpf16ps_sizes<0x52, "vdpphps", X86dpfp16ps, avx512vl_f16_info,18 [HasAVX10_2], [HasAVX10_2]>,19 T8, PS, EVEX_CD8<32, CD8VF>;20 21// VNNI INT822defm VPDPBSSD : VNNI_common<0x50, "vpdpbssd", X86vpdpbssd, SchedWriteVecIMul, 1,23 [HasAVX10_2], [HasAVX10_2]>, XD;24defm VPDPBSSDS : VNNI_common<0x51, "vpdpbssds", X86vpdpbssds, SchedWriteVecIMul, 1,25 [HasAVX10_2], [HasAVX10_2]>, XD;26defm VPDPBSUD : VNNI_common<0x50, "vpdpbsud", X86vpdpbsud, SchedWriteVecIMul, 0,27 [HasAVX10_2], [HasAVX10_2]>, XS;28defm VPDPBSUDS : VNNI_common<0x51, "vpdpbsuds", X86vpdpbsuds, SchedWriteVecIMul, 0,29 [HasAVX10_2], [HasAVX10_2]>, XS;30defm VPDPBUUD : VNNI_common<0x50, "vpdpbuud", X86vpdpbuud, SchedWriteVecIMul, 1,31 [HasAVX10_2], [HasAVX10_2]>, PS;32defm VPDPBUUDS : VNNI_common<0x51, "vpdpbuuds", X86vpdpbuuds, SchedWriteVecIMul, 1,33 [HasAVX10_2], [HasAVX10_2]>, PS;34 35// VNNI INT1636defm VPDPWSUD : VNNI_common<0xd2, "vpdpwsud", X86vpdpwsud, SchedWriteVecIMul, 0,37 [HasAVX10_2], [HasAVX10_2]>, XS;38defm VPDPWSUDS : VNNI_common<0xd3, "vpdpwsuds", X86vpdpwsuds, SchedWriteVecIMul, 0,39 [HasAVX10_2], [HasAVX10_2]>, XS;40defm VPDPWUSD : VNNI_common<0xd2, "vpdpwusd", X86vpdpwusd, SchedWriteVecIMul, 0,41 [HasAVX10_2], [HasAVX10_2]>, PD;42defm VPDPWUSDS : VNNI_common<0xd3, "vpdpwusds", X86vpdpwusds, SchedWriteVecIMul, 0,43 [HasAVX10_2], [HasAVX10_2]>, PD;44defm VPDPWUUD : VNNI_common<0xd2, "vpdpwuud", X86vpdpwuud, SchedWriteVecIMul, 1,45 [HasAVX10_2], [HasAVX10_2]>, PS;46defm VPDPWUUDS : VNNI_common<0xd3, "vpdpwuuds", X86vpdpwuuds, SchedWriteVecIMul, 1,47 [HasAVX10_2], [HasAVX10_2]>, PS;48 49// VMPSADBW50defm VMPSADBW : avx512_common_3Op_rm_imm8<0x42, X86Vmpsadbw, "vmpsadbw", SchedWritePSADBW,51 avx512vl_i16_info, avx512vl_i8_info,52 HasAVX10_2>,53 XS, EVEX_CD8<32, CD8VF>;54 55//-------------------------------------------------56// AVX10 MINMAX instructions57//-------------------------------------------------58 59multiclass avx10_minmax_packed_base<string OpStr, X86VectorVTInfo VTI, SDNode OpNode> {60 let ExeDomain = VTI.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {61 defm rri : AVX512_maskable<0x52, MRMSrcReg, VTI, (outs VTI.RC:$dst),62 (ins VTI.RC:$src1, VTI.RC:$src2, i32u8imm:$src3), OpStr,63 "$src3, $src2, $src1", "$src1, $src2, $src3",64 (VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,65 (i32 timm:$src3)))>,66 EVEX, VVVV, Sched<[WriteFMAX]>;67 defm rmi : AVX512_maskable<0x52, MRMSrcMem, VTI, (outs VTI.RC:$dst),68 (ins VTI.RC:$src1, VTI.MemOp:$src2, i32u8imm:$src3), OpStr,69 "$src3, $src2, $src1", "$src1, $src2, $src3",70 (VTI.VT (OpNode VTI.RC:$src1, (VTI.LdFrag addr:$src2),71 (i32 timm:$src3)))>,72 EVEX, VVVV,73 Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;74 defm rmbi : AVX512_maskable<0x52, MRMSrcMem, VTI, (outs VTI.RC:$dst),75 (ins VTI.RC:$src1, VTI.ScalarMemOp:$src2, i32u8imm:$src3),76 OpStr, "$src3, ${src2}"#VTI.BroadcastStr#", $src1",77 "$src1, ${src2}"#VTI.BroadcastStr#", $src3",78 (VTI.VT (OpNode VTI.RC:$src1, (VTI.BroadcastLdFrag addr:$src2),79 (i32 timm:$src3)))>,80 EVEX, VVVV, EVEX_B,81 Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;82 }83}84 85multiclass avx10_minmax_packed_sae<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> {86 let Uses = []<Register>, mayRaiseFPException = 0 in87 defm Zrrib : AVX512_maskable<0x52, MRMSrcReg, VTI.info512, (outs VTI.info512.RC:$dst),88 (ins VTI.info512.RC:$src1, VTI.info512.RC:$src2, i32u8imm:$src3), OpStr,89 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",90 (VTI.info512.VT (OpNode (VTI.info512.VT VTI.info512.RC:$src1),91 (VTI.info512.VT VTI.info512.RC:$src2),92 (i32 timm:$src3)))>,93 EVEX, VVVV, EVEX_B, EVEX_V512, Sched<[WriteFMAX]>;94}95 96multiclass avx10_minmax_packed<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> {97 let Predicates = [HasAVX10_2] in {98 defm Z : avx10_minmax_packed_base<OpStr, VTI.info512, OpNode>, EVEX_V512;99 defm Z256 : avx10_minmax_packed_base<OpStr, VTI.info256, OpNode>, EVEX_V256;100 defm Z128 : avx10_minmax_packed_base<OpStr, VTI.info128, OpNode>, EVEX_V128;101 }102}103 104multiclass avx10_minmax_scalar<string OpStr, X86VectorVTInfo _, SDNode OpNode,105 SDNode OpNodeSAE> {106 let ExeDomain = _.ExeDomain, Predicates = [HasAVX10_2] in {107 let mayRaiseFPException = 1 in {108 let isCodeGenOnly = 1 in {109 def rri : AVX512Ii8<0x53, MRMSrcReg, (outs _.FRC:$dst),110 (ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3),111 !strconcat(OpStr, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),112 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2, (i32 timm:$src3)))]>,113 Sched<[WriteFMAX]>;114 115 def rmi : AVX512Ii8<0x53, MRMSrcMem, (outs _.FRC:$dst),116 (ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),117 !strconcat(OpStr, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),118 [(set _.FRC:$dst, (OpNode _.FRC:$src1, (_.ScalarLdFrag addr:$src2),119 (i32 timm:$src3)))]>,120 Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;121 }122 defm rri : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),123 (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),124 OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",125 (_.VT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),126 (i32 timm:$src3))),127 0, 0, 0, vselect_mask, "", "_Int">,128 Sched<[WriteFMAX]>;129 130 defm rmi : AVX512_maskable<0x53, MRMSrcMem, _, (outs VR128X:$dst),131 (ins VR128X:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),132 OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",133 (_.VT (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),134 (i32 timm:$src3))),135 0, 0, 0, vselect_mask, "", "_Int">,136 Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;137 }138 let Uses = []<Register>, mayRaiseFPException = 0 in139 defm rrib : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),140 (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),141 OpStr, "$src3, {sae}, $src2, $src1",142 "$src1, $src2, {sae}, $src3",143 (_.VT (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),144 (i32 timm:$src3))),145 0, 0, 0, vselect_mask, "", "_Int">,146 Sched<[WriteFMAX]>, EVEX_B;147 }148}149 150 151let mayRaiseFPException = 0 in152defm VMINMAXBF16 : avx10_minmax_packed<"vminmaxbf16", avx512vl_bf16_info, X86vminmax>,153 AVX512XDIi8Base, EVEX_CD8<16, CD8VF>, TA;154 155defm VMINMAXPD : avx10_minmax_packed<"vminmaxpd", avx512vl_f64_info, X86vminmax>,156 avx10_minmax_packed_sae<"vminmaxpd", avx512vl_f64_info, X86vminmaxSae>,157 AVX512PDIi8Base, REX_W, TA, EVEX_CD8<64, CD8VF>;158 159defm VMINMAXPH : avx10_minmax_packed<"vminmaxph", avx512vl_f16_info, X86vminmax>,160 avx10_minmax_packed_sae<"vminmaxph", avx512vl_f16_info, X86vminmaxSae>,161 AVX512PSIi8Base, TA, EVEX_CD8<16, CD8VF>;162 163defm VMINMAXPS : avx10_minmax_packed<"vminmaxps", avx512vl_f32_info, X86vminmax>,164 avx10_minmax_packed_sae<"vminmaxps", avx512vl_f32_info, X86vminmaxSae>,165 AVX512PDIi8Base, TA, EVEX_CD8<32, CD8VF>;166 167defm VMINMAXSD : avx10_minmax_scalar<"vminmaxsd", v2f64x_info, X86vminmaxs, X86vminmaxsSae>,168 AVX512AIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<64, CD8VT1>, REX_W;169defm VMINMAXSH : avx10_minmax_scalar<"vminmaxsh", v8f16x_info, X86vminmaxs, X86vminmaxsSae>,170 AVX512PSIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<16, CD8VT1>, TA;171defm VMINMAXSS : avx10_minmax_scalar<"vminmaxss", v4f32x_info, X86vminmaxs, X86vminmaxsSae>,172 AVX512AIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<32, CD8VT1>;173 174//-------------------------------------------------175// AVX10 SATCVT instructions176//-------------------------------------------------177 178multiclass avx10_sat_cvt_rmb<bits<8> Opc, string OpStr, X86FoldableSchedWrite sched,179 X86VectorVTInfo DestInfo,180 X86VectorVTInfo SrcInfo,181 SDNode MaskNode> {182 defm rr: AVX512_maskable<Opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),183 (ins SrcInfo.RC:$src), OpStr, "$src", "$src",184 (DestInfo.VT (MaskNode (SrcInfo.VT SrcInfo.RC:$src)))>,185 Sched<[sched]>;186 defm rm: AVX512_maskable<Opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),187 (ins SrcInfo.MemOp:$src), OpStr, "$src", "$src",188 (DestInfo.VT (MaskNode (SrcInfo.VT189 (SrcInfo.LdFrag addr:$src))))>,190 Sched<[sched.Folded, sched.ReadAfterFold]>;191 defm rmb: AVX512_maskable<Opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),192 (ins SrcInfo.ScalarMemOp:$src), OpStr,193 "${src}"#SrcInfo.BroadcastStr, "${src}"#SrcInfo.BroadcastStr,194 (DestInfo.VT (MaskNode (SrcInfo.VT195 (SrcInfo.BroadcastLdFrag addr:$src))))>, EVEX_B,196 Sched<[sched.Folded, sched.ReadAfterFold]>;197}198 199// Conversion with rounding control (RC)200multiclass avx10_sat_cvt_rc<bits<8> Opc, string OpStr, X86SchedWriteWidths sched,201 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo,202 SDNode MaskNode> {203 let Predicates = [HasAVX10_2], Uses = [MXCSR] in204 defm Zrrb : AVX512_maskable<Opc, MRMSrcReg, DestInfo.info512,205 (outs DestInfo.info512.RC:$dst),206 (ins SrcInfo.info512.RC:$src, AVX512RC:$rc),207 OpStr, "$rc, $src", "$src, $rc",208 (DestInfo.info512.VT209 (MaskNode (SrcInfo.info512.VT SrcInfo.info512.RC:$src),210 (i32 timm:$rc)))>,211 Sched<[sched.ZMM]>, EVEX, EVEX_RC, EVEX_B;212}213 214// Conversion with SAE215multiclass avx10_sat_cvt_sae<bits<8> Opc, string OpStr, X86SchedWriteWidths sched,216 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo,217 SDNode Node> {218 let Predicates = [HasAVX10_2], Uses = [MXCSR] in219 defm Zrrb : AVX512_maskable<Opc, MRMSrcReg, DestInfo.info512,220 (outs DestInfo.info512.RC:$dst),221 (ins SrcInfo.info512.RC:$src),222 OpStr, "{sae}, $src", "$src, {sae}",223 (DestInfo.info512.VT224 (Node (SrcInfo.info512.VT SrcInfo.info512.RC:$src)))>,225 Sched<[sched.ZMM]>, EVEX, EVEX_B;226}227 228multiclass avx10_sat_cvt_base<bits<8> Opc, string OpStr, X86SchedWriteWidths sched,229 SDNode MaskNode, AVX512VLVectorVTInfo DestInfo,230 AVX512VLVectorVTInfo SrcInfo> {231 let Predicates = [HasAVX10_2] in {232 defm Z : avx10_sat_cvt_rmb<Opc, OpStr, sched.ZMM,233 DestInfo.info512, SrcInfo.info512,234 MaskNode>,235 EVEX, EVEX_V512;236 defm Z256237 : avx10_sat_cvt_rmb<Opc, OpStr, sched.YMM,238 DestInfo.info256, SrcInfo.info256,239 MaskNode>,240 EVEX, EVEX_V256;241 defm Z128242 : avx10_sat_cvt_rmb<Opc, OpStr, sched.XMM,243 DestInfo.info128, SrcInfo.info128,244 MaskNode>,245 EVEX, EVEX_V128;246 }247}248 249defm VCVTBF162IBS : avx10_sat_cvt_base<0x69, "vcvtbf162ibs",250 SchedWriteVecIMul, X86vcvtp2ibs,251 avx512vl_i16_info, avx512vl_bf16_info>,252 AVX512XDIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;253defm VCVTBF162IUBS : avx10_sat_cvt_base<0x6b, "vcvtbf162iubs",254 SchedWriteVecIMul, X86vcvtp2iubs,255 avx512vl_i16_info, avx512vl_bf16_info>,256 AVX512XDIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;257 258defm VCVTPH2IBS : avx10_sat_cvt_base<0x69, "vcvtph2ibs", SchedWriteVecIMul,259 X86vcvtp2ibs, avx512vl_i16_info,260 avx512vl_f16_info>,261 avx10_sat_cvt_rc<0x69, "vcvtph2ibs", SchedWriteVecIMul,262 avx512vl_i16_info, avx512vl_f16_info,263 X86vcvtp2ibsRnd>,264 AVX512PSIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;265defm VCVTPH2IUBS : avx10_sat_cvt_base<0x6b, "vcvtph2iubs", SchedWriteVecIMul,266 X86vcvtp2iubs, avx512vl_i16_info,267 avx512vl_f16_info>,268 avx10_sat_cvt_rc<0x6b, "vcvtph2iubs", SchedWriteVecIMul,269 avx512vl_i16_info, avx512vl_f16_info,270 X86vcvtp2iubsRnd>,271 AVX512PSIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;272 273defm VCVTPS2IBS : avx10_sat_cvt_base<0x69, "vcvtps2ibs", SchedWriteVecIMul,274 X86vcvtp2ibs, avx512vl_i32_info,275 avx512vl_f32_info>,276 avx10_sat_cvt_rc<0x69, "vcvtps2ibs", SchedWriteVecIMul,277 avx512vl_i32_info, avx512vl_f32_info,278 X86vcvtp2ibsRnd>,279 AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;280defm VCVTPS2IUBS : avx10_sat_cvt_base<0x6b, "vcvtps2iubs", SchedWriteVecIMul,281 X86vcvtp2iubs, avx512vl_i32_info,282 avx512vl_f32_info>,283 avx10_sat_cvt_rc<0x6b, "vcvtps2iubs", SchedWriteVecIMul,284 avx512vl_i32_info, avx512vl_f32_info,285 X86vcvtp2iubsRnd>,286 AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;287 288defm VCVTTBF162IBS : avx10_sat_cvt_base<0x68, "vcvttbf162ibs",289 SchedWriteVecIMul, X86vcvttp2ibs,290 avx512vl_i16_info, avx512vl_bf16_info>,291 AVX512XDIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;292defm VCVTTBF162IUBS : avx10_sat_cvt_base<0x6a, "vcvttbf162iubs",293 SchedWriteVecIMul, X86vcvttp2iubs,294 avx512vl_i16_info, avx512vl_bf16_info>,295 AVX512XDIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;296 297defm VCVTTPH2IBS : avx10_sat_cvt_base<0x68, "vcvttph2ibs", SchedWriteVecIMul,298 X86vcvttp2ibs, avx512vl_i16_info,299 avx512vl_f16_info>,300 avx10_sat_cvt_sae<0x68, "vcvttph2ibs", SchedWriteVecIMul,301 avx512vl_i16_info, avx512vl_f16_info,302 X86vcvttp2ibsSAE>,303 AVX512PSIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;304defm VCVTTPH2IUBS : avx10_sat_cvt_base<0x6a, "vcvttph2iubs", SchedWriteVecIMul,305 X86vcvttp2iubs, avx512vl_i16_info,306 avx512vl_f16_info>,307 avx10_sat_cvt_sae<0x6a, "vcvttph2iubs", SchedWriteVecIMul,308 avx512vl_i16_info, avx512vl_f16_info,309 X86vcvttp2iubsSAE>,310 AVX512PSIi8Base, T_MAP5, EVEX_CD8<16, CD8VF>;311 312defm VCVTTPS2IBS : avx10_sat_cvt_base<0x68, "vcvttps2ibs", SchedWriteVecIMul,313 X86vcvttp2ibs, avx512vl_i32_info,314 avx512vl_f32_info>,315 avx10_sat_cvt_sae<0x68, "vcvttps2ibs", SchedWriteVecIMul,316 avx512vl_i32_info, avx512vl_f32_info,317 X86vcvttp2ibsSAE>,318 AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;319defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a, "vcvttps2iubs", SchedWriteVecIMul,320 X86vcvttp2iubs, avx512vl_i32_info,321 avx512vl_f32_info>,322 avx10_sat_cvt_sae<0x6a, "vcvttps2iubs", SchedWriteVecIMul,323 avx512vl_i32_info, avx512vl_f32_info,324 X86vcvttp2iubsSAE>,325 AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;326 327//-------------------------------------------------328// AVX10 SATCVT-DS instructions329//-------------------------------------------------330 331// Convert Double to Signed/Unsigned Doubleword with truncation.332multiclass avx10_cvttpd2dqs<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,333 SDNode MaskOpNode, SDNode OpNodeSAE,334 X86SchedWriteWidths sched> {335 let Predicates = [HasAVX10_2] in {336 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode,337 MaskOpNode, sched.ZMM>,338 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,339 OpNodeSAE, sched.ZMM>, EVEX_V512;340 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info,341 null_frag, null_frag, sched.XMM, "{1to2}", "{x}",342 f128mem, VK2WM>, EVEX_V128;343 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,344 MaskOpNode, sched.YMM, "{1to4}", "{y}">, EVEX_V256;345 }346 347 let Predicates = [HasAVX10_2], hasEVEX_U=1 in {348 defm Z256 : avx512_vcvt_fp_sae<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNodeSAE,349 sched.YMM>, EVEX_V256;350 }351 352 353 def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",354 (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,355 VR128X:$src), 0, "att">;356 def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",357 (!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,358 VK2WM:$mask, VR128X:$src), 0, "att">;359 def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",360 (!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,361 VK2WM:$mask, VR128X:$src), 0, "att">;362 def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",363 (!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst,364 f64mem:$src), 0, "att">;365 def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}}|"366 "$dst {${mask}}, ${src}{1to2}}",367 (!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,368 VK2WM:$mask, f64mem:$src), 0, "att">;369 def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}} {z}|"370 "$dst {${mask}} {z}, ${src}{1to2}}",371 (!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,372 VK2WM:$mask, f64mem:$src), 0, "att">;373 374 def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",375 (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,376 VR256X:$src), 0, "att">;377 def : InstAlias<OpcodeStr#"y\t{{sae} $src, $dst|$dst, $src {sae}}",378 (!cast<Instruction>(NAME # "Z256rrb") VR128X:$dst,379 VR256X:$src), 0, "att">;380 def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",381 (!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,382 VK4WM:$mask, VR256X:$src), 0, "att">;383 def : InstAlias<OpcodeStr#"y\t{{sae} $src, $dst {${mask}}|$dst {${mask}}, $src {sae}}",384 (!cast<Instruction>(NAME # "Z256rrbk") VR128X:$dst,385 VK4WM:$mask, VR256X:$src), 0, "att">;386 def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",387 (!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,388 VK4WM:$mask, VR256X:$src), 0, "att">;389 def : InstAlias<OpcodeStr#"y\t{{sae} $src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src {sae}}",390 (!cast<Instruction>(NAME # "Z256rrbkz") VR128X:$dst,391 VK4WM:$mask, VR256X:$src), 0, "att">;392 def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",393 (!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst,394 f64mem:$src), 0, "att">;395 def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}}|"396 "$dst {${mask}}, ${src}{1to4}}",397 (!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,398 VK4WM:$mask, f64mem:$src), 0, "att">;399 def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}} {z}|"400 "$dst {${mask}} {z}, ${src}{1to4}}",401 (!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,402 VK4WM:$mask, f64mem:$src), 0, "att">;403}404 405// Convert Double to Signed/Unsigned Quardword with truncation saturationn enabled406multiclass avx10_cvttpd2qqs<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,407 SDNode MaskOpNode, SDNode OpNodeRnd,408 X86SchedWriteWidths sched> {409 let Predicates = [HasAVX10_2] in {410 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode,411 MaskOpNode, sched.ZMM>,412 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,413 OpNodeRnd, sched.ZMM>, EVEX_V512;414 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode,415 MaskOpNode, sched.XMM>, EVEX_V128;416 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode,417 MaskOpNode, sched.YMM>, EVEX_V256;418 }419 let Predicates = [HasAVX10_2], hasEVEX_U=1 in {420 defm Z256 : avx512_vcvt_fp_sae<opc, OpcodeStr, v4i64x_info, v4f64x_info,421 OpNodeRnd, sched.YMM>, EVEX_V256;422 }423}424 425// Convert Float to Signed/Unsigned Quardword with truncation426multiclass avx10_cvttps2qqs<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,427 SDNode MaskOpNode, SDNode OpNodeRnd,428 X86SchedWriteWidths sched> {429 let Predicates = [HasAVX10_2] in {430 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode,431 MaskOpNode, sched.ZMM>,432 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,433 OpNodeRnd, sched.ZMM>, EVEX_V512;434 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,435 MaskOpNode, sched.XMM, "{1to2}", "", f64mem, VK2WM,436 (v2i64 (OpNode (bc_v4f32 (v2f64437 (scalar_to_vector (loadf64 addr:$src)))))),438 (v2i64 (MaskOpNode (bc_v4f32 (v2f64439 (scalar_to_vector (loadf64 addr:$src))))))>,440 EVEX_V128;441 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode,442 MaskOpNode, sched.YMM>, EVEX_V256;443 }444 445 let Predicates = [HasAVX10_2], hasEVEX_U=1 in {446 defm Z256 : avx512_vcvt_fp_sae<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNodeRnd,447 sched.YMM>, EVEX_V256;448 }449}450 451// Convert Float to Signed/Unsigned Doubleword with truncation452multiclass avx10_cvttps2dqs<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,453 SDNode MaskOpNode,454 SDNode OpNodeSAE, X86SchedWriteWidths sched> {455 let Predicates = [HasAVX10_2] in {456 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode,457 MaskOpNode, sched.ZMM>,458 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,459 OpNodeSAE, sched.ZMM>, EVEX_V512;460 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode,461 MaskOpNode, sched.XMM>, EVEX_V128;462 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode,463 MaskOpNode, sched.YMM>, EVEX_V256;464 }465}466 467defm VCVTTPD2DQS : avx10_cvttpd2dqs<0x6D, "vcvttpd2dqs", X86cvttp2sis,468 X86cvttp2sis, X86cvttp2sisSAE,469 SchedWriteCvtPD2DQ>,470 PD, REX_W, T_MAP5,PS, EVEX_CD8<64, CD8VF>;471defm VCVTTPD2UDQS : avx10_cvttpd2dqs<0x6C, "vcvttpd2udqs", X86cvttp2uis,472 X86cvttp2uis, X86cvttp2uisSAE,473 SchedWriteCvtPD2DQ>,474 REX_W, T_MAP5,PS, EVEX_CD8<64, CD8VF>;475defm VCVTTPS2DQS : avx10_cvttps2dqs<0x6D, "vcvttps2dqs", X86cvttp2sis,476 X86cvttp2sis, X86cvttp2sisSAE,477 SchedWriteCvtPS2DQ>, T_MAP5,PS,478 EVEX_CD8<32, CD8VF>;479defm VCVTTPS2UDQS : avx10_cvttps2dqs<0x6C, "vcvttps2udqs", X86cvttp2uis,480 X86cvttp2uis, X86cvttp2uisSAE,481 SchedWriteCvtPS2DQ>, T_MAP5,PS,482 EVEX_CD8<32, CD8VF>;483defm VCVTTPD2QQS : avx10_cvttpd2qqs<0x6D, "vcvttpd2qqs", X86cvttp2sis,484 X86cvttp2sis, X86cvttp2sisSAE,485 SchedWriteCvtPD2DQ>, REX_W, T_MAP5,PD,486 EVEX_CD8<64, CD8VF>;487defm VCVTTPS2QQS : avx10_cvttps2qqs<0x6D, "vcvttps2qqs", X86cvttp2sis,488 X86cvttp2sis, X86cvttp2sisSAE,489 SchedWriteCvtPS2DQ>, T_MAP5,PD,490 EVEX_CD8<32, CD8VH>;491defm VCVTTPD2UQQS : avx10_cvttpd2qqs<0x6C, "vcvttpd2uqqs", X86cvttp2uis,492 X86cvttp2uis, X86cvttp2uisSAE,493 SchedWriteCvtPD2DQ>, REX_W, T_MAP5,PD,494 EVEX_CD8<64, CD8VF>;495defm VCVTTPS2UQQS : avx10_cvttps2qqs<0x6C, "vcvttps2uqqs", X86cvttp2uis,496 X86cvttp2uis, X86cvttp2uisSAE,497 SchedWriteCvtPS2DQ>, T_MAP5,PD,498 EVEX_CD8<32, CD8VH>;499 500let Predicates = [HasAVX10_2] in {501// Special patterns to allow use of X86mcvttp2si for masking. Instruction502// patterns have been disabled with null_frag.503// Patterns VCVTTPD2DQSZ128504 505// VCVTTPD2DQS506def : Pat<(v4i32(X86fp2sisat(v2f64 VR128X:$src))),507 (VCVTTPD2DQSZ128rr VR128X:$src)>;508def : Pat<(v4i32(fp_to_sint_sat(v4f64 VR256X:$src), i32)),509 (VCVTTPD2DQSZ256rr VR256X:$src)>;510def : Pat<(v8i32(fp_to_sint_sat(v8f64 VR512:$src), i32)),511 (VCVTTPD2DQSZrr VR512:$src)>;512 513// VCVTTPD2QQS514def : Pat<(v2i64(fp_to_sint_sat(v2f64 VR128X:$src), i64)),515 (VCVTTPD2QQSZ128rr VR128X:$src)>;516def : Pat<(v4i64(fp_to_sint_sat(v4f64 VR256X:$src), i64)),517 (VCVTTPD2QQSZ256rr VR256X:$src)>;518def : Pat<(v8i64(fp_to_sint_sat(v8f64 VR512:$src), i64)),519 (VCVTTPD2QQSZrr VR512:$src)>;520 521// VCVTTPD2UDQS522def : Pat<(v4i32(X86fp2uisat(v2f64 VR128X:$src))),523 (VCVTTPD2UDQSZ128rr VR128X:$src)>;524def : Pat<(v4i32(fp_to_uint_sat(v4f64 VR256X:$src), i32)),525 (VCVTTPD2UDQSZ256rr VR256X:$src)>;526def : Pat<(v8i32(fp_to_uint_sat(v8f64 VR512:$src), i32)),527 (VCVTTPD2UDQSZrr VR512:$src)>;528 529// VCVTTPD2UQQS530def : Pat<(v2i64(fp_to_uint_sat(v2f64 VR128X:$src), i64)),531 (VCVTTPD2UQQSZ128rr VR128X:$src)>;532def : Pat<(v4i64(fp_to_uint_sat(v4f64 VR256X:$src), i64)),533 (VCVTTPD2UQQSZ256rr VR256X:$src)>;534def : Pat<(v8i64(fp_to_uint_sat(v8f64 VR512:$src), i64)),535 (VCVTTPD2UQQSZrr VR512:$src)>;536 537// VCVTTPS2DQS538def : Pat<(v4i32(fp_to_sint_sat(v4f32 VR128X:$src), i32)),539 (VCVTTPS2DQSZ128rr VR128X:$src)>;540def : Pat<(v8i32(fp_to_sint_sat(v8f32 VR256X:$src), i32)),541 (VCVTTPS2DQSZ256rr VR256X:$src)>;542def : Pat<(v16i32(fp_to_sint_sat(v16f32 VR512:$src), i32)),543 (VCVTTPS2DQSZrr VR512:$src)>;544 545// VCVTTPS2QQS546def : Pat<(v2i64(X86fp2sisat(v4f32 VR128X:$src))),547 (VCVTTPS2QQSZ128rr VR128X:$src)>;548def : Pat<(v4i64(fp_to_sint_sat(v4f32 VR128X:$src), i64)),549 (VCVTTPS2QQSZ256rr VR128X:$src)>;550def : Pat<(v8i64(fp_to_sint_sat(v8f32 VR256X:$src), i64)),551 (VCVTTPS2QQSZrr VR256X:$src)>;552 553// VCVTTPS2UDQS554def : Pat<(v4i32(fp_to_uint_sat(v4f32 VR128X:$src), i32)),555 (VCVTTPS2UDQSZ128rr VR128X:$src)>;556def : Pat<(v8i32(fp_to_uint_sat(v8f32 VR256X:$src), i32)),557 (VCVTTPS2UDQSZ256rr VR256X:$src)>;558def : Pat<(v16i32(fp_to_uint_sat(v16f32 VR512:$src), i32)),559 (VCVTTPS2UDQSZrr VR512:$src)>;560 561// VCVTTPS2UQQS562def : Pat<(v2i64(X86fp2uisat(v4f32 VR128X:$src))),563 (VCVTTPS2UQQSZ128rr VR128X:$src)>;564def : Pat<(v4i64(fp_to_uint_sat(v4f32 VR128X:$src), i64)),565 (VCVTTPS2UQQSZ256rr VR128X:$src)>;566def : Pat<(v8i64(fp_to_uint_sat(v8f32 VR256X:$src), i64)),567 (VCVTTPS2UQQSZrr VR256X:$src)>;568 569def : Pat<(v4i32 (X86cvttp2sis (v2f64 VR128X:$src))),570 (VCVTTPD2DQSZ128rr VR128X:$src)>;571def : Pat<(v4i32 (X86cvttp2sis (loadv2f64 addr:$src))),572 (VCVTTPD2DQSZ128rm addr:$src)>;573def : Pat<(v4i32 (X86cvttp2sis (v2f64 (X86VBroadcastld64 addr:$src)))),574 (VCVTTPD2DQSZ128rmb addr:$src)>;575def : Pat<(X86mcvttp2sis (v2f64 VR128X:$src), (v4i32 VR128X:$src0),576 VK2WM:$mask),577 (VCVTTPD2DQSZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;578def : Pat<(X86mcvttp2sis (v2f64 VR128X:$src), v4i32x_info.ImmAllZerosV,579 VK2WM:$mask),580 (VCVTTPD2DQSZ128rrkz VK2WM:$mask, VR128X:$src)>;581def : Pat<(X86mcvttp2sis (loadv2f64 addr:$src), (v4i32 VR128X:$src0),582 VK2WM:$mask),583 (VCVTTPD2DQSZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;584def : Pat<(X86mcvttp2sis (loadv2f64 addr:$src), v4i32x_info.ImmAllZerosV,585 VK2WM:$mask),586 (VCVTTPD2DQSZ128rmkz VK2WM:$mask, addr:$src)>;587def : Pat<(X86mcvttp2sis (v2f64 (X86VBroadcastld64 addr:$src)),588 (v4i32 VR128X:$src0), VK2WM:$mask),589 (VCVTTPD2DQSZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;590def : Pat<(X86mcvttp2sis (v2f64 (X86VBroadcastld64 addr:$src)),591 v4i32x_info.ImmAllZerosV, VK2WM:$mask),592 (VCVTTPD2DQSZ128rmbkz VK2WM:$mask, addr:$src)>;593 594// Patterns VCVTTPD2UDQSZ128595def : Pat<(v4i32 (X86cvttp2uis (v2f64 VR128X:$src))),596 (VCVTTPD2UDQSZ128rr VR128X:$src)>;597def : Pat<(v4i32 (X86cvttp2uis (loadv2f64 addr:$src))),598 (VCVTTPD2UDQSZ128rm addr:$src)>;599def : Pat<(v4i32 (X86cvttp2uis (v2f64 (X86VBroadcastld64 addr:$src)))),600 (VCVTTPD2UDQSZ128rmb addr:$src)>;601def : Pat<(X86mcvttp2uis (v2f64 VR128X:$src), (v4i32 VR128X:$src0),602 VK2WM:$mask),603 (VCVTTPD2UDQSZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;604def : Pat<(X86mcvttp2uis (v2f64 VR128X:$src), v4i32x_info.ImmAllZerosV,605 VK2WM:$mask),606 (VCVTTPD2UDQSZ128rrkz VK2WM:$mask, VR128X:$src)>;607def : Pat<(X86mcvttp2uis (loadv2f64 addr:$src), (v4i32 VR128X:$src0),608 VK2WM:$mask),609 (VCVTTPD2UDQSZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;610def : Pat<(X86mcvttp2uis (loadv2f64 addr:$src), v4i32x_info.ImmAllZerosV,611 VK2WM:$mask),612 (VCVTTPD2UDQSZ128rmkz VK2WM:$mask, addr:$src)>;613def : Pat<(X86mcvttp2uis (v2f64 (X86VBroadcastld64 addr:$src)),614 (v4i32 VR128X:$src0), VK2WM:$mask),615 (VCVTTPD2UDQSZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;616def : Pat<(X86mcvttp2uis (v2f64 (X86VBroadcastld64 addr:$src)),617 v4i32x_info.ImmAllZerosV, VK2WM:$mask),618 (VCVTTPD2UDQSZ128rmbkz VK2WM:$mask, addr:$src)>;619}620 621// Convert scalar float/double to signed/unsigned int 32/64 with truncation and saturation.622multiclass avx10_cvt_s_ds<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,623 X86VectorVTInfo _DstRC, SDPatternOperator OpNode,624 SDNode OpNodeInt, SDNode OpNodeSAE,625 X86FoldableSchedWrite sched> {626 let Predicates = [HasAVX10_2], ExeDomain = _SrcRC.ExeDomain in {627 let isCodeGenOnly = 1 in {628 def rr : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),629 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),630 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src, _DstRC.EltVT))]>,631 EVEX, VEX_LIG, Sched<[sched]>, SIMD_EXC;632 def rm : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src),633 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),634 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src), _DstRC.EltVT))]>,635 EVEX, VEX_LIG, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;636 }637 def rr_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),638 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),639 [(set _DstRC.RC:$dst, (OpNodeInt (_SrcRC.VT _SrcRC.RC:$src)))]>,640 EVEX, VEX_LIG, Sched<[sched]>, SIMD_EXC;641 let Uses = [MXCSR] in642 def rrb_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),643 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),644 [(set _DstRC.RC:$dst, (OpNodeSAE (_SrcRC.VT _SrcRC.RC:$src)))]>,645 EVEX, VEX_LIG, EVEX_B, Sched<[sched]>;646 def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst),647 (ins _SrcRC.IntScalarMemOp:$src),648 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),649 [(set _DstRC.RC:$dst,650 (OpNodeInt (_SrcRC.ScalarIntMemFrags addr:$src)))]>,651 EVEX, VEX_LIG, Sched<[sched.Folded, sched.ReadAfterFold]>,652 SIMD_EXC;653 }654}655 656defm VCVTTSS2SIS: avx10_cvt_s_ds<0x6D, "vcvttss2sis", f32x_info, i32x_info,657 fp_to_sint_sat, X86cvttss2Int,658 X86cvttss2IntSAE, WriteCvtSS2I>,659 T_MAP5,XS, EVEX_CD8<32, CD8VT1>;660defm VCVTTSS2SI64S: avx10_cvt_s_ds<0x6D, "vcvttss2sis", f32x_info, i64x_info,661 fp_to_sint_sat, X86cvttss2Int,662 X86cvttss2IntSAE, WriteCvtSS2I>,663 REX_W, T_MAP5,XS, EVEX_CD8<32, CD8VT1>;664defm VCVTTSD2SIS: avx10_cvt_s_ds<0x6D, "vcvttsd2sis", f64x_info, i32x_info,665 fp_to_sint_sat, X86cvttss2Int,666 X86cvttss2IntSAE, WriteCvtSD2I>,667 T_MAP5,XD, EVEX_CD8<64, CD8VT1>;668defm VCVTTSD2SI64S: avx10_cvt_s_ds<0x6D, "vcvttsd2sis", f64x_info, i64x_info,669 fp_to_sint_sat, X86cvttss2Int,670 X86cvttss2IntSAE, WriteCvtSD2I>,671 REX_W, T_MAP5,XD, EVEX_CD8<64, CD8VT1>;672defm VCVTTSS2USIS: avx10_cvt_s_ds<0x6C, "vcvttss2usis", f32x_info, i32x_info,673 fp_to_uint_sat, X86cvttss2UInt,674 X86cvttss2UIntSAE, WriteCvtSS2I>,675 T_MAP5,XS, EVEX_CD8<32, CD8VT1>;676defm VCVTTSS2USI64S: avx10_cvt_s_ds<0x6C, "vcvttss2usis", f32x_info, i64x_info,677 fp_to_uint_sat, X86cvttss2UInt,678 X86cvttss2UIntSAE, WriteCvtSS2I>,679 T_MAP5,XS,REX_W, EVEX_CD8<32, CD8VT1>;680defm VCVTTSD2USIS: avx10_cvt_s_ds<0x6C, "vcvttsd2usis", f64x_info, i32x_info,681 fp_to_uint_sat, X86cvttss2UInt,682 X86cvttss2UIntSAE, WriteCvtSD2I>,683 T_MAP5,XD, EVEX_CD8<64, CD8VT1>;684defm VCVTTSD2USI64S: avx10_cvt_s_ds<0x6C, "vcvttsd2usis", f64x_info, i64x_info,685 fp_to_uint_sat, X86cvttss2UInt,686 X86cvttss2UIntSAE, WriteCvtSD2I>,687 T_MAP5,XD, REX_W, EVEX_CD8<64, CD8VT1>;688 689//-------------------------------------------------690// AVX10 CONVERT instructions691//-------------------------------------------------692 693multiclass avx10_cvt2ps2ph_rc<bits<8> opc, string OpcodeStr, X86FoldableSchedWrite sched,694 X86VectorVTInfo _Src, X86VectorVTInfo _,695 SDNode OpNodeRnd> {696 let Uses = [MXCSR] in697 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),698 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,699 "$rc, $src2, $src1", "$src1, $src2, $rc",700 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),701 (_Src.VT _Src.RC:$src2), (i32 timm:$rc)))>,702 EVEX, VVVV, EVEX_B, EVEX_RC, PD, Sched<[sched]>;703}704 705//TODO: Merge into avx512_binop_all, difference is rounding control added here.706multiclass avx10_cvt2ps2ph<bits<8> opc, string OpcodeStr,707 X86SchedWriteWidths sched,708 AVX512VLVectorVTInfo _SrcVTInfo,709 AVX512VLVectorVTInfo _DstVTInfo,710 SDNode OpNode, SDNode OpNodeRnd> {711 let Predicates = [HasAVX10_2] in {712 defm Z : avx512_binop_rm2<opc, OpcodeStr, sched.ZMM, OpNode,713 _SrcVTInfo.info512, _DstVTInfo.info512,714 _SrcVTInfo.info512>,715 avx10_cvt2ps2ph_rc<opc, OpcodeStr, sched.ZMM,716 _SrcVTInfo.info512, _DstVTInfo.info512,717 OpNodeRnd>,718 EVEX_V512, EVEX_CD8<32, CD8VF>;719 defm Z256 : avx512_binop_rm2<opc, OpcodeStr, sched.YMM, OpNode,720 _SrcVTInfo.info256, _DstVTInfo.info256,721 _SrcVTInfo.info256>,722 EVEX_V256, EVEX_CD8<32, CD8VF>;723 defm Z128 : avx512_binop_rm2<opc, OpcodeStr, sched.XMM, OpNode,724 _SrcVTInfo.info128, _DstVTInfo.info128,725 _SrcVTInfo.info128>,726 EVEX_V128, EVEX_CD8<32, CD8VF>;727 }728}729 730defm VCVT2PS2PHX : avx10_cvt2ps2ph<0x67, "vcvt2ps2phx",731 SchedWriteCvtPD2PS,732 avx512vl_f32_info, avx512vl_f16_info,733 X86vfpround2, X86vfpround2Rnd>, T8;734 735defm VCVT2PH2BF8 : avx512_binop_all<0x74, "vcvt2ph2bf8", SchedWriteCvtPD2PS,736 avx512vl_f16_info, avx512vl_i8_info,737 X86vcvt2ph2bf8, [HasAVX10_2], [HasAVX10_2]>,738 EVEX_CD8<16, CD8VF>, T8, XD;739defm VCVT2PH2BF8S : avx512_binop_all<0x74, "vcvt2ph2bf8s", SchedWriteCvtPD2PS,740 avx512vl_f16_info, avx512vl_i8_info,741 X86vcvt2ph2bf8s, [HasAVX10_2], [HasAVX10_2]>,742 EVEX_CD8<16, CD8VF>, T_MAP5, XD;743defm VCVT2PH2HF8 : avx512_binop_all<0x18, "vcvt2ph2hf8", SchedWriteCvtPD2PS,744 avx512vl_f16_info, avx512vl_i8_info,745 X86vcvt2ph2hf8, [HasAVX10_2], [HasAVX10_2]>,746 EVEX_CD8<16, CD8VF>, T_MAP5, XD;747defm VCVT2PH2HF8S : avx512_binop_all<0x1b, "vcvt2ph2hf8s", SchedWriteCvtPD2PS,748 avx512vl_f16_info, avx512vl_i8_info,749 X86vcvt2ph2hf8s, [HasAVX10_2], [HasAVX10_2]>,750 EVEX_CD8<16, CD8VF>, T_MAP5, XD;751 752//TODO: Merge into avx512_vcvt_fp, diffrence is one more source register here.753multiclass avx10_convert_3op_packed<bits<8> OpCode, string OpcodeStr,754 X86VectorVTInfo vt_dst, X86VectorVTInfo vt_src1,755 X86VectorVTInfo vt_src2, SDPatternOperator OpNode,756 SDPatternOperator MaskOpNode, X86FoldableSchedWrite sched,757 string Broadcast = vt_src2.BroadcastStr,758 X86MemOperand MemOp = vt_src2.MemOp,759 RegisterClass MaskRC = vt_src2.KRCWM,760 dag LdDAG = (vt_dst.VT (OpNode (vt_src1.VT vt_src1.RC:$src1),761 (vt_src2.VT (vt_src2.LdFrag addr:$src2)))),762 dag MaskLdDAG = (vt_dst.VT (MaskOpNode (vt_src1.VT vt_src1.RC:$src1),763 (vt_src2.VT (vt_src2.LdFrag addr:$src2))))> {764 defm rr : AVX512_maskable_cvt<OpCode, MRMSrcReg, vt_dst, (outs vt_dst.RC:$dst),765 (ins vt_src1.RC:$src1, vt_src2.RC:$src2),766 (ins vt_dst.RC:$src0, MaskRC:$mask, vt_src1.RC:$src1, vt_src2.RC:$src2),767 (ins MaskRC:$mask, vt_src1.RC:$src1, vt_src2.RC:$src2),768 OpcodeStr, "$src2, $src1", "$src1, $src2",769 (vt_dst.VT (OpNode (vt_src1.VT vt_src1.RC:$src1),770 (vt_src2.VT vt_src2.RC:$src2))),771 (vselect_mask MaskRC:$mask,772 (vt_dst.VT (MaskOpNode (vt_src1.VT vt_src1.RC:$src1),773 (vt_src2.VT vt_src2.RC:$src2))),774 vt_dst.RC:$src0),775 (vselect_mask MaskRC:$mask,776 (vt_dst.VT (MaskOpNode (vt_src1.VT vt_src1.RC:$src1),777 (vt_src2.VT vt_src2.RC:$src2))),778 vt_dst.ImmAllZerosV)>,779 EVEX, VVVV, Sched<[sched]>;780 let mayLoad = 1 in781 defm rm : AVX512_maskable_cvt<OpCode, MRMSrcMem, vt_dst, (outs vt_dst.RC:$dst),782 (ins vt_src1.RC:$src1, MemOp:$src2),783 (ins vt_dst.RC:$src0, MaskRC:$mask, vt_src1.RC:$src1, MemOp:$src2),784 (ins MaskRC:$mask, vt_src1.RC:$src1, MemOp:$src2),785 OpcodeStr, "$src2, $src1", "$src1, $src2",786 LdDAG,787 (vselect_mask MaskRC:$mask, MaskLdDAG, vt_dst.RC:$src0),788 (vselect_mask MaskRC:$mask, MaskLdDAG, vt_dst.ImmAllZerosV)>,789 EVEX, VVVV, Sched<[sched]>;790 791 let mayLoad = 1 in792 defm rmb : AVX512_maskable_cvt<OpCode, MRMSrcMem, vt_dst, (outs vt_dst.RC:$dst),793 (ins vt_src1.RC:$src1, vt_src2.ScalarMemOp:$src2),794 (ins vt_dst.RC:$src0, MaskRC:$mask, vt_src1.RC:$src1,795 vt_src2.ScalarMemOp:$src2),796 (ins MaskRC:$mask, vt_src1.RC:$src1, vt_src2.ScalarMemOp:$src2),797 OpcodeStr,798 "${src2}"#Broadcast#", $src1", "$src1, ${src2}"#Broadcast,799 (vt_dst.VT (OpNode (vt_src1.VT vt_src1.RC:$src1), (vt_src2.VT800 (vt_src2.BroadcastLdFrag addr:$src2)))),801 (vselect_mask MaskRC:$mask,802 (vt_dst.VT803 (MaskOpNode804 (vt_src1.VT vt_src1.RC:$src1), (vt_src2.VT805 (vt_src2.BroadcastLdFrag addr:$src2)))),806 vt_dst.RC:$src0),807 (vselect_mask MaskRC:$mask,808 (vt_dst.VT809 (MaskOpNode810 (vt_src1.VT vt_src1.RC:$src1),811 (vt_src2.VT812 (vt_src2.BroadcastLdFrag addr:$src2)))),813 vt_dst.ImmAllZerosV)>,814 EVEX, VVVV, EVEX_B, Sched<[sched]>;815}816 817//TODO: Merge into avx512_cvt_trunc818multiclass avx10_convert_3op<bits<8> OpCode, string OpcodeStr,819 AVX512VLVectorVTInfo vt_dst, AVX512VLVectorVTInfo vt_src,820 X86SchedWriteWidths sched,821 SDPatternOperator OpNode,822 SDPatternOperator MaskOpNode,823 PatFrag bcast128 = vt_src.info128.BroadcastLdFrag,824 PatFrag loadVT128 = vt_src.info128.LdFrag,825 RegisterClass maskRC128 = vt_src.info128.KRCWM> {826 let Predicates = [HasAVX10_2] in {827 defm Z : avx10_convert_3op_packed<OpCode, OpcodeStr, vt_dst.info256,828 vt_dst.info512, vt_src.info512, OpNode, OpNode, sched.ZMM>,829 EVEX_V512, EVEX_CD8<16, CD8VF>;830 defm Z256 : avx10_convert_3op_packed<OpCode, OpcodeStr, vt_dst.info128,831 vt_dst.info256, vt_src.info256, OpNode, OpNode, sched.YMM>,832 EVEX_V256, EVEX_CD8<16, CD8VF>;833 defm Z128 : avx10_convert_3op_packed<OpCode, OpcodeStr, vt_dst.info128,834 vt_dst.info128, vt_src.info128,835 null_frag, null_frag, sched.XMM>,836 EVEX_V128, EVEX_CD8<16, CD8VF>;837 // Special patterns to allow use of MaskOpNode for masking 128 version. Instruction838 // patterns have been disabled with null_frag.839 def : Pat<(vt_dst.info128.VT (OpNode (vt_dst.info128.VT VR128X:$src1),840 (vt_src.info128.VT VR128X:$src2))),841 (!cast<Instruction>(NAME # "Z128rr") VR128X:$src1, VR128X:$src2)>;842 def : Pat<(MaskOpNode (vt_dst.info128.VT VR128X:$src1),843 (vt_src.info128.VT VR128X:$src2),844 (vt_dst.info128.VT VR128X:$src0), maskRC128:$mask),845 (!cast<Instruction>(NAME # "Z128rrk") VR128X:$src0, maskRC128:$mask,846 VR128X:$src1, VR128X:$src2)>;847 def : Pat<(MaskOpNode (vt_dst.info128.VT VR128X:$src1),848 (vt_src.info128.VT VR128X:$src2),849 vt_dst.info128.ImmAllZerosV, maskRC128:$mask),850 (!cast<Instruction>(NAME # "Z128rrkz") maskRC128:$mask,851 VR128X:$src1, VR128X:$src2)>;852 853 def : Pat<(vt_dst.info128.VT (OpNode (vt_dst.info128.VT VR128X:$src1),854 (loadVT128 addr:$src2))),855 (!cast<Instruction>(NAME # "Z128rm") VR128X:$src1, addr:$src2)>;856 def : Pat<(MaskOpNode (vt_dst.info128.VT VR128X:$src1),857 (loadVT128 addr:$src2),858 (vt_dst.info128.VT VR128X:$src0),859 maskRC128:$mask),860 (!cast<Instruction>(NAME # "Z128rmk") VR128X:$src0, maskRC128:$mask,861 VR128X:$src1, addr:$src2)>;862 def : Pat<(MaskOpNode (vt_dst.info128.VT VR128X:$src1),863 (loadVT128 addr:$src2),864 vt_dst.info128.ImmAllZerosV,865 maskRC128:$mask),866 (!cast<Instruction>(NAME # "Z128rmkz") maskRC128:$mask,867 VR128X:$src1, addr:$src2)>;868 869 def : Pat<(vt_dst.info128.VT (OpNode (vt_dst.info128.VT VR128X:$src1),870 (vt_src.info128.VT (bcast128 addr:$src2)))),871 (!cast<Instruction>(NAME # "Z128rmb") VR128X:$src1, addr:$src2)>;872 def : Pat<(MaskOpNode (vt_dst.info128.VT VR128X:$src1),873 (vt_src.info128.VT (bcast128 addr:$src2)),874 (vt_dst.info128.VT VR128X:$src0), maskRC128:$mask),875 (!cast<Instruction>(NAME # "Z128rmbk") VR128X:$src0, maskRC128:$mask,876 VR128X:$src1, addr:$src2)>;877 def : Pat<(MaskOpNode (vt_dst.info128.VT VR128X:$src1),878 (vt_src.info128.VT (bcast128 addr:$src2)),879 vt_dst.info128.ImmAllZerosV, maskRC128:$mask),880 (!cast<Instruction>(NAME # "Z128rmbkz") maskRC128:$mask,881 VR128X:$src1, addr:$src2)>;882 }883}884 885defm VCVTBIASPH2BF8 : avx10_convert_3op<0x74, "vcvtbiasph2bf8",886 avx512vl_i8_info, avx512vl_f16_info,887 SchedWriteCvtPD2PS,888 X86vcvtbiasph2bf8, X86vmcvtbiasph2bf8>,889 T8, PS;890defm VCVTBIASPH2BF8S : avx10_convert_3op<0x74, "vcvtbiasph2bf8s",891 avx512vl_i8_info, avx512vl_f16_info,892 SchedWriteCvtPD2PS,893 X86vcvtbiasph2bf8s, X86vmcvtbiasph2bf8s>,894 T_MAP5, PS;895defm VCVTBIASPH2HF8 : avx10_convert_3op<0x18, "vcvtbiasph2hf8",896 avx512vl_i8_info, avx512vl_f16_info,897 SchedWriteCvtPD2PS,898 X86vcvtbiasph2hf8, X86vmcvtbiasph2hf8>,899 T_MAP5, PS;900defm VCVTBIASPH2HF8S : avx10_convert_3op<0x1b, "vcvtbiasph2hf8s",901 avx512vl_i8_info, avx512vl_f16_info,902 SchedWriteCvtPD2PS,903 X86vcvtbiasph2hf8s, X86vmcvtbiasph2hf8s>,904 T_MAP5, PS;905 906defm VCVTPH2BF8 : avx512_cvt_trunc_ne<0x74, "vcvtph2bf8", avx512vl_i8_info,907 avx512vl_f16_info, SchedWriteCvtPD2PS,908 X86vcvtph2bf8, X86vmcvtph2bf8,909 [HasAVX10_2], [HasAVX10_2]>,910 T8, XS, EVEX_CD8<16, CD8VF>;911 912defm VCVTPH2BF8S : avx512_cvt_trunc_ne<0x74, "vcvtph2bf8s", avx512vl_i8_info,913 avx512vl_f16_info, SchedWriteCvtPD2PS,914 X86vcvtph2bf8s, X86vmcvtph2bf8s,915 [HasAVX10_2], [HasAVX10_2]>,916 T_MAP5, XS, EVEX_CD8<16, CD8VF>;917 918defm VCVTPH2HF8 : avx512_cvt_trunc_ne<0x18, "vcvtph2hf8", avx512vl_i8_info,919 avx512vl_f16_info, SchedWriteCvtPD2PS,920 X86vcvtph2hf8, X86vmcvtph2hf8,921 [HasAVX10_2], [HasAVX10_2]>,922 T_MAP5, XS, EVEX_CD8<16, CD8VF>;923 924defm VCVTPH2HF8S : avx512_cvt_trunc_ne<0x1b, "vcvtph2hf8s", avx512vl_i8_info,925 avx512vl_f16_info, SchedWriteCvtPD2PS,926 X86vcvtph2hf8s, X86vmcvtph2hf8s,927 [HasAVX10_2], [HasAVX10_2]>,928 T_MAP5, XS, EVEX_CD8<16, CD8VF>;929 930multiclass avx10_convert_2op_nomb_packed<bits<8> opc, string OpcodeStr,931 X86VectorVTInfo _dest, X86VectorVTInfo _src,932 SDNode OpNode, X86MemOperand x86memop,933 X86FoldableSchedWrite sched,934 dag ld_dag = (load addr:$src)> {935 let ExeDomain = _dest.ExeDomain in {936 defm rr : AVX512_maskable_split<opc, MRMSrcReg, _dest ,(outs _dest.RC:$dst),937 (ins _src.RC:$src), OpcodeStr, "$src", "$src",938 (OpNode (_src.VT _src.RC:$src)),939 (OpNode (_src.VT _src.RC:$src))>,940 Sched<[sched]>;941 defm rm : AVX512_maskable_split<opc, MRMSrcMem, _dest, (outs _dest.RC:$dst),942 (ins x86memop:$src), OpcodeStr, "$src", "$src",943 (OpNode (_src.VT ld_dag)),944 (OpNode (_src.VT ld_dag))>,945 Sched<[sched.Folded]>;946 }947}948 949multiclass avx10_convert_2op_nomb<string OpcodeStr, AVX512VLVectorVTInfo _dest,950 AVX512VLVectorVTInfo _src, bits<8> opc, SDNode OpNode> {951 let Predicates = [HasAVX10_2] in {952 defm Z : avx10_convert_2op_nomb_packed<opc, OpcodeStr, _dest.info512, _src.info256,953 OpNode, f256mem, WriteCvtPH2PSZ>, EVEX_V512;954 defm Z128 : avx10_convert_2op_nomb_packed<opc, OpcodeStr, _dest.info128, _src.info128,955 OpNode, f64mem, WriteCvtPH2PSZ>, EVEX_V128;956 defm Z256 : avx10_convert_2op_nomb_packed<opc, OpcodeStr, _dest.info256, _src.info128,957 OpNode, f128mem, WriteCvtPH2PSZ>, EVEX_V256;958 }959}960 961defm VCVTHF82PH : avx10_convert_2op_nomb<"vcvthf82ph", avx512vl_f16_info,962 avx512vl_i8_info, 0x1e, X86vcvthf82ph>,963 AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;964 965//-------------------------------------------------966// AVX10 BF16 instructions967//-------------------------------------------------968 969// VADDBF16, VSUBBF16, VMULBF16, VDIVBF16, VMAXBF16, VMINBF16970multiclass avx10_fp_binop_int_bf16<bits<8> opc, string OpcodeStr,971 X86SchedWriteSizes sched,972 bit IsCommutable = 0> {973 let Predicates = [HasAVX10_2] in {974 defm Z : avx512_fp_packed<opc, OpcodeStr,975 !cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"bf16512"),976 !cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"bf16512"),977 v32bf16_info, sched.PH.ZMM, IsCommutable>, EVEX_V512,978 T_MAP5, PD, EVEX_CD8<16, CD8VF>;979 defm Z128 : avx512_fp_packed<opc, OpcodeStr,980 !cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"bf16128"),981 !cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"bf16128"),982 v8bf16x_info, sched.PH.XMM, IsCommutable>, EVEX_V128,983 T_MAP5, PD, EVEX_CD8<16, CD8VF>;984 defm Z256 : avx512_fp_packed<opc, OpcodeStr,985 !cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"bf16256"),986 !cast<Intrinsic>("int_x86_avx10_"#OpcodeStr#"bf16256"),987 v16bf16x_info, sched.PH.YMM, IsCommutable>, EVEX_V256,988 T_MAP5, PD, EVEX_CD8<16, CD8VF>;989 }990}991 992multiclass avx10_fp_binop_bf16<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,993 X86SchedWriteSizes sched,994 bit IsCommutable = 0,995 SDPatternOperator MaskOpNode = OpNode> {996 let Predicates = [HasAVX10_2] in {997 defm Z : avx512_fp_packed<opc, OpcodeStr, OpNode, MaskOpNode, 998 v32bf16_info, sched.PH.ZMM, IsCommutable>, EVEX_V512,999 T_MAP5, PD, EVEX_CD8<16, CD8VF>;1000 defm Z128 : avx512_fp_packed<opc, OpcodeStr, OpNode, MaskOpNode, 1001 v8bf16x_info, sched.PH.XMM, IsCommutable>, EVEX_V128,1002 T_MAP5, PD, EVEX_CD8<16, CD8VF>;1003 defm Z256 : avx512_fp_packed<opc, OpcodeStr, OpNode, MaskOpNode, 1004 v16bf16x_info, sched.PH.YMM, IsCommutable>, EVEX_V256,1005 T_MAP5, PD, EVEX_CD8<16, CD8VF>;1006 }1007}1008 1009let Uses = []<Register>, mayRaiseFPException = 0 in {1010defm VADDBF16 : avx10_fp_binop_bf16<0x58, "vadd", fadd, SchedWriteFAddSizes, 1>;1011defm VSUBBF16 : avx10_fp_binop_bf16<0x5C, "vsub", fsub, SchedWriteFAddSizes, 0>;1012defm VMULBF16 : avx10_fp_binop_bf16<0x59, "vmul", fmul, SchedWriteFMulSizes, 1>;1013defm VDIVBF16 : avx10_fp_binop_bf16<0x5E, "vdiv", fdiv, SchedWriteFDivSizes, 0>;1014defm VMINBF16 : avx10_fp_binop_int_bf16<0x5D, "vmin", SchedWriteFCmpSizes, 0>;1015defm VMAXBF16 : avx10_fp_binop_int_bf16<0x5F, "vmax", SchedWriteFCmpSizes, 0>;1016}1017 1018// VCOMISBF161019let Uses = []<Register>, mayRaiseFPException = 0,1020 Defs = [EFLAGS], Predicates = [HasAVX10_2] in {1021 //TODO: Replace null_frag with X86fcmp to support lowering `fcmp oeq bfloat *`1022 //which may require extend supports on BFR16X, loadbf16, ...1023 defm VCOMISBF16Z : sse12_ord_cmp<0x2F, FR16X, null_frag, bf16, f16mem, loadf16,1024 "comisbf16", SSEPackedSingle>, T_MAP5, PD, EVEX,1025 VEX_LIG, EVEX_CD8<16, CD8VT1>;1026 1027 let isCodeGenOnly = 1 in {1028 defm VCOMISBF16Z : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v8bf16, f16mem,1029 sse_load_bf16, "comisbf16", SSEPackedSingle>,1030 T_MAP5, PD, EVEX, VEX_LIG, EVEX_CD8<16, CD8VT1>;1031 }1032}1033 1034// VCMPBF161035multiclass avx10_vcmp_common_bf16<X86FoldableSchedWrite sched, X86VectorVTInfo _> {1036 let mayRaiseFPException = 0 in {1037 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,1038 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),1039 "vcmp"#_.Suffix,1040 "$cc, $src2, $src1", "$src1, $src2, $cc",1041 (X86cmpm (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc),1042 (X86cmpm_su (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc),1043 1>, Sched<[sched]>;1044 1045 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,1046 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),1047 "vcmp"#_.Suffix,1048 "$cc, $src2, $src1", "$src1, $src2, $cc",1049 (X86cmpm (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)),1050 timm:$cc),1051 (X86cmpm_su (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)),1052 timm:$cc)>,1053 Sched<[sched.Folded, sched.ReadAfterFold]>;1054 1055 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,1056 (outs _.KRC:$dst),1057 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),1058 "vcmp"#_.Suffix,1059 "$cc, ${src2}"#_.BroadcastStr#", $src1",1060 "$src1, ${src2}"#_.BroadcastStr#", $cc",1061 (X86cmpm (_.VT _.RC:$src1),1062 (_.VT (_.BroadcastLdFrag addr:$src2)),1063 timm:$cc),1064 (X86cmpm_su (_.VT _.RC:$src1),1065 (_.VT (_.BroadcastLdFrag addr:$src2)),1066 timm:$cc)>,1067 EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;1068 }1069}1070 1071multiclass avx10_vcmp_bf16<X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> {1072 let Predicates = [HasAVX10_2] in {1073 defm Z : avx10_vcmp_common_bf16<sched.ZMM, _.info512>, EVEX_V512;1074 defm Z128 : avx10_vcmp_common_bf16<sched.XMM, _.info128>, EVEX_V128;1075 defm Z256 : avx10_vcmp_common_bf16<sched.YMM, _.info256>, EVEX_V256;1076 }1077}1078 1079defm VCMPBF16 : avx10_vcmp_bf16<SchedWriteFCmp, avx512vl_bf16_info>,1080 AVX512XDIi8Base, EVEX, VVVV,1081 EVEX_CD8<16, CD8VF>, TA;1082 1083 1084// VSQRTBF161085multiclass avx10_sqrt_packed_bf16<bits<8> opc, string OpcodeStr,1086 X86SchedWriteSizes sched> {1087 let Predicates = [HasAVX10_2] in {1088 defm Z : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "bf16"),1089 sched.PH.ZMM, v32bf16_info>,1090 EVEX_V512, PD, T_MAP5, EVEX_CD8<16, CD8VF>;1091 defm Z128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "bf16"),1092 sched.PH.XMM, v8bf16x_info>,1093 EVEX_V128, PD, T_MAP5, EVEX_CD8<16, CD8VF>;1094 defm Z256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "bf16"),1095 sched.PH.YMM, v16bf16x_info>,1096 EVEX_V256, PD, T_MAP5, EVEX_CD8<16, CD8VF>;1097 }1098}1099 1100let Uses = []<Register>, mayRaiseFPException = 0 in1101defm VSQRTBF16 : avx10_sqrt_packed_bf16<0x51, "vsqrt", SchedWriteFSqrtSizes>;1102 1103// VRSQRTBF16, VRCPBF16, VSRQTBF16, VGETEXPBF161104multiclass avx10_fp14_bf16<bits<8> opc, string OpcodeStr, SDNode OpNode,1105 X86SchedWriteWidths sched> {1106 let Predicates = [HasAVX10_2] in {1107 defm BF16Z : avx512_fp14_p<opc, !strconcat(OpcodeStr, "bf16"),1108 OpNode, sched.ZMM, v32bf16_info>,1109 EVEX_V512;1110 defm BF16Z128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "bf16"),1111 OpNode, sched.XMM, v8bf16x_info>,1112 EVEX_V128;1113 defm BF16Z256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "bf16"),1114 OpNode, sched.YMM, v16bf16x_info>,1115 EVEX_V256;1116 }1117}1118 1119defm VRSQRT : avx10_fp14_bf16<0x4E, "vrsqrt", X86rsqrt14, SchedWriteFRsqrt>,1120 T_MAP6, PS, EVEX_CD8<16, CD8VF>;1121defm VRCP : avx10_fp14_bf16<0x4C, "vrcp", X86rcp14, SchedWriteFRcp>,1122 T_MAP6, PS, EVEX_CD8<16, CD8VF>;1123defm VGETEXP : avx10_fp14_bf16<0x42, "vgetexp", X86fgetexp, SchedWriteFRnd>,1124 T_MAP6, PS, EVEX_CD8<16, CD8VF>;1125 1126// VSCALEFBF161127multiclass avx10_fp_scalef_bf16<bits<8> opc, string OpcodeStr,1128 X86SchedWriteWidths sched> {1129 let Predicates = [HasAVX10_2] in {1130 defm Z : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.ZMM, v32bf16_info>,1131 EVEX_V512, T_MAP6, PS, EVEX_CD8<16, CD8VF>;1132 defm Z128 : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.XMM, v8bf16x_info>,1133 EVEX_V128, EVEX_CD8<16, CD8VF>, T_MAP6, PS;1134 defm Z256 : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.YMM, v16bf16x_info>,1135 EVEX_V256, EVEX_CD8<16, CD8VF>, T_MAP6, PS;1136 }1137}1138 1139let Uses = []<Register>, mayRaiseFPException = 0 in1140defm VSCALEFBF16 : avx10_fp_scalef_bf16<0x2C, "vscalef", SchedWriteFAdd>;1141 1142// VREDUCEBF16, VRNDSCALEBF16, VGETMANTBF161143multiclass avx10_common_unary_fp_packed_imm_bf16<string OpcodeStr,1144 AVX512VLVectorVTInfo _, bits<8> opc, SDPatternOperator OpNode,1145 SDPatternOperator MaskOpNode, X86SchedWriteWidths sched> {1146 let Predicates = [HasAVX10_2] in {1147 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, MaskOpNode,1148 sched.ZMM, _.info512>, EVEX_V512;1149 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, MaskOpNode,1150 sched.XMM, _.info128>, EVEX_V128;1151 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, MaskOpNode,1152 sched.YMM, _.info256>, EVEX_V256;1153 }1154}1155 1156let Uses = []<Register>, mayRaiseFPException = 0 in {1157defm VREDUCEBF16 : avx10_common_unary_fp_packed_imm_bf16<"vreduce", avx512vl_bf16_info, 0x56,1158 X86VReduce, X86VReduce, SchedWriteFRnd>,1159 AVX512XDIi8Base, TA, EVEX, EVEX_CD8<16, CD8VF>;1160defm VRNDSCALEBF16 : avx10_common_unary_fp_packed_imm_bf16<"vrndscale", avx512vl_bf16_info, 0x08,1161 X86any_VRndScale, X86VRndScale, SchedWriteFRnd>,1162 AVX512XDIi8Base, TA, EVEX, EVEX_CD8<16, CD8VF>;1163defm VGETMANTBF16 : avx10_common_unary_fp_packed_imm_bf16<"vgetmant", avx512vl_bf16_info, 0x26,1164 X86VGetMant, X86VGetMant, SchedWriteFRnd>,1165 AVX512XDIi8Base, TA, EVEX, EVEX_CD8<16, CD8VF>;1166}1167 1168// VFPCLASSBF161169multiclass avx10_fp_fpclass_bf16<string OpcodeStr, bits<8> opcVec,1170 X86SchedWriteWidths sched> {1171 let Predicates = [HasAVX10_2] in {1172 defm Z : avx512_vector_fpclass<opcVec, OpcodeStr, sched.ZMM,1173 avx512vl_bf16_info.info512, "z",1174 []<Register>>, EVEX_V512;1175 defm Z128 : avx512_vector_fpclass<opcVec, OpcodeStr, sched.XMM,1176 avx512vl_bf16_info.info128, "x",1177 []<Register>>, EVEX_V128;1178 defm Z256 : avx512_vector_fpclass<opcVec, OpcodeStr, sched.YMM,1179 avx512vl_bf16_info.info256, "y",1180 []<Register>>, EVEX_V256;1181 }1182}1183 1184defm VFPCLASSBF16 : avx10_fp_fpclass_bf16<"vfpclass", 0x66, SchedWriteFCmp>,1185 AVX512XDIi8Base, TA, EVEX, EVEX_CD8<16, CD8VF>;1186 1187// VF[,N]M[ADD,SUB][132,213,231]BF161188multiclass avx10_fma3p_213_bf16<bits<8> opc, string OpcodeStr,1189 SDPatternOperator OpNode, SDNode MaskOpNode,1190 X86SchedWriteWidths sched> {1191 let Predicates = [HasAVX10_2] in {1192 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, MaskOpNode,1193 sched.ZMM, v32bf16_info>, EVEX_V512, T_MAP6, PS,1194 EVEX_CD8<16, CD8VF>;1195 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, MaskOpNode,1196 sched.XMM, v8bf16x_info>, EVEX_V128, T_MAP6, PS,1197 EVEX_CD8<16, CD8VF>;1198 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, MaskOpNode,1199 sched.YMM, v16bf16x_info>, EVEX_V256, T_MAP6, PS,1200 EVEX_CD8<16, CD8VF>;1201 }1202}1203 1204let Uses = []<Register>, mayRaiseFPException = 0 in {1205defm VFMADD213BF16 : avx10_fma3p_213_bf16<0xA8, "vfmadd213bf16", any_fma,1206 fma, SchedWriteFMA>;1207defm VFMSUB213BF16 : avx10_fma3p_213_bf16<0xAA, "vfmsub213bf16", X86any_Fmsub,1208 X86Fmsub, SchedWriteFMA>;1209defm VFNMADD213BF16 : avx10_fma3p_213_bf16<0xAC, "vfnmadd213bf16", X86any_Fnmadd,1210 X86Fnmadd, SchedWriteFMA>;1211defm VFNMSUB213BF16 : avx10_fma3p_213_bf16<0xAE, "vfnmsub213bf16", X86any_Fnmsub,1212 X86Fnmsub, SchedWriteFMA>;1213}1214 1215multiclass avx10_fma3p_231_bf16<bits<8> opc, string OpcodeStr,1216 SDPatternOperator OpNode, SDNode MaskOpNode,1217 X86SchedWriteWidths sched> {1218 let Predicates = [HasAVX10_2] in {1219 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, MaskOpNode,1220 sched.ZMM, v32bf16_info>, EVEX_V512, T_MAP6, PS,1221 EVEX_CD8<16, CD8VF>;1222 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, MaskOpNode,1223 sched.XMM, v8bf16x_info>, EVEX_V128, T_MAP6, PS,1224 EVEX_CD8<16, CD8VF>;1225 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, MaskOpNode,1226 sched.YMM, v16bf16x_info>, EVEX_V256, T_MAP6, PS,1227 EVEX_CD8<16, CD8VF>;1228 }1229}1230 1231let Uses = []<Register>, mayRaiseFPException = 0 in {1232defm VFMADD231BF16 : avx10_fma3p_231_bf16<0xB8, "vfmadd231bf16", any_fma,1233 fma, SchedWriteFMA>;1234defm VFMSUB231BF16 : avx10_fma3p_231_bf16<0xBA, "vfmsub231bf16", X86any_Fmsub,1235 X86Fmsub, SchedWriteFMA>;1236defm VFNMADD231BF16 : avx10_fma3p_231_bf16<0xBC, "vfnmadd231bf16", X86any_Fnmadd,1237 X86Fnmadd, SchedWriteFMA>;1238defm VFNMSUB231BF16 : avx10_fma3p_231_bf16<0xBE, "vfnmsub231bf16", X86any_Fnmsub,1239 X86Fnmsub, SchedWriteFMA>;1240}1241 1242multiclass avx10_fma3p_132_bf16<bits<8> opc, string OpcodeStr,1243 SDPatternOperator OpNode, SDNode MaskOpNode,1244 X86SchedWriteWidths sched> {1245 let Predicates = [HasAVX10_2] in {1246 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, MaskOpNode,1247 sched.ZMM, v32bf16_info>, EVEX_V512, T_MAP6, PS,1248 EVEX_CD8<16, CD8VF>;1249 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, MaskOpNode,1250 sched.XMM, v8bf16x_info>, EVEX_V128, T_MAP6, PS,1251 EVEX_CD8<16, CD8VF>;1252 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, MaskOpNode,1253 sched.YMM, v16bf16x_info>, EVEX_V256, T_MAP6, PS,1254 EVEX_CD8<16, CD8VF>;1255 }1256}1257 1258let Uses = []<Register>, mayRaiseFPException = 0 in {1259defm VFMADD132BF16 : avx10_fma3p_132_bf16<0x98, "vfmadd132bf16", any_fma,1260 fma, SchedWriteFMA>;1261defm VFMSUB132BF16 : avx10_fma3p_132_bf16<0x9A, "vfmsub132bf16", X86any_Fmsub,1262 X86Fmsub, SchedWriteFMA>;1263defm VFNMADD132BF16 : avx10_fma3p_132_bf16<0x9C, "vfnmadd132bf16", X86any_Fnmadd,1264 X86Fnmadd, SchedWriteFMA>;1265defm VFNMSUB132BF16 : avx10_fma3p_132_bf16<0x9E, "vfnmsub132bf16", X86any_Fnmsub,1266 X86Fnmsub, SchedWriteFMA>;1267}1268 1269//-------------------------------------------------1270// AVX10 COMEF instructions1271//-------------------------------------------------1272multiclass avx10_com_ef<bits<8> Opc, RegisterClass RC, ValueType VT,1273 SDPatternOperator OpNode, string OpcodeStr,1274 X86MemOperand x86memop, PatFrag ld_frag,1275 Domain d, X86FoldableSchedWrite sched = WriteFComX>{1276 let ExeDomain = d, mayRaiseFPException = 1, isCodeGenOnly = 1 in {1277 def rr : AVX512<Opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),1278 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),1279 [(set EFLAGS, (OpNode (VT RC:$src1), RC:$src2))]>,1280 EVEX, EVEX_V128, Sched<[sched]>, SIMD_EXC;1281 let mayLoad = 1 in {1282 def rm : AVX512<Opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),1283 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),1284 [(set EFLAGS, (OpNode (VT RC:$src1), (ld_frag addr:$src2)))]>,1285 EVEX, EVEX_V128, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;1286 }1287 }1288}1289 1290multiclass avx10_com_ef_int<bits<8> Opc, X86VectorVTInfo _, SDNode OpNode,1291 string OpcodeStr,1292 Domain d,1293 X86FoldableSchedWrite sched = WriteFComX> {1294 let ExeDomain = d, mayRaiseFPException = 1 in {1295 def rr_Int : AVX512<Opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),1296 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),1297 [(set EFLAGS, (OpNode (_.VT _.RC:$src1), _.RC:$src2))]>,1298 EVEX, EVEX_V128, Sched<[sched]>, SIMD_EXC;1299 let mayLoad = 1 in {1300 def rm_Int : AVX512<Opc, MRMSrcMem, (outs), (ins _.RC:$src1, _.ScalarMemOp:$src2),1301 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),1302 [(set EFLAGS, (OpNode (_.VT _.RC:$src1), (_.LdFrag addr:$src2)))]>,1303 EVEX, EVEX_V128, Sched<[sched]>, SIMD_EXC;1304 }1305 def rrb_Int : AVX512<Opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),1306 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),1307 []>,1308 EVEX, EVEX_V128, EVEX_B, Sched<[sched]>, SIMD_EXC;1309 }1310}1311 1312let Defs = [EFLAGS], Uses = [MXCSR], Predicates = [HasAVX10_2] in {1313 defm VUCOMXSDZ : avx10_com_ef<0x2e, FR64X, f64, X86ucomi512,1314 "vucomxsd", f64mem, loadf64, SSEPackedDouble>,1315 TB, XD, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;1316 defm VUCOMXSHZ : avx10_com_ef<0x2e, FR16X, f16, X86ucomi512,1317 "vucomxsh", f16mem, loadf16, SSEPackedSingle>,1318 T_MAP5, XS, EVEX_CD8<16, CD8VT1>;1319 defm VUCOMXSSZ : avx10_com_ef<0x2e, FR32X, f32, X86ucomi512,1320 "vucomxss", f32mem, loadf32, SSEPackedSingle>,1321 TB, XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;1322 defm VCOMXSDZ : avx10_com_ef_int<0x2f, v2f64x_info, X86comi512,1323 "vcomxsd", SSEPackedDouble>,1324 TB, XD, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;1325 defm VCOMXSHZ : avx10_com_ef_int<0x2f, v8f16x_info, X86comi512,1326 "vcomxsh", SSEPackedSingle>,1327 T_MAP5, XS, EVEX_CD8<16, CD8VT1>;1328 defm VCOMXSSZ : avx10_com_ef_int<0x2f, v4f32x_info, X86comi512,1329 "vcomxss", SSEPackedSingle>,1330 TB, XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;1331 defm VUCOMXSDZ : avx10_com_ef_int<0x2e, v2f64x_info, X86ucomi512,1332 "vucomxsd", SSEPackedDouble>,1333 TB, XD, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;1334 defm VUCOMXSHZ : avx10_com_ef_int<0x2e, v8f16x_info, X86ucomi512,1335 "vucomxsh", SSEPackedSingle>,1336 T_MAP5, XS, EVEX_CD8<16, CD8VT1>;1337 defm VUCOMXSSZ : avx10_com_ef_int<0x2e, v4f32x_info, X86ucomi512,1338 "vucomxss", SSEPackedSingle>,1339 TB, XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;1340}1341 1342//-------------------------------------------------1343// AVX10 MOVZXC (COPY) instructions1344//-------------------------------------------------1345let Predicates = [HasAVX10_2] in {1346 def VMOVZPDILo2PDIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),1347 (ins VR128X:$src),1348 "vmovd\t{$src, $dst|$dst, $src}",1349 [(set VR128X:$dst, (v4i32 (X86vzmovl1350 (v4i32 VR128X:$src))))]>, EVEX,1351 Sched<[WriteVecMoveFromGpr]>;1352 1353let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in1354 def VMOVZPDILo2PDIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),1355 (ins i32mem:$src),1356 "vmovd\t{$src, $dst|$dst, $src}", []>, EVEX,1357 EVEX_CD8<32, CD8VT1>,1358 Sched<[WriteVecLoad]>;1359 1360let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in1361 def VMOVZPDILo2PDIZmr : AVX512PDI<0xD6, MRMDestMem, (outs),1362 (ins i32mem:$dst, VR128X:$src),1363 "vmovd\t{$src, $dst|$dst, $src}", []>, EVEX,1364 EVEX_CD8<32, CD8VT1>,1365 Sched<[WriteVecStore]>;1366 1367let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in1368 def VMOVZPDILo2PDIZrr2 : AVX512PDI<0xD6, MRMSrcReg, (outs VR128X:$dst),1369 (ins VR128X:$src),1370 "vmovd\t{$src, $dst|$dst, $src}", []>, EVEX,1371 Sched<[WriteVecMoveFromGpr]>;1372 def : InstAlias<"vmovd.s\t{$src, $dst|$dst, $src}",1373 (VMOVZPDILo2PDIZrr2 VR128X:$dst, VR128X:$src), 0>;1374 1375def VMOVZPWILo2PWIZrr : AVX512XSI<0x6E, MRMSrcReg, (outs VR128X:$dst),1376 (ins VR128X:$src),1377 "vmovw\t{$src, $dst|$dst, $src}",1378 [(set VR128X:$dst, (v8i16 (X86vzmovl1379 (v8i16 VR128X:$src))))]>, EVEX, T_MAP5,1380 Sched<[WriteVecMoveFromGpr]>;1381 1382let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in1383 def VMOVZPWILo2PWIZrm : AVX512XSI<0x6E, MRMSrcMem, (outs VR128X:$dst),1384 (ins i16mem:$src),1385 "vmovw\t{$src, $dst|$dst, $src}", []>, EVEX,1386 EVEX_CD8<16, CD8VT1>, T_MAP5,1387 Sched<[WriteVecLoad]>;1388 1389let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in1390 def VMOVZPWILo2PWIZmr : AVX512XSI<0x7E, MRMDestMem, (outs),1391 (ins i32mem:$dst, VR128X:$src),1392 "vmovw\t{$src, $dst|$dst, $src}", []>, EVEX,1393 EVEX_CD8<16, CD8VT1>, T_MAP5,1394 Sched<[WriteVecStore]>;1395 1396let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in1397 def VMOVZPWILo2PWIZrr2 : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),1398 (ins VR128X:$src),1399 "vmovw\t{$src, $dst|$dst, $src}",1400 []>, EVEX, T_MAP5,1401 Sched<[WriteVecMoveFromGpr]>;1402 def : InstAlias<"vmovw.s\t{$src, $dst|$dst, $src}",1403 (VMOVZPWILo2PWIZrr2 VR128X:$dst, VR128X:$src), 0>;1404}1405 1406// MOVRS1407multiclass vmovrs_p<bits<8> opc, string OpStr, X86VectorVTInfo _> {1408 let ExeDomain = _.ExeDomain in {1409 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),1410 (ins _.MemOp:$src), OpStr, "$src", "$src",1411 (_.VT (!cast<Intrinsic>("int_x86_avx10_"#OpStr#_.Size)1412 addr:$src))>, EVEX;1413 }1414}1415 1416multiclass vmovrs_p_vl<bits<8> opc, string OpStr, AVX512VLVectorVTInfo _Vec> {1417 let Predicates = [HasMOVRS, HasAVX10_2, In64BitMode] in {1418 defm Z : vmovrs_p<opc, OpStr, _Vec.info512>, EVEX_V512;1419 defm Z128 : vmovrs_p<opc, OpStr, _Vec.info128>, EVEX_V128;1420 defm Z256 : vmovrs_p<opc, OpStr, _Vec.info256>, EVEX_V256;1421 }1422}1423 1424defm VMOVRSB : vmovrs_p_vl<0x6f, "vmovrsb", avx512vl_i8_info>,1425 T_MAP5, XD, EVEX_CD8<8, CD8VF>, Sched<[WriteVecLoad]>;1426defm VMOVRSW : vmovrs_p_vl<0x6f, "vmovrsw", avx512vl_i16_info>,1427 T_MAP5, XD, REX_W, EVEX_CD8<16, CD8VF>, Sched<[WriteVecLoad]>;1428defm VMOVRSD : vmovrs_p_vl<0x6f, "vmovrsd", avx512vl_i32_info>,1429 T_MAP5, XS, EVEX_CD8<32, CD8VF>, Sched<[WriteVecLoad]>;1430defm VMOVRSQ : vmovrs_p_vl<0x6f, "vmovrsq", avx512vl_i64_info>,1431 T_MAP5, XS, REX_W, EVEX_CD8<64, CD8VF>, Sched<[WriteVecLoad]>;1432 1433// SM4(EVEX)1434multiclass avx10_sm4_base<string OpStr> {1435 // SM4_Base is in X86InstrSSE.td.1436 let Predicates = [HasSM4, HasAVX10_2], AddedComplexity = 1 in {1437 defm Z128 : SM4_Base<OpStr, VR128X, "128", loadv4i32, i128mem>, EVEX_V128;1438 defm Z256 : SM4_Base<OpStr, VR256X, "256", loadv8i32, i256mem>, EVEX_V256;1439 }1440 let Predicates = [HasSM4, HasAVX10_2] in1441 defm Z : SM4_Base<OpStr, VR512, "512", loadv16i32, i512mem>, EVEX_V512;1442}1443 1444defm VSM4KEY4 : avx10_sm4_base<"vsm4key4">, T8, XS, EVEX, VVVV;1445defm VSM4RNDS4 : avx10_sm4_base<"vsm4rnds4">, T8, XD, EVEX, VVVV;1446