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1//==- X86InstrAsmAlias.td - Assembler Instruction Aliases --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the assembler mnemonic/instruction aliases in the X8610// architecture.11//12//===----------------------------------------------------------------------===//13 14// Reversed version with ".s" suffix for GAS compatibility.15def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}",16 (MOV8rr_REV GR8:$dst, GR8:$src), 0>;17def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}",18 (MOV16rr_REV GR16:$dst, GR16:$src), 0>;19def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}",20 (MOV32rr_REV GR32:$dst, GR32:$src), 0>;21def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}",22 (MOV64rr_REV GR64:$dst, GR64:$src), 0>;23def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",24 (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">;25def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",26 (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">;27def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",28 (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">;29def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",30 (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">;31 32// MONITORX/MWAITX Instructions Alias33def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>,34 Requires<[ Not64BitMode ]>;35def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>,36 Requires<[ In64BitMode ]>;37 38// MONITORX/MWAITX Instructions Alias39def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORX32rrr)>,40 Requires<[ Not64BitMode ]>;41def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORX64rrr)>,42 Requires<[ In64BitMode ]>;43 44// CLZERO Instruction Alias45def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;46def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;47 48// INVLPGB Instruction Alias49def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>;50def : InstAlias<"invlpgb\t{%rax, %edx|rax, edx}", (INVLPGB64)>, Requires<[In64BitMode]>;51 52// CMPCCXADD Instructions Alias53multiclass CMPCCXADD_Aliases<string Cond, int CC> {54 let Predicates = [In64BitMode] in {55 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",56 (CMPCCXADDmr32 GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>;57 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",58 (CMPCCXADDmr64 GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>;59 60 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",61 (CMPCCXADDmr32_EVEX GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>;62 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",63 (CMPCCXADDmr64_EVEX GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>;64 }65}66 67// CCMP Instructions Alias68multiclass CCMP_Aliases<string Cond, int CC> {69let Predicates = [In64BitMode] in {70def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",71 (CCMP8rr GR8:$src1, GR8:$src2, cflags:$dcf, CC), 0>;72def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",73 (CCMP16rr GR16:$src1, GR16:$src2, cflags:$dcf, CC), 0>;74def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",75 (CCMP32rr GR32:$src1, GR32:$src2, cflags:$dcf, CC), 0>;76def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",77 (CCMP64rr GR64:$src1, GR64:$src2, cflags:$dcf, CC), 0>;78def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",79 (CCMP8rm GR8:$src1, i8mem:$src2, cflags:$dcf, CC), 0>;80def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",81 (CCMP16rm GR16:$src1, i16mem:$src2, cflags:$dcf, CC), 0>;82def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",83 (CCMP32rm GR32:$src1, i32mem:$src2, cflags:$dcf, CC), 0>;84def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",85 (CCMP64rm GR64:$src1, i64mem:$src2, cflags:$dcf, CC), 0>;86def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",87 (CCMP8mr i8mem:$src1, GR8:$src2, cflags:$dcf, CC), 0>;88def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",89 (CCMP16mr i16mem:$src1, GR16:$src2, cflags:$dcf, CC), 0>;90def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",91 (CCMP32mr i32mem:$src1, GR32:$src2, cflags:$dcf, CC), 0>;92def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",93 (CCMP64mr i64mem:$src1, GR64:$src2, cflags:$dcf, CC), 0>;94def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",95 (CCMP8ri GR8:$src1, i8imm:$src2, cflags:$dcf, CC), 0>;96def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",97 (CCMP16ri GR16:$src1, i16imm:$src2, cflags:$dcf, CC), 0>;98def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",99 (CCMP32ri GR32:$src1, i32imm:$src2, cflags:$dcf, CC), 0>;100def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",101 (CCMP64ri32 GR64:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>;102def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",103 (CCMP16ri8 GR16:$src1, i16i8imm:$src2, cflags:$dcf, CC), 0>;104def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",105 (CCMP32ri8 GR32:$src1, i32i8imm:$src2, cflags:$dcf, CC), 0>;106def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",107 (CCMP64ri8 GR64:$src1, i64i8imm:$src2, cflags:$dcf, CC), 0>;108def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",109 (CCMP8mi i8mem:$src1, i8imm:$src2, cflags:$dcf, CC), 0>;110def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",111 (CCMP16mi i16mem:$src1, i16imm:$src2, cflags:$dcf, CC), 0>;112def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",113 (CCMP32mi i32mem:$src1, i32imm:$src2, cflags:$dcf, CC), 0>;114def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",115 (CCMP64mi32 i64mem:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>;116def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",117 (CCMP16mi8 i16mem:$src1, i16i8imm:$src2, cflags:$dcf, CC), 0>;118def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",119 (CCMP32mi8 i32mem:$src1, i32i8imm:$src2, cflags:$dcf, CC), 0>;120def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",121 (CCMP64mi8 i64mem:$src1, i64i8imm:$src2, cflags:$dcf, CC), 0>;122}123}124defm : CCMP_Aliases<"o" , 0>;125defm : CCMP_Aliases<"no", 1>;126defm : CCMP_Aliases<"b" , 2>;127defm : CCMP_Aliases<"c" , 2>;128defm : CCMP_Aliases<"nae", 2>;129defm : CCMP_Aliases<"nb", 3>;130defm : CCMP_Aliases<"nc", 3>;131defm : CCMP_Aliases<"ae", 3>;132defm : CCMP_Aliases<"e" , 4>;133defm : CCMP_Aliases<"z" , 4>;134defm : CCMP_Aliases<"ne", 5>;135defm : CCMP_Aliases<"nz", 5>;136defm : CCMP_Aliases<"be", 6>;137defm : CCMP_Aliases<"na", 6>;138defm : CCMP_Aliases<"nbe", 7>;139defm : CCMP_Aliases<"a" , 7>;140defm : CCMP_Aliases<"s" , 8>;141defm : CCMP_Aliases<"ns", 9>;142defm : CCMP_Aliases<"t" , 10>;143defm : CCMP_Aliases<"f", 11>;144defm : CCMP_Aliases<"l" , 12>;145defm : CCMP_Aliases<"nge",12>;146defm : CCMP_Aliases<"nl", 13>;147defm : CCMP_Aliases<"ge", 13>;148defm : CCMP_Aliases<"le", 14>;149defm : CCMP_Aliases<"ng", 14>;150defm : CCMP_Aliases<"g" , 15>;151defm : CCMP_Aliases<"nle",15>;152 153// CTEST Instructions Alias154multiclass CTEST_Aliases<string Cond, int CC> {155let Predicates = [In64BitMode] in {156def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",157 (CTEST8rr GR8:$src1, GR8:$src2, cflags:$dcf, CC), 0>;158def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",159 (CTEST16rr GR16:$src1, GR16:$src2, cflags:$dcf, CC), 0>;160def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",161 (CTEST32rr GR32:$src1, GR32:$src2, cflags:$dcf, CC), 0>;162def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",163 (CTEST64rr GR64:$src1, GR64:$src2, cflags:$dcf, CC), 0>;164def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",165 (CTEST8mr i8mem:$src1, GR8:$src2, cflags:$dcf, CC), 0>;166def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",167 (CTEST16mr i16mem:$src1, GR16:$src2, cflags:$dcf, CC), 0>;168def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",169 (CTEST32mr i32mem:$src1, GR32:$src2, cflags:$dcf, CC), 0>;170def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",171 (CTEST64mr i64mem:$src1, GR64:$src2, cflags:$dcf, CC), 0>;172def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src1, $src2|$src2, $src1}",173 (CTEST8mr i8mem:$src1, GR8:$src2, cflags:$dcf, CC), 0>;174def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src1, $src2|$src2, $src1}",175 (CTEST16mr i16mem:$src1, GR16:$src2, cflags:$dcf, CC), 0>;176def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src1, $src2|$src2, $src1}",177 (CTEST32mr i32mem:$src1, GR32:$src2, cflags:$dcf, CC), 0>;178def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src1, $src2|$src2, $src1}",179 (CTEST64mr i64mem:$src1, GR64:$src2, cflags:$dcf, CC), 0>;180def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",181 (CTEST8ri GR8:$src1, i8imm:$src2, cflags:$dcf, CC), 0>;182def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",183 (CTEST16ri GR16:$src1, i16imm:$src2, cflags:$dcf, CC), 0>;184def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",185 (CTEST32ri GR32:$src1, i32imm:$src2, cflags:$dcf, CC), 0>;186def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",187 (CTEST64ri32 GR64:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>;188def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",189 (CTEST8mi i8mem:$src1, i8imm:$src2, cflags:$dcf, CC), 0>;190def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",191 (CTEST16mi i16mem:$src1, i16imm:$src2, cflags:$dcf, CC), 0>;192def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",193 (CTEST32mi i32mem:$src1, i32imm:$src2, cflags:$dcf, CC), 0>;194def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",195 (CTEST64mi32 i64mem:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>;196}197}198defm : CTEST_Aliases<"o" , 0>;199defm : CTEST_Aliases<"no", 1>;200defm : CTEST_Aliases<"b" , 2>;201defm : CTEST_Aliases<"c" , 2>;202defm : CTEST_Aliases<"nae", 2>;203defm : CTEST_Aliases<"nb", 3>;204defm : CTEST_Aliases<"nc", 3>;205defm : CTEST_Aliases<"ae", 3>;206defm : CTEST_Aliases<"e" , 4>;207defm : CTEST_Aliases<"z" , 4>;208defm : CTEST_Aliases<"ne", 5>;209defm : CTEST_Aliases<"nz", 5>;210defm : CTEST_Aliases<"be", 6>;211defm : CTEST_Aliases<"na", 6>;212defm : CTEST_Aliases<"nbe", 7>;213defm : CTEST_Aliases<"a" , 7>;214defm : CTEST_Aliases<"s" , 8>;215defm : CTEST_Aliases<"ns", 9>;216defm : CTEST_Aliases<"t" , 10>;217defm : CTEST_Aliases<"f", 11>;218defm : CTEST_Aliases<"l" , 12>;219defm : CTEST_Aliases<"nge",12>;220defm : CTEST_Aliases<"nl", 13>;221defm : CTEST_Aliases<"ge", 13>;222defm : CTEST_Aliases<"le", 14>;223defm : CTEST_Aliases<"ng", 14>;224defm : CTEST_Aliases<"g" , 15>;225defm : CTEST_Aliases<"nle",15>;226 227//===----------------------------------------------------------------------===//228// Assembler Mnemonic Aliases229//===----------------------------------------------------------------------===//230 231defm : CMPCCXADD_Aliases<"o" , 0>;232defm : CMPCCXADD_Aliases<"no", 1>;233defm : CMPCCXADD_Aliases<"b" , 2>;234defm : CMPCCXADD_Aliases<"ae", 3>;235defm : CMPCCXADD_Aliases<"e" , 4>;236defm : CMPCCXADD_Aliases<"ne", 5>;237defm : CMPCCXADD_Aliases<"be", 6>;238defm : CMPCCXADD_Aliases<"a", 7>;239defm : CMPCCXADD_Aliases<"s" , 8>;240defm : CMPCCXADD_Aliases<"ns", 9>;241defm : CMPCCXADD_Aliases<"p" , 10>;242defm : CMPCCXADD_Aliases<"np", 11>;243defm : CMPCCXADD_Aliases<"l" , 12>;244defm : CMPCCXADD_Aliases<"ge", 13>;245defm : CMPCCXADD_Aliases<"le", 14>;246defm : CMPCCXADD_Aliases<"g", 15>;247 248 249def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;250def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;251def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;252 253def : MnemonicAlias<"cbw", "cbtw", "att">;254def : MnemonicAlias<"cwde", "cwtl", "att">;255def : MnemonicAlias<"cwd", "cwtd", "att">;256def : MnemonicAlias<"cdq", "cltd", "att">;257def : MnemonicAlias<"cdqe", "cltq", "att">;258def : MnemonicAlias<"cqo", "cqto", "att">;259 260// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.261def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;262def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;263 264def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;265def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;266 267def : MnemonicAlias<"loopz", "loope">;268def : MnemonicAlias<"loopnz", "loopne">;269 270def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;271def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;272def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;273def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;274def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;275def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;276def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>;277def : MnemonicAlias<"popfd", "popfl", "att">;278def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In32BitMode]>;279def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In64BitMode]>;280 281// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in282// all modes. However: "push (addr)" and "push $42" should default to283// pushl/pushq depending on the current mode. Similar for "pop %bx"284def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;285def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;286def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;287def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;288def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;289def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;290def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>;291def : MnemonicAlias<"pushfd", "pushfl", "att">;292def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In32BitMode]>;293def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In64BitMode]>;294 295def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;296def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;297def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;298def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;299def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;300def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;301 302def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;303def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;304def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;305def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;306 307def : MnemonicAlias<"repe", "rep">;308def : MnemonicAlias<"repz", "rep">;309def : MnemonicAlias<"repnz", "repne">;310 311def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;312def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;313def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;314 315// Apply 'ret' behavior to 'retn'316def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>;317def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>;318def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>;319def : MnemonicAlias<"retn", "ret", "intel">;320 321def : MnemonicAlias<"sal", "shl", "intel">;322def : MnemonicAlias<"salb", "shlb", "att">;323def : MnemonicAlias<"salw", "shlw", "att">;324def : MnemonicAlias<"sall", "shll", "att">;325def : MnemonicAlias<"salq", "shlq", "att">;326 327def : MnemonicAlias<"smovb", "movsb", "att">;328def : MnemonicAlias<"smovw", "movsw", "att">;329def : MnemonicAlias<"smovl", "movsl", "att">;330def : MnemonicAlias<"smovq", "movsq", "att">;331 332def : MnemonicAlias<"ud2a", "ud2", "att">;333def : MnemonicAlias<"ud2bw", "ud1w", "att">;334def : MnemonicAlias<"ud2bl", "ud1l", "att">;335def : MnemonicAlias<"ud2bq", "ud1q", "att">;336def : MnemonicAlias<"verrw", "verr", "att">;337 338// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release'339def : MnemonicAlias<"acquire", "xacquire", "intel">;340def : MnemonicAlias<"release", "xrelease", "intel">;341 342// System instruction aliases.343def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;344def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;345def : MnemonicAlias<"sysret", "sysretl", "att">;346def : MnemonicAlias<"sysexit", "sysexitl", "att">;347 348def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;349def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;350def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;351def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;352def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;353def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;354def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;355def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;356def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;357def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;358def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;359def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;360def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>;361def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>;362def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>;363def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>;364def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>;365def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>;366def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>;367def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>;368 369 370// Floating point stack aliases.371def : MnemonicAlias<"fcmovz", "fcmove", "att">;372def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;373def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;374def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;375def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;376def : MnemonicAlias<"fcomip", "fcompi">;377def : MnemonicAlias<"fildq", "fildll", "att">;378def : MnemonicAlias<"fistpq", "fistpll", "att">;379def : MnemonicAlias<"fisttpq", "fisttpll", "att">;380def : MnemonicAlias<"fldcww", "fldcw", "att">;381def : MnemonicAlias<"fnstcww", "fnstcw", "att">;382def : MnemonicAlias<"fnstsww", "fnstsw", "att">;383def : MnemonicAlias<"fucomip", "fucompi">;384def : MnemonicAlias<"fwait", "wait">;385 386def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;387def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;388def : MnemonicAlias<"xsaveq", "xsave64", "att">;389def : MnemonicAlias<"xrstorq", "xrstor64", "att">;390def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;391def : MnemonicAlias<"xrstorsq", "xrstors64", "att">;392def : MnemonicAlias<"xsavecq", "xsavec64", "att">;393def : MnemonicAlias<"xsavesq", "xsaves64", "att">;394 395class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,396 string VariantName>397 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),398 !strconcat(Prefix, NewCond, Suffix), VariantName>;399 400/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of401/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for402/// example "setz" -> "sete".403multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,404 string V = ""> {405 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb406 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete407 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe408 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae409 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae410 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle411 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge412 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne413 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp414 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp415 416 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb417 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta418 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl419 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg420}421 422// Aliases for set<CC>423defm : IntegerCondCodeMnemonicAlias<"set", "">;424defm : IntegerCondCodeMnemonicAlias<"setzu", "">;425// Aliases for j<CC>426defm : IntegerCondCodeMnemonicAlias<"j", "">;427// Aliases for cmov<CC>{w,l,q}428defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;429defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;430defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;431// No size suffix for intel-style asm.432defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;433 434// Aliases for cfcmov<CC>{w,l,q}435defm : IntegerCondCodeMnemonicAlias<"cfcmov", "w", "att">;436defm : IntegerCondCodeMnemonicAlias<"cfcmov", "l", "att">;437defm : IntegerCondCodeMnemonicAlias<"cfcmov", "q", "att">;438// No size suffix for intel-style asm.439defm : IntegerCondCodeMnemonicAlias<"cfcmov", "", "intel">;440 441// Aliases for cmp<CC>xadd442defm : IntegerCondCodeMnemonicAlias<"cmp", "xadd", "">;443//===----------------------------------------------------------------------===//444// Assembler Instruction Aliases445//===----------------------------------------------------------------------===//446 447// aad/aam default to base 10 if no operand is specified.448def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>;449def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>;450 451// Disambiguate the mem/imm form of bt-without-a-suffix as btl.452// Likewise for btc/btr/bts.453def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}",454 (BT32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;455def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}",456 (BTC32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;457def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}",458 (BTR32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;459def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}",460 (BTS32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;461 462// clr aliases.463def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;464def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;465def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;466def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;467 468// lods aliases. Accept the destination being omitted because it's implicit469// in the mnemonic, or the mnemonic suffix being omitted because it's implicit470// in the destination.471def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>;472def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>;473def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>;474def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;475def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;476def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;477def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;478def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;479def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">;480def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">;481def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">;482def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>;483 484 485// stos aliases. Accept the source being omitted because it's implicit in486// the mnemonic, or the mnemonic suffix being omitted because it's implicit487// in the source.488def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>;489def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>;490def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>;491def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;492def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;493def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;494def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;495def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;496def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">;497def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">;498def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">;499def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>;500 501 502// scas aliases. Accept the destination being omitted because it's implicit503// in the mnemonic, or the mnemonic suffix being omitted because it's implicit504// in the destination.505def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>;506def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>;507def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>;508def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;509def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;510def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;511def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;512def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;513def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">;514def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">;515def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">;516def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>;517 518// cmps aliases. Mnemonic suffix being omitted because it's implicit519// in the destination.520def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">;521def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">;522def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">;523def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>;524 525// movs aliases. Mnemonic suffix being omitted because it's implicit526// in the destination.527def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">;528def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">;529def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">;530def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>;531 532// div and idiv aliases for explicit A register.533def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;534def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;535def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;536def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;537def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;538def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;539def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;540def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;541def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;542def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;543def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;544def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;545def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;546def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;547def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;548def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;549 550 551 552// Various unary fpstack operations default to operating on ST1.553// For example, "fxch" -> "fxch %st(1)"554def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;555def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;556def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;557def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;558def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;559def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;560def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;561def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;562def : InstAlias<"fxch", (XCH_F ST1), 0>;563def : InstAlias<"fcom", (COM_FST0r ST1), 0>;564def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;565def : InstAlias<"fcomi", (COM_FIr ST1), 0>;566def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;567def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;568def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;569def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;570def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;571 572// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.573// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate574// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with575// gas.576multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {577 def : InstAlias<!strconcat(Mnemonic, "\t$op"),578 (Inst RSTi:$op), EmitAlias>;579 def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"),580 (Inst ST0), EmitAlias>;581}582 583defm : FpUnaryAlias<"fadd", ADD_FST0r, 0>;584defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;585defm : FpUnaryAlias<"fsub", SUB_FST0r, 0>;586defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0, 0>;587defm : FpUnaryAlias<"fsubr", SUBR_FST0r, 0>;588defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>;589defm : FpUnaryAlias<"fmul", MUL_FST0r, 0>;590defm : FpUnaryAlias<"fmulp", MUL_FPrST0, 0>;591defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>;592defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>;593defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>;594defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>;595defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;596defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;597defm : FpUnaryAlias<"fcompi", COM_FIPr, 0>;598defm : FpUnaryAlias<"fucompi", UCOM_FIPr, 0>;599 600 601// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they602// commute. We also allow fdiv[r]p/fsubrp even though they don't commute,603// solely because gas supports it.604def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>;605def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>;606def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>;607def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>;608def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>;609def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>;610 611def : InstAlias<"fnstsw" , (FNSTSW16r), 0>;612 613// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but614// this is compatible with what GAS does.615def : InstAlias<"lcall\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>;616def : InstAlias<"ljmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>;617def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>;618def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>;619def : InstAlias<"lcall\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;620def : InstAlias<"ljmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;621def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>;622def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>;623 624def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>;625def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>;626def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>;627 628 629// "imul <imm>, B" is an alias for "imul <imm>, B, B".630def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;631def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;632def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;633def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;634def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;635def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;636 637// ins aliases. Accept the mnemonic suffix being omitted because it's implicit638// in the destination.639def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">;640def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">;641def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">;642 643// outs aliases. Accept the mnemonic suffix being omitted because it's implicit644// in the source.645def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">;646def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">;647def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">;648 649// inb %dx -> inb %al, %dx650def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;651def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;652def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;653def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>;654def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>;655def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>;656 657 658// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp659def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;660def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;661def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>;662def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>;663def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;664def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;665def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;666def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;667 668// Match 'movq <largeimm>, <reg>' as an alias for movabsq.669def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;670 671// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas,672// which supports this due to an old AMD documentation bug when 64-bit mode was673// created.674def : InstAlias<"movd\t{$src, $dst|$dst, $src}",675 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;676def : InstAlias<"movd\t{$src, $dst|$dst, $src}",677 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;678 679// movsx aliases680def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">;681def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">;682def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">;683def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">;684def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">;685def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">;686def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">;687 688// movzx aliases689def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">;690def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">;691def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">;692def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">;693def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">;694def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">;695// Note: No GR32->GR64 movzx form.696 697// outb %dx -> outb %al, %dx698def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;699def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;700def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;701def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>;702def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>;703def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>;704 705// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same706// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity707// errors, since its encoding is the most compact.708def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;709 710// shld/shrd op,op -> shld op, op, CL711def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;712def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;713def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;714def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;715def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;716def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;717 718def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;719def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;720def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;721def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;722def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;723def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;724 725// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.726def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}",727 (TEST8mr i8mem :$mem, GR8 :$val), 0>;728def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}",729 (TEST16mr i16mem:$mem, GR16:$val), 0>;730def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}",731 (TEST32mr i32mem:$mem, GR32:$val), 0>;732def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}",733 (TEST64mr i64mem:$mem, GR64:$val), 0>;734 735// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.736def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",737 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;738def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",739 (XCHG16rm GR16:$val, i16mem:$mem), 0>;740def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",741 (XCHG32rm GR32:$val, i32mem:$mem), 0>;742def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",743 (XCHG64rm GR64:$val, i64mem:$mem), 0>;744 745// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.746def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;747def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>;748def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;749 750// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we751// would get by default because it's defined as NOP. But xchg %eax, %eax implies752// implicit zeroing of the upper 32 bits. So alias to the longer encoding.753def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}",754 (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>;755 756// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this757// we emit an unneeded REX.w prefix.758def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>;759 760// These aliases exist to get the parser to prioritize matching 8-bit761// immediate encodings over matching the implicit ax/eax/rax encodings. By762// explicitly mentioning the A register here, these entries will be ordered763// first due to the more explicit immediate type.764def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>;765def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>;766def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>;767def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>;768def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>;769def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>;770def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>;771def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>;772 773def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>;774def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>;775def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>;776def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>;777def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>;778def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>;779def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>;780def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>;781 782def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>;783def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>;784def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>;785def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>;786def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>;787def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>;788def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>;789def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>;790 791// MMX instr alia792def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",793 (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;794 795// CMOV SETCC SETZUCC Aliases796multiclass CMOV_SETCC_Aliases<string Cond, int CC> {797 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",798 (CMOV16rr GR16:$dst, GR16:$src, CC), 0>;799 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",800 (CMOV16rm GR16:$dst, i16mem:$src, CC), 0>;801 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",802 (CMOV32rr GR32:$dst, GR32:$src, CC), 0>;803 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",804 (CMOV32rm GR32:$dst, i32mem:$src, CC), 0>;805 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",806 (CMOV64rr GR64:$dst, GR64:$src, CC), 0>;807 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",808 (CMOV64rm GR64:$dst, i64mem:$src, CC), 0>;809let Predicates = [In64BitMode] in {810 def : InstAlias<"cmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",811 (CMOV16rr_ND GR16:$dst, GR16:$src1, GR16:$src2, CC), 0>;812 def : InstAlias<"cmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",813 (CMOV16rm_ND GR16:$dst, GR16:$src1, i16mem:$src2, CC), 0>;814 def : InstAlias<"cmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",815 (CMOV32rr_ND GR32:$dst, GR32:$src1, GR32:$src2, CC), 0>;816 def : InstAlias<"cmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",817 (CMOV32rm_ND GR32:$dst, GR32:$src1, i32mem:$src2, CC), 0>;818 def : InstAlias<"cmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",819 (CMOV64rr_ND GR64:$dst, GR64:$src1, GR64:$src2, CC), 0>;820 def : InstAlias<"cmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",821 (CMOV64rm_ND GR64:$dst, GR64:$src1, i64mem:$src2, CC), 0>;822 823 def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCr GR8:$dst, CC), 0>;824 def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCm i8mem:$dst, CC), 0>;825 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr_EVEX GR8:$dst, CC), 0>;826 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm_EVEX i8mem:$dst, CC), 0>;827}828 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;829 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;830}831 832defm : CMOV_SETCC_Aliases<"o" , 0>;833defm : CMOV_SETCC_Aliases<"no", 1>;834defm : CMOV_SETCC_Aliases<"b" , 2>;835defm : CMOV_SETCC_Aliases<"ae", 3>;836defm : CMOV_SETCC_Aliases<"e" , 4>;837defm : CMOV_SETCC_Aliases<"ne", 5>;838defm : CMOV_SETCC_Aliases<"be", 6>;839defm : CMOV_SETCC_Aliases<"a" , 7>;840defm : CMOV_SETCC_Aliases<"s" , 8>;841defm : CMOV_SETCC_Aliases<"ns", 9>;842defm : CMOV_SETCC_Aliases<"p" , 10>;843defm : CMOV_SETCC_Aliases<"np", 11>;844defm : CMOV_SETCC_Aliases<"l" , 12>;845defm : CMOV_SETCC_Aliases<"ge", 13>;846defm : CMOV_SETCC_Aliases<"le", 14>;847defm : CMOV_SETCC_Aliases<"g" , 15>;848 849multiclass CFCMOV_Aliases<string Cond, int CC> {850let Predicates = [In64BitMode] in {851 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",852 (CFCMOV16rr GR16:$dst, GR16:$src, CC), 0>;853 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",854 (CFCMOV32rr GR32:$dst, GR32:$src, CC), 0>;855 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",856 (CFCMOV64rr GR64:$dst, GR64:$src, CC), 0>;857 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",858 (CFCMOV16rm GR16:$dst, i16mem:$src, CC), 0>;859 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",860 (CFCMOV32rm GR32:$dst, i32mem:$src, CC), 0>;861 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",862 (CFCMOV64rm GR64:$dst, i64mem:$src, CC), 0>;863 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",864 (CFCMOV16mr i16mem:$dst, GR16:$src, CC), 0>;865 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",866 (CFCMOV32mr i32mem:$dst, GR32:$src, CC), 0>;867 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",868 (CFCMOV64mr i64mem:$dst, GR64:$src, CC), 0>;869 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",870 (CFCMOV16rr_ND GR16:$dst, GR16:$src1, GR16:$src2, CC), 0>;871 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",872 (CFCMOV32rr_ND GR32:$dst, GR32:$src1, GR32:$src2, CC), 0>;873 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",874 (CFCMOV64rr_ND GR64:$dst, GR64:$src1, GR64:$src2, CC), 0>;875 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",876 (CFCMOV16rm_ND GR16:$dst, GR16:$src1, i16mem:$src2, CC), 0>;877 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",878 (CFCMOV32rm_ND GR32:$dst, GR32:$src1, i32mem:$src2, CC), 0>;879 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",880 (CFCMOV64rm_ND GR64:$dst, GR64:$src1, i64mem:$src2, CC), 0>;881}882}883defm : CFCMOV_Aliases<"o" , 0>;884defm : CFCMOV_Aliases<"no", 1>;885defm : CFCMOV_Aliases<"b" , 2>;886defm : CFCMOV_Aliases<"ae", 3>;887defm : CFCMOV_Aliases<"e" , 4>;888defm : CFCMOV_Aliases<"ne", 5>;889defm : CFCMOV_Aliases<"be", 6>;890defm : CFCMOV_Aliases<"a" , 7>;891defm : CFCMOV_Aliases<"s" , 8>;892defm : CFCMOV_Aliases<"ns", 9>;893defm : CFCMOV_Aliases<"p" , 10>;894defm : CFCMOV_Aliases<"np", 11>;895defm : CFCMOV_Aliases<"l" , 12>;896defm : CFCMOV_Aliases<"ge", 13>;897defm : CFCMOV_Aliases<"le", 14>;898defm : CFCMOV_Aliases<"g" , 15>;899 900// Condition dump instructions Alias901def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>;902def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>;903def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>;904def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>;905def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>;906def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>;907def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>;908def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>;909def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>;910def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>;911def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>;912def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>;913def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>;914def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>;915def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>;916def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>;917 918// SVM instructions Alias919def : InstAlias<"skinit\t{%eax|eax}", (SKINIT), 0>;920def : InstAlias<"vmrun\t{%eax|eax}", (VMRUN32), 0>, Requires<[Not64BitMode]>;921def : InstAlias<"vmrun\t{%rax|rax}", (VMRUN64), 0>, Requires<[In64BitMode]>;922def : InstAlias<"vmload\t{%eax|eax}", (VMLOAD32), 0>, Requires<[Not64BitMode]>;923def : InstAlias<"vmload\t{%rax|rax}", (VMLOAD64), 0>, Requires<[In64BitMode]>;924def : InstAlias<"vmsave\t{%eax|eax}", (VMSAVE32), 0>, Requires<[Not64BitMode]>;925def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;926def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;927def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;928 929// Aliases with explicit %xmm0930def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",931 (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;932def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",933 (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;934