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1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the various pseudo instructions used by the compiler,10// as well as Pat patterns used during instruction selection.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Pattern Matching Support16 17def GetLo32XForm : SDNodeXForm<imm, [{18 // Transformation function: get the low 32 bits.19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N));20}]>;21 22 23//===----------------------------------------------------------------------===//24// Random Pseudo Instructions.25 26// PIC base construction. This expands to code that looks like this:27// call $next_inst28// popl %destreg"29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP],30 SchedRW = [WriteJump] in31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),32 "", []>;33 34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into35// a stack adjustment and the codegen must know that they may modify the stack36// pointer before prolog-epilog rewriting occurs.37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become38// sub / add which can clobber EFLAGS.39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),42 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>;43def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),44 "#ADJCALLSTACKUP",45 [(X86callseq_end timm:$amt1, timm:$amt2)]>,46 Requires<[NotLP64]>;47}48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;50 51 52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into53// a stack adjustment and the codegen must know that they may modify the stack54// pointer before prolog-epilog rewriting occurs.55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become56// sub / add which can clobber EFLAGS.57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),60 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>;61def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),62 "#ADJCALLSTACKUP",63 [(X86callseq_end timm:$amt1, timm:$amt2)]>,64 Requires<[IsLP64]>;65}66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;68 69let SchedRW = [WriteSystem] in {70 71// x86-64 va_start lowering magic.72let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in {73def VASTART_SAVE_XMM_REGS : I<0, Pseudo,74 (outs),75 (ins GR8:$al, i8mem:$regsavefi, variable_ops),76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi",77 [(X86vastart_save_xmm_regs GR8:$al, addr:$regsavefi)]>;78}79 80let usesCustomInserter = 1, Defs = [EFLAGS] in {81// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the82// va_list, and place the address of the next argument into a register.83let Defs = [EFLAGS] in {84def VAARG_64 : I<0, Pseudo,85 (outs GR64:$dst),86 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),87 "#VAARG_64 $dst, $ap, $size, $mode, $align",88 [(set GR64:$dst,89 (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align))]>,90 Requires<[In64BitMode, IsLP64]>;91def VAARG_X32 : I<0, Pseudo,92 (outs GR32:$dst),93 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),94 "#VAARG_X32 $dst, $ap, $size, $mode, $align",95 [(set GR32:$dst,96 (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align))]>,97 Requires<[In64BitMode, NotLP64]>;98}99 100// When using segmented stacks these are lowered into instructions which first101// check if the current stacklet has enough free memory. If it does, memory is102// allocated by bumping the stack pointer. Otherwise memory is allocated from103// the heap.104 105let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in106def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),107 "# variable sized alloca for segmented stacks",108 [(set GR32:$dst,109 (X86SegAlloca GR32:$size))]>,110 Requires<[NotLP64]>;111 112let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in113def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),114 "# variable sized alloca for segmented stacks",115 [(set GR64:$dst,116 (X86SegAlloca GR64:$size))]>,117 Requires<[In64BitMode]>;118 119// To protect against stack clash, dynamic allocation should perform a memory120// probe at each page.121 122let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in123def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),124 "# variable sized alloca with probing",125 [(set GR32:$dst,126 (X86ProbedAlloca GR32:$size))]>,127 Requires<[NotLP64]>;128 129let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in130def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),131 "# variable sized alloca with probing",132 [(set GR64:$dst,133 (X86ProbedAlloca GR64:$size))]>,134 Requires<[In64BitMode]>;135}136 137let hasNoSchedulingInfo = 1 in138def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize),139 "# fixed size alloca with probing",140 []>;141 142// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows143// targets. These calls are needed to probe the stack when allocating more than144// 4k bytes in one go. Touching the stack at 4K increments is necessary to145// ensure that the guard pages used by the OS virtual memory manager are146// allocated in correct sequence.147// The main point of having separate instruction are extra unmodelled effects148// (compared to ordinary calls) like stack pointer change.149 150let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in151def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size),152 "# dynamic stack allocation",153 [(X86DynAlloca GR32:$size)]>,154 Requires<[NotLP64]>;155 156let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in157def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),158 "# dynamic stack allocation",159 [(X86DynAlloca GR64:$size)]>,160 Requires<[In64BitMode]>;161} // SchedRW162 163// These instructions XOR the frame pointer into a GPR. They are used in some164// stack protection schemes. These are post-RA pseudos because we only know the165// frame register after register allocation.166let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in {167 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),168 "xorl\t$$FP, $src", []>,169 Requires<[NotLP64]>, Sched<[WriteALU]>;170 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),171 "xorq\t$$FP $src", []>,172 Requires<[In64BitMode]>, Sched<[WriteALU]>;173}174 175//===----------------------------------------------------------------------===//176// EH Pseudo Instructions177//178let SchedRW = [WriteSystem] in {179let isTerminator = 1, isReturn = 1, isBarrier = 1,180 hasCtrlDep = 1, isCodeGenOnly = 1 in {181def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),182 "ret\t#eh_return, addr: $addr",183 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>;184 185}186 187let isTerminator = 1, isReturn = 1, isBarrier = 1,188 hasCtrlDep = 1, isCodeGenOnly = 1 in {189def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),190 "ret\t#eh_return, addr: $addr",191 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>;192 193}194 195let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,196 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in {197 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET",198 [(cleanupret bb)]>;199 200 // CATCHRET needs a custom inserter for SEH.201 let usesCustomInserter = 1 in202 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),203 "# CATCHRET",204 [(catchret bb:$dst, bb:$from)]>;205}206 207let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,208 usesCustomInserter = 1 in {209 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),210 "#EH_SJLJ_SETJMP32",211 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,212 Requires<[Not64BitMode]>;213 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),214 "#EH_SJLJ_SETJMP64",215 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,216 Requires<[In64BitMode]>;217 let isTerminator = 1 in {218 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),219 "#EH_SJLJ_LONGJMP32",220 [(X86eh_sjlj_longjmp addr:$buf)]>,221 Requires<[Not64BitMode]>;222 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),223 "#EH_SJLJ_LONGJMP64",224 [(X86eh_sjlj_longjmp addr:$buf)]>,225 Requires<[In64BitMode]>;226 }227}228 229let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {230 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),231 "#EH_SjLj_Setup\t$dst", []>;232}233} // SchedRW234 235//===----------------------------------------------------------------------===//236// Pseudo instructions used by unwind info.237//238 239// Prolog instructions should not be duplicated, since this can cause issues240// because 1) if only some of the instructions are duplicated, then we will241// observe prolog instructions after the end-prolog instruction and 2) Windows242// expects there to only be a single prolog (e.g., when checking if unwinding243// is happening in the middle of a prolog).244let isPseudo = 1, isMeta = 1, isNotDuplicable = 1, SchedRW = [WriteSystem] in {245 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),246 "#SEH_PushReg $reg", []>;247 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),248 "#SEH_SaveReg $reg, $dst", []>;249 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),250 "#SEH_SaveXMM $reg, $dst", []>;251 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),252 "#SEH_StackAlloc $size", []>;253 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align),254 "#SEH_StackAlign $align", []>;255 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),256 "#SEH_SetFrame $reg, $offset", []>;257 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),258 "#SEH_PushFrame $mode", []>;259 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),260 "#SEH_EndPrologue", []>;261 def SEH_UnwindVersion : I<0, Pseudo, (outs), (ins i1imm:$version),262 "#SEH_UnwindVersion $version", []>;263}264 265// Epilog instructions:266let isPseudo = 1, isMeta = 1, SchedRW = [WriteSystem] in {267 def SEH_BeginEpilogue : I<0, Pseudo, (outs), (ins),268 "#SEH_BeginEpilogue", []>;269 def SEH_EndEpilogue : I<0, Pseudo, (outs), (ins),270 "#SEH_EndEpilogue", []>;271 def SEH_UnwindV2Start : I<0, Pseudo, (outs), (ins),272 "#SEH_UnwindV2Start", []>;273}274 275//===----------------------------------------------------------------------===//276// Pseudo instructions used by KCFI.277//===----------------------------------------------------------------------===//278let279 Defs = [R10, R11, EFLAGS] in {280def KCFI_CHECK : PseudoI<281 (outs), (ins GR64:$ptr, i32imm:$type), []>, Sched<[]>;282}283 284//===----------------------------------------------------------------------===//285// Pseudo instructions used by address sanitizer.286//===----------------------------------------------------------------------===//287let288 Defs = [R10, R11, EFLAGS] in {289def ASAN_CHECK_MEMACCESS : PseudoI<290 (outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo),291 [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>,292 Sched<[]>;293}294 295//===----------------------------------------------------------------------===//296// Pseudo instructions used by segmented stacks.297//298 299// This is lowered into a RET instruction by MCInstLower. We need300// this so that we don't have to have a MachineBasicBlock which ends301// with a RET and also has successors.302let isPseudo = 1, SchedRW = [WriteJumpLd] in {303def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>;304 305// This instruction is lowered to a RET followed by a MOV. The two306// instructions are not generated on a higher level since then the307// verifier sees a MachineBasicBlock ending with a non-terminator.308def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>;309}310 311//===----------------------------------------------------------------------===//312// Alias Instructions313//===----------------------------------------------------------------------===//314 315// Alias instruction mapping movr0 to xor.316// FIXME: remove when we can teach regalloc that xor reg, reg is ok.317let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,318 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in319def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",320 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>;321 322// Other widths can also make use of the 32-bit xor, which may have a smaller323// encoding and avoid partial register updates.324let AddedComplexity = 10 in {325def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;326def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;327def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;328}329 330let Predicates = [OptForSize, Not64BitMode],331 AddedComplexity = 10 in {332 let SchedRW = [WriteALU] in {333 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC,334 // which only require 3 bytes compared to MOV32ri which requires 5.335 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {336 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",337 [(set GR32:$dst, 1)]>;338 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",339 [(set GR32:$dst, -1)]>;340 }341 } // SchedRW342 343 // MOV16ri is 4 bytes, so the instructions above are smaller.344 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;345 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;346}347 348let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5,349 SchedRW = [WriteALU] in {350// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1.351def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "",352 [(set GR32:$dst, i32immSExt8:$src)]>,353 Requires<[OptForMinSize, NotWin64WithoutFP]>;354def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",355 [(set GR64:$dst, i64immSExt8:$src)]>,356 Requires<[OptForMinSize, NotWin64WithoutFP]>;357}358 359// Materialize i64 constant where top 32-bits are zero. This could theoretically360// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however361// that would make it more difficult to rematerialize.362let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,363 isPseudo = 1, SchedRW = [WriteMove] in364def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "",365 [(set GR64:$dst, i64immZExt32:$src)]>;366 367// This 64-bit pseudo-move can also be used for labels in the x86-64 small code368// model.369def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>;370def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>;371 372// Use sbb to materialize carry bit.373let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC],374 hasSideEffects = 0 in {375// FIXME: These are pseudo ops that should be replaced with Pat<> patterns.376// However, Pat<> can't replicate the destination reg into the inputs of the377// result.378def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>;379def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>;380} // isCodeGenOnly381 382//===----------------------------------------------------------------------===//383// String Pseudo Instructions384//385let SchedRW = [WriteMicrocoded] in {386let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {387def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins),388 "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}",389 [(X86rep_movs i8)]>, REP, AdSize32,390 Requires<[NotLP64]>;391def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins),392 "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}",393 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16,394 Requires<[NotLP64]>;395def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins),396 "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}",397 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32,398 Requires<[NotLP64]>;399def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins),400 "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}",401 [(X86rep_movs i64)]>, REP, AdSize32,402 Requires<[NotLP64, In64BitMode]>;403}404 405let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {406def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins),407 "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}",408 [(X86rep_movs i8)]>, REP, AdSize64,409 Requires<[IsLP64]>;410def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins),411 "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}",412 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16,413 Requires<[IsLP64]>;414def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins),415 "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}",416 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32,417 Requires<[IsLP64]>;418def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins),419 "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}",420 [(X86rep_movs i64)]>, REP, AdSize64,421 Requires<[IsLP64]>;422}423 424// FIXME: Should use "(X86rep_stos AL)" as the pattern.425let Defs = [ECX,EDI], isCodeGenOnly = 1 in {426 let Uses = [AL,ECX,EDI] in427 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins),428 "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}",429 [(X86rep_stos i8)]>, REP, AdSize32,430 Requires<[NotLP64]>;431 let Uses = [AX,ECX,EDI] in432 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins),433 "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}",434 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16,435 Requires<[NotLP64]>;436 let Uses = [EAX,ECX,EDI] in437 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins),438 "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}",439 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32,440 Requires<[NotLP64]>;441 let Uses = [RAX,RCX,RDI] in442 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins),443 "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}",444 [(X86rep_stos i64)]>, REP, AdSize32,445 Requires<[NotLP64, In64BitMode]>;446}447 448let Defs = [RCX,RDI], isCodeGenOnly = 1 in {449 let Uses = [AL,RCX,RDI] in450 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins),451 "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}",452 [(X86rep_stos i8)]>, REP, AdSize64,453 Requires<[IsLP64]>;454 let Uses = [AX,RCX,RDI] in455 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins),456 "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}",457 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16,458 Requires<[IsLP64]>;459 let Uses = [RAX,RCX,RDI] in460 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins),461 "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}",462 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32,463 Requires<[IsLP64]>;464 465 let Uses = [RAX,RCX,RDI] in466 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins),467 "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}",468 [(X86rep_stos i64)]>, REP, AdSize64,469 Requires<[IsLP64]>;470}471} // SchedRW472 473//===----------------------------------------------------------------------===//474// Thread Local Storage Instructions475//476let SchedRW = [WriteSystem] in {477 478// ELF TLS Support479// All calls clobber the non-callee saved registers. ESP is marked as480// a use to prevent stack-pointer assignments that appear immediately481// before calls from potentially appearing dead.482let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,483 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,484 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,485 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,486 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],487 Uses = [ESP, SSP] in {488def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),489 "# TLS_addr32",490 [(X86tlsaddr tls32addr:$sym)]>,491 Requires<[Not64BitMode]>;492def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),493 "# TLS_base_addr32",494 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,495 Requires<[Not64BitMode]>;496}497 498// All calls clobber the non-callee saved registers. RSP is marked as499// a use to prevent stack-pointer assignments that appear immediately500// before calls from potentially appearing dead.501let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,502 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,503 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,504 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,505 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,506 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],507 Uses = [RSP, SSP] in {508def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),509 "# TLS_addr64",510 [(X86tlsaddr tls64addr:$sym)]>,511 Requires<[In64BitMode, IsLP64]>;512def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),513 "# TLS_base_addr64",514 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,515 Requires<[In64BitMode, IsLP64]>;516def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym),517 "# TLS_addrX32",518 [(X86tlsaddr tls32addr:$sym)]>,519 Requires<[In64BitMode, NotLP64]>;520def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym),521 "# TLS_base_addrX32",522 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,523 Requires<[In64BitMode, NotLP64]>;524}525 526// TLSDESC only clobbers EAX and EFLAGS. ESP is marked as a use to prevent527// stack-pointer assignments that appear immediately before calls from528// potentially appearing dead.529let Defs = [EAX, EFLAGS], Uses = [RSP, SSP] in {530 def TLS_desc32 : I<0, Pseudo, (outs), (ins i32mem:$sym),531 "# TLS_desc32", [(X86tlsdesc tls32addr:$sym)]>;532 def TLS_desc64 : I<0, Pseudo, (outs), (ins i64mem:$sym),533 "# TLS_desc64", [(X86tlsdesc tls64addr:$sym)]>;534}535 536// Darwin TLS Support537// For i386, the address of the thunk is passed on the stack, on return the538// address of the variable is in %eax. %ecx is trashed during the function539// call. All other registers are preserved.540let Defs = [EAX, ECX, EFLAGS, DF],541 Uses = [ESP, SSP],542 usesCustomInserter = 1 in543def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),544 "# TLSCall_32",545 [(X86TLSCall addr:$sym)]>,546 Requires<[Not64BitMode]>;547 548// For x86_64, the address of the thunk is passed in %rdi, but the549// pseudo directly use the symbol, so do not add an implicit use of550// %rdi. The lowering will do the right thing with RDI.551// On return the address of the variable is in %rax. All other552// registers are preserved.553let Defs = [RAX, EFLAGS, DF],554 Uses = [RSP, SSP],555 usesCustomInserter = 1 in556def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),557 "# TLSCall_64",558 [(X86TLSCall addr:$sym)]>,559 Requires<[In64BitMode]>;560} // SchedRW561 562//===----------------------------------------------------------------------===//563// Conditional Move Pseudo Instructions564 565// CMOV* - Used to implement the SELECT DAG operation. Expanded after566// instruction selection into a branch sequence.567multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {568 def CMOV#NAME : I<0, Pseudo,569 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),570 "#CMOV_"#NAME#" PSEUDO!",571 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond,572 EFLAGS)))]>;573}574 575let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {576 // X86 doesn't have 8-bit conditional moves. Use a customInserter to577 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,578 // however that requires promoting the operands, and can induce additional579 // i8 register pressure.580 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;581 582 let Predicates = [NoCMOV] in {583 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;584 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;585 } // Predicates = [NoCMOV]586 587 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no588 // SSE1/SSE2.589 let Predicates = [FPStackf32] in590 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;591 592 let Predicates = [FPStackf64] in593 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;594 595 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;596 597 let Predicates = [HasMMX] in598 defm _VR64 : CMOVrr_PSEUDO<VR64, x86mmx>;599 600 let Predicates = [HasSSE1,NoAVX512] in601 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;602 let Predicates = [HasSSE2,NoAVX512] in {603 defm _FR16 : CMOVrr_PSEUDO<FR16, f16>;604 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;605 }606 let Predicates = [HasAVX512] in {607 defm _FR16X : CMOVrr_PSEUDO<FR16X, f16>;608 defm _FR32X : CMOVrr_PSEUDO<FR32X, f32>;609 defm _FR64X : CMOVrr_PSEUDO<FR64X, f64>;610 }611 let Predicates = [NoVLX] in {612 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>;613 defm _VR256 : CMOVrr_PSEUDO<VR256, v4i64>;614 }615 let Predicates = [HasVLX] in {616 defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>;617 defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>;618 }619 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>;620 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>;621 defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>;622 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>;623 defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>;624 defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>;625 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>;626 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>;627} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS]628 629def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),630 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;631 632let Predicates = [NoVLX] in {633 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),634 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;635 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),636 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;637 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),638 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;639 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),640 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;641 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),642 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;643 644 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),645 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;646 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),647 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;648 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),649 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;650 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),651 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;652 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),653 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;654}655let Predicates = [HasVLX] in {656 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),657 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;658 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),659 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;660 def : Pat<(v8f16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),661 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;662 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),663 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;664 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),665 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;666 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),667 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;668 669 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),670 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;671 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),672 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;673 def : Pat<(v16f16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),674 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;675 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),676 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;677 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),678 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;679 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),680 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;681}682 683def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),684 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;685def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),686 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;687def : Pat<(v32f16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),688 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;689def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),690 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;691def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),692 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;693def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),694 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;695 696//===----------------------------------------------------------------------===//697// Normal-Instructions-With-Lock-Prefix Pseudo Instructions698//===----------------------------------------------------------------------===//699 700// FIXME: Use normal instructions and add lock prefix dynamically.701 702// Memory barriers703 704let isCodeGenOnly = 1, Defs = [EFLAGS] in705def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero),706 "or{l}\t{$zero, $dst|$dst, $zero}", []>,707 Requires<[Not64BitMode]>, OpSize32, LOCK,708 Sched<[WriteALURMW]>;709 710// RegOpc corresponds to the mr version of the instruction711// ImmOpc corresponds to the mi version of the instruction712// ImmOpc8 corresponds to the mi8 version of the instruction713// ImmMod corresponds to the instruction format of the mi and mi8 versions714multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,715 Format ImmMod, SDNode Op, string mnemonic> {716let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,717 SchedRW = [WriteALURMW] in {718 719def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},720 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },721 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),722 !strconcat(mnemonic, "{b}\t",723 "{$src2, $dst|$dst, $src2}"),724 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;725 726def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},727 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },728 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),729 !strconcat(mnemonic, "{w}\t",730 "{$src2, $dst|$dst, $src2}"),731 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,732 OpSize16, LOCK;733 734def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},735 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },736 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),737 !strconcat(mnemonic, "{l}\t",738 "{$src2, $dst|$dst, $src2}"),739 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,740 OpSize32, LOCK;741 742def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},743 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },744 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),745 !strconcat(mnemonic, "{q}\t",746 "{$src2, $dst|$dst, $src2}"),747 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK;748 749// NOTE: These are order specific, we want the mi8 forms to be listed750// first so that they are slightly preferred to the mi forms.751def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},752 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },753 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),754 !strconcat(mnemonic, "{w}\t",755 "{$src2, $dst|$dst, $src2}"),756 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>,757 OpSize16, LOCK;758 759def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},760 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },761 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),762 !strconcat(mnemonic, "{l}\t",763 "{$src2, $dst|$dst, $src2}"),764 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>,765 OpSize32, LOCK;766 767def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},768 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },769 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),770 !strconcat(mnemonic, "{q}\t",771 "{$src2, $dst|$dst, $src2}"),772 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>,773 LOCK;774 775def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},776 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },777 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),778 !strconcat(mnemonic, "{b}\t",779 "{$src2, $dst|$dst, $src2}"),780 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK;781 782def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},783 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },784 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),785 !strconcat(mnemonic, "{w}\t",786 "{$src2, $dst|$dst, $src2}"),787 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>,788 OpSize16, LOCK;789 790def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},791 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },792 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),793 !strconcat(mnemonic, "{l}\t",794 "{$src2, $dst|$dst, $src2}"),795 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>,796 OpSize32, LOCK;797 798def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},799 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },800 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),801 !strconcat(mnemonic, "{q}\t",802 "{$src2, $dst|$dst, $src2}"),803 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>,804 LOCK;805}806 807}808 809defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">;810defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">;811defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">;812defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">;813defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">;814 815let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,816 SchedRW = [WriteALURMW] in {817 let Predicates = [UseIncDec] in {818 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),819 "inc{b}\t$dst",820 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>,821 LOCK;822 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),823 "inc{w}\t$dst",824 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>,825 OpSize16, LOCK;826 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),827 "inc{l}\t$dst",828 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>,829 OpSize32, LOCK;830 831 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),832 "dec{b}\t$dst",833 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>,834 LOCK;835 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),836 "dec{w}\t$dst",837 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>,838 OpSize16, LOCK;839 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),840 "dec{l}\t$dst",841 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>,842 OpSize32, LOCK;843 }844 845 let Predicates = [UseIncDec, In64BitMode] in {846 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),847 "inc{q}\t$dst",848 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>,849 LOCK;850 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),851 "dec{q}\t$dst",852 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>,853 LOCK;854 }855}856 857let Predicates = [UseIncDec] in {858 // Additional patterns for -1 constant.859 def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>;860 def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>;861 def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>;862 def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>;863 def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>;864 def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>;865}866 867let Predicates = [UseIncDec, In64BitMode] in {868 // Additional patterns for -1 constant.869 def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>;870 def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>;871}872 873// Atomic bit test.874def X86LBTest : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisPtrTy<1>,875 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>;876def x86bts : SDNode<"X86ISD::LBTS", X86LBTest,877 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;878def x86btc : SDNode<"X86ISD::LBTC", X86LBTest,879 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;880def x86btr : SDNode<"X86ISD::LBTR", X86LBTest,881 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;882 883def X86LBTestRM : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>,884 SDTCisInt<2>]>;885 886def x86_rm_bts : SDNode<"X86ISD::LBTS_RM", X86LBTestRM,887 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;888def x86_rm_btc : SDNode<"X86ISD::LBTC_RM", X86LBTestRM,889 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;890def x86_rm_btr : SDNode<"X86ISD::LBTR_RM", X86LBTestRM,891 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;892 893 894multiclass ATOMIC_LOGIC_OP<Format Form, string s> {895 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,896 SchedRW = [WriteBitTestSetRegRMW] in {897 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2),898 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"),899 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>,900 OpSize16, TB, LOCK;901 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2),902 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"),903 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>,904 OpSize32, TB, LOCK;905 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2),906 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"),907 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>,908 TB, LOCK;909 }910}911 912multiclass ATOMIC_LOGIC_OP_RM<bits<8> Opc8, string s> {913 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,914 SchedRW = [WriteBitTestSetRegRMW] in {915 def 16rm : I<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),916 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"),917 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>,918 OpSize16, TB, LOCK;919 def 32rm : I<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),920 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"),921 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>,922 OpSize32, TB, LOCK;923 def 64rm : RI<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),924 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"),925 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>,926 TB, LOCK;927 }928}929 930 931defm LOCK_BTS : ATOMIC_LOGIC_OP<MRM5m, "bts">;932defm LOCK_BTC : ATOMIC_LOGIC_OP<MRM7m, "btc">;933defm LOCK_BTR : ATOMIC_LOGIC_OP<MRM6m, "btr">;934 935defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">;936defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">;937defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">;938 939// Atomic compare and swap.940multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,941 string mnemonic, SDPatternOperator frag> {942let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in {943 let Defs = [AL, EFLAGS], Uses = [AL] in944 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),945 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),946 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;947 let Defs = [AX, EFLAGS], Uses = [AX] in948 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),949 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),950 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK;951 let Defs = [EAX, EFLAGS], Uses = [EAX] in952 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),953 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),954 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK;955 let Defs = [RAX, EFLAGS], Uses = [RAX] in956 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),957 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),958 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;959}960}961 962let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],963 Predicates = [HasCX8], SchedRW = [WriteCMPXCHGRMW],964 isCodeGenOnly = 1, usesCustomInserter = 1 in {965def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),966 "cmpxchg8b\t$ptr",967 [(X86cas8 addr:$ptr)]>, TB, LOCK;968}969 970let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],971 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW],972 isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in {973def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),974 "cmpxchg16b\t$ptr",975 []>, TB, LOCK;976}977 978// This pseudo must be used when the frame uses RBX as979// the base pointer. Indeed, in such situation RBX is a reserved980// register and the register allocator will ignore any use/def of981// it. In other words, the register will not fix the clobbering of982// RBX that will happen when setting the arguments for the instrucion.983//984// Unlike the actual related instruction, we mark that this one985// defines RBX (instead of using RBX).986// The rationale is that we will define RBX during the expansion of987// the pseudo. The argument feeding RBX is rbx_input.988//989// The additional argument, $rbx_save, is a temporary register used to990// save the value of RBX across the actual instruction.991//992// To make sure the register assigned to $rbx_save does not interfere with993// the definition of the actual instruction, we use a definition $dst which994// is tied to $rbx_save. That way, the live-range of $rbx_save spans across995// the instruction and we are sure we will have a valid register to restore996// the value of RBX.997let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX],998 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW],999 isCodeGenOnly = 1, isPseudo = 1,1000 mayLoad = 1, mayStore = 1, hasSideEffects = 0,1001 Constraints = "$rbx_save = $dst" in {1002def LCMPXCHG16B_SAVE_RBX :1003 I<0, Pseudo, (outs GR64:$dst),1004 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), "", []>;1005}1006 1007// Pseudo instruction that doesn't read/write RBX. Will be turned into either1008// LCMPXCHG16B_SAVE_RBX or LCMPXCHG16B via a custom inserter.1009let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX],1010 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW],1011 isCodeGenOnly = 1, isPseudo = 1,1012 mayLoad = 1, mayStore = 1, hasSideEffects = 0,1013 usesCustomInserter = 1 in {1014def LCMPXCHG16B_NO_RBX :1015 I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "",1016 [(X86cas16 addr:$ptr, GR64:$rbx_input)]>;1017}1018 1019// This pseudo must be used when the frame uses RBX/EBX as1020// the base pointer.1021// cf comment for LCMPXCHG16B_SAVE_RBX.1022let Defs = [EBX], Uses = [ECX, EAX],1023 Predicates = [HasMWAITX], SchedRW = [WriteSystem],1024 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst" in {1025def MWAITX_SAVE_RBX :1026 I<0, Pseudo, (outs GR64:$dst),1027 (ins GR32:$ebx_input, GR64:$rbx_save),1028 "mwaitx",1029 []>;1030}1031 1032// Pseudo mwaitx instruction to use for custom insertion.1033let Predicates = [HasMWAITX], SchedRW = [WriteSystem],1034 isCodeGenOnly = 1, isPseudo = 1,1035 usesCustomInserter = 1 in {1036def MWAITX :1037 I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx),1038 "mwaitx",1039 [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>;1040}1041 1042 1043defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>;1044 1045// Atomic exchange and add1046multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,1047 string frag> {1048 let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1,1049 isCodeGenOnly = 1, SchedRW = [WriteALURMW] in {1050 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),1051 (ins GR8:$val, i8mem:$ptr),1052 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),1053 [(set GR8:$dst,1054 (!cast<PatFrag>(frag # "_i8") addr:$ptr, GR8:$val))]>;1055 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),1056 (ins GR16:$val, i16mem:$ptr),1057 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),1058 [(set1059 GR16:$dst,1060 (!cast<PatFrag>(frag # "_i16") addr:$ptr, GR16:$val))]>,1061 OpSize16;1062 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),1063 (ins GR32:$val, i32mem:$ptr),1064 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),1065 [(set1066 GR32:$dst,1067 (!cast<PatFrag>(frag # "_i32") addr:$ptr, GR32:$val))]>,1068 OpSize32;1069 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),1070 (ins GR64:$val, i64mem:$ptr),1071 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),1072 [(set1073 GR64:$dst,1074 (!cast<PatFrag>(frag # "_i64") addr:$ptr, GR64:$val))]>;1075 }1076}1077 1078defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK;1079 1080/* The following multiclass tries to make sure that in code like1081 * x.store (immediate op x.load(acquire), release)1082 * and1083 * x.store (register op x.load(acquire), release)1084 * an operation directly on memory is generated instead of wasting a register.1085 * It is not automatic as atomic_store/load are only lowered to MOV instructions1086 * extremely late to prevent them from being accidentally reordered in the backend1087 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)1088 */1089multiclass RELEASE_BINOP_MI<string Name, SDNode op> {1090 def : Pat<(atomic_store_8 (op (atomic_load_nonext_8 addr:$dst), (i8 imm:$src)),1091 addr:$dst),1092 (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>;1093 def : Pat<(atomic_store_16 (op (atomic_load_nonext_16 addr:$dst), (i16 imm:$src)),1094 addr:$dst),1095 (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>;1096 def : Pat<(atomic_store_32 (op (atomic_load_nonext_32 addr:$dst), (i32 imm:$src)),1097 addr:$dst),1098 (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>;1099 def : Pat<(atomic_store_64 (op (atomic_load_nonext_64 addr:$dst), (i64immSExt32:$src)),1100 addr:$dst),1101 (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>;1102 def : Pat<(atomic_store_8 (op (atomic_load_nonext_8 addr:$dst), (i8 GR8:$src)), addr:$dst),1103 (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>;1104 def : Pat<(atomic_store_16 (op (atomic_load_nonext_16 addr:$dst), (i16 GR16:$src)),1105 addr:$dst),1106 (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>;1107 def : Pat<(atomic_store_32 (op (atomic_load_nonext_32 addr:$dst), (i32 GR32:$src)),1108 addr:$dst),1109 (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>;1110 def : Pat<(atomic_store_64 (op (atomic_load_nonext_64 addr:$dst), (i64 GR64:$src)),1111 addr:$dst),1112 (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>;1113}1114defm : RELEASE_BINOP_MI<"ADD", add>;1115defm : RELEASE_BINOP_MI<"AND", and>;1116defm : RELEASE_BINOP_MI<"OR", or>;1117defm : RELEASE_BINOP_MI<"XOR", xor>;1118defm : RELEASE_BINOP_MI<"SUB", sub>;1119 1120// Atomic load + floating point patterns.1121// FIXME: This could also handle SIMD operations with *ps and *pd instructions.1122multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> {1123 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_nonext_32 addr:$src2)))),1124 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>,1125 Requires<[UseSSE1]>;1126 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_nonext_32 addr:$src2)))),1127 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>,1128 Requires<[UseAVX]>;1129 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_nonext_32 addr:$src2)))),1130 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>,1131 Requires<[HasAVX512]>;1132 1133 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_nonext_64 addr:$src2)))),1134 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>,1135 Requires<[UseSSE1]>;1136 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_nonext_64 addr:$src2)))),1137 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>,1138 Requires<[UseAVX]>;1139 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_nonext_64 addr:$src2)))),1140 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>,1141 Requires<[HasAVX512]>;1142}1143defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>;1144defm : ATOMIC_LOAD_FP_BINOP_MI<"SUB", fsub>;1145defm : ATOMIC_LOAD_FP_BINOP_MI<"MUL", fmul>;1146defm : ATOMIC_LOAD_FP_BINOP_MI<"DIV", fdiv>;1147 1148multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32,1149 dag dag64> {1150 def : Pat<(atomic_store_8 dag8, addr:$dst),1151 (!cast<Instruction>(Name#8m) addr:$dst)>;1152 def : Pat<(atomic_store_16 dag16, addr:$dst),1153 (!cast<Instruction>(Name#16m) addr:$dst)>;1154 def : Pat<(atomic_store_32 dag32, addr:$dst),1155 (!cast<Instruction>(Name#32m) addr:$dst)>;1156 def : Pat<(atomic_store_64 dag64, addr:$dst),1157 (!cast<Instruction>(Name#64m) addr:$dst)>;1158}1159 1160let Predicates = [UseIncDec] in {1161 defm : RELEASE_UNOP<"INC",1162 (add (atomic_load_nonext_8 addr:$dst), (i8 1)),1163 (add (atomic_load_nonext_16 addr:$dst), (i16 1)),1164 (add (atomic_load_nonext_32 addr:$dst), (i32 1)),1165 (add (atomic_load_nonext_64 addr:$dst), (i64 1))>;1166 defm : RELEASE_UNOP<"DEC",1167 (add (atomic_load_nonext_8 addr:$dst), (i8 -1)),1168 (add (atomic_load_nonext_16 addr:$dst), (i16 -1)),1169 (add (atomic_load_nonext_32 addr:$dst), (i32 -1)),1170 (add (atomic_load_nonext_64 addr:$dst), (i64 -1))>;1171}1172 1173defm : RELEASE_UNOP<"NEG",1174 (ineg (i8 (atomic_load_nonext_8 addr:$dst))),1175 (ineg (i16 (atomic_load_nonext_16 addr:$dst))),1176 (ineg (i32 (atomic_load_nonext_32 addr:$dst))),1177 (ineg (i64 (atomic_load_nonext_64 addr:$dst)))>;1178defm : RELEASE_UNOP<"NOT",1179 (not (i8 (atomic_load_nonext_8 addr:$dst))),1180 (not (i16 (atomic_load_nonext_16 addr:$dst))),1181 (not (i32 (atomic_load_nonext_32 addr:$dst))),1182 (not (i64 (atomic_load_nonext_64 addr:$dst)))>;1183 1184def : Pat<(atomic_store_8 (i8 imm:$src), addr:$dst),1185 (MOV8mi addr:$dst, imm:$src)>;1186def : Pat<(atomic_store_16 (i16 imm:$src), addr:$dst),1187 (MOV16mi addr:$dst, imm:$src)>;1188def : Pat<(atomic_store_32 (i32 imm:$src), addr:$dst),1189 (MOV32mi addr:$dst, imm:$src)>;1190def : Pat<(atomic_store_64 (i64immSExt32:$src), addr:$dst),1191 (MOV64mi32 addr:$dst, i64immSExt32:$src)>;1192 1193def : Pat<(atomic_store_8 GR8:$src, addr:$dst),1194 (MOV8mr addr:$dst, GR8:$src)>;1195def : Pat<(atomic_store_16 GR16:$src, addr:$dst),1196 (MOV16mr addr:$dst, GR16:$src)>;1197def : Pat<(atomic_store_32 GR32:$src, addr:$dst),1198 (MOV32mr addr:$dst, GR32:$src)>;1199def : Pat<(atomic_store_64 GR64:$src, addr:$dst),1200 (MOV64mr addr:$dst, GR64:$src)>;1201 1202def : Pat<(i8 (atomic_load_nonext_8 addr:$src)), (MOV8rm addr:$src)>;1203def : Pat<(i16 (atomic_load_nonext_16 addr:$src)), (MOV16rm addr:$src)>;1204def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>;1205def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>;1206 1207// Floating point loads/stores.1208def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst),1209 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>;1210def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst),1211 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>;1212def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst),1213 (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>;1214 1215def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst),1216 (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>;1217def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst),1218 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>;1219def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst),1220 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>;1221 1222def : Pat<(f32 (bitconvert (i32 (atomic_load_nonext_32 addr:$src)))),1223 (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>;1224def : Pat<(f32 (bitconvert (i32 (atomic_load_nonext_32 addr:$src)))),1225 (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>;1226def : Pat<(f32 (bitconvert (i32 (atomic_load_nonext_32 addr:$src)))),1227 (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>;1228 1229def : Pat<(f64 (bitconvert (i64 (atomic_load_nonext_64 addr:$src)))),1230 (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>;1231def : Pat<(f64 (bitconvert (i64 (atomic_load_nonext_64 addr:$src)))),1232 (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>;1233def : Pat<(f64 (bitconvert (i64 (atomic_load_nonext_64 addr:$src)))),1234 (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>;1235 1236//===----------------------------------------------------------------------===//1237// DAG Pattern Matching Rules1238//===----------------------------------------------------------------------===//1239 1240// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves1241// binary size compared to a regular MOV, but it introduces an unnecessary1242// load, so is not suitable for regular or optsize functions.1243let Predicates = [OptForMinSize] in {1244def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi addr:$dst, 0)>;1245def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi addr:$dst, 0)>;1246def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi32 addr:$dst, 0)>;1247def : Pat<(simple_store (i16 -1), addr:$dst), (OR16mi addr:$dst, -1)>;1248def : Pat<(simple_store (i32 -1), addr:$dst), (OR32mi addr:$dst, -1)>;1249def : Pat<(simple_store (i64 -1), addr:$dst), (OR64mi32 addr:$dst, -1)>;1250}1251 1252// In kernel code model, we can get the address of a label1253// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of1254// the MOV64ri32 should accept these.1255def : Pat<(i64 (X86Wrapper tconstpool :$dst)),1256 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;1257def : Pat<(i64 (X86Wrapper tjumptable :$dst)),1258 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;1259 1260// If the globaladdr is an absolute_symbol, don't bother using the sign extending1261// instruction since there's no benefit to using it with absolute symbols.1262def globalAddrNoAbsSym : PatLeaf<(tglobaladdr:$dst), [{1263 auto *GA = cast<GlobalAddressSDNode>(N);1264 return !GA->getGlobal()->getAbsoluteSymbolRange();1265}]>;1266def : Pat<(i64 (X86Wrapper globalAddrNoAbsSym:$dst)),1267 (MOV64ri32 tglobaladdr:$dst)>,1268 Requires<[KernelCode]>;1269 1270def : Pat<(i64 (X86Wrapper texternalsym:$dst)),1271 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;1272def : Pat<(i64 (X86Wrapper mcsym:$dst)),1273 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;1274def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),1275 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;1276 1277// If we have small model and -static mode, it is safe to store global addresses1278// directly as immediates. FIXME: This is really a hack, the 'imm' predicate1279// for MOV64mi32 should handle this sort of thing.1280def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),1281 (MOV64mi32 addr:$dst, tconstpool:$src)>,1282 Requires<[NearData, IsNotPIC]>;1283def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),1284 (MOV64mi32 addr:$dst, tjumptable:$src)>,1285 Requires<[NearData, IsNotPIC]>;1286def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),1287 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,1288 Requires<[NearData, IsNotPIC]>;1289def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),1290 (MOV64mi32 addr:$dst, texternalsym:$src)>,1291 Requires<[NearData, IsNotPIC]>;1292def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),1293 (MOV64mi32 addr:$dst, mcsym:$src)>,1294 Requires<[NearData, IsNotPIC]>;1295def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),1296 (MOV64mi32 addr:$dst, tblockaddress:$src)>,1297 Requires<[NearData, IsNotPIC]>;1298 1299def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;1300def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;1301 1302// Calls1303 1304// tls has some funny stuff here...1305// This corresponds to movabs $foo@tpoff, %rax1306def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),1307 (MOV64ri32 tglobaltlsaddr :$dst)>;1308// This corresponds to add $foo@tpoff, %rax1309def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),1310 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;1311 1312 1313// Direct PC relative function call for small code model. 32-bit displacement1314// sign extended to 64-bit.1315def : Pat<(X86call (i64 tglobaladdr:$dst)),1316 (CALL64pcrel32 tglobaladdr:$dst)>;1317def : Pat<(X86call (i64 texternalsym:$dst)),1318 (CALL64pcrel32 texternalsym:$dst)>;1319 1320def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 texternalsym:$dst)),1321 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, texternalsym:$dst)>;1322def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 tglobaladdr:$dst)),1323 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, tglobaladdr:$dst)>;1324 1325def : Pat<(X86imp_call (i64 tglobaladdr:$dst)),1326 (CALL64pcrel32 tglobaladdr:$dst)>;1327 1328// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they1329// can never use callee-saved registers. That is the purpose of the GR64_TC1330// register classes.1331//1332// The only volatile register that is never used by the calling convention is1333// %r11. This happens when calling a vararg function with 6 arguments.1334//1335// Match an X86tcret that uses less than 7 volatile registers.1336def : Pat<(X86tcret GR32_TC:$dst, timm:$off),1337 (TCRETURNri GR32_TC:$dst, timm:$off)>,1338 Requires<[Not64BitMode, IsNotHiPECCFunc, NotUseIndirectThunkCalls]>;1339 1340def : Pat<(X86tcret GR32:$dst, timm:$off),1341 (TCRETURN_HIPE32ri GR32:$dst, timm:$off)>,1342 Requires<[Not64BitMode, IsHiPECCFunc, NotUseIndirectThunkCalls]>;1343 1344// FIXME: This is disabled for 32-bit PIC mode because the global base1345// register which is part of the address mode may be assigned a1346// callee-saved register.1347// Similar to X86tcret_6regs, here we only have 1 register left1348def : Pat<(X86tcret_1reg (load addr:$dst), timm:$off),1349 (TCRETURNmi addr:$dst, timm:$off)>,1350 Requires<[Not64BitMode, IsNotPIC, NotUseIndirectThunkCalls]>;1351 1352def : Pat<(X86tcret (i32 tglobaladdr:$dst), timm:$off),1353 (TCRETURNdi tglobaladdr:$dst, timm:$off)>,1354 Requires<[NotLP64]>;1355 1356def : Pat<(X86tcret (i32 texternalsym:$dst), timm:$off),1357 (TCRETURNdi texternalsym:$dst, timm:$off)>,1358 Requires<[NotLP64]>;1359 1360def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),1361 (TCRETURNri64 ptr_rc_tailcall:$dst, timm:$off)>,1362 Requires<[In64BitMode, IsNotWin64CCFunc, NotUseIndirectThunkCalls, ImportCallOptimizationDisabled]>;1363 1364def : Pat<(X86tcret GR64_TCW64:$dst, timm:$off),1365 (TCRETURN_WIN64ri GR64_TCW64:$dst, timm:$off)>,1366 Requires<[IsWin64CCFunc, NotUseIndirectThunkCalls, ImportCallOptimizationDisabled]>;1367 1368def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),1369 (TCRETURNri64_ImpCall ptr_rc_tailcall:$dst, timm:$off)>,1370 Requires<[In64BitMode, NotUseIndirectThunkCalls, ImportCallOptimizationEnabled]>;1371 1372// Don't fold loads into X86tcret requiring more than 6 regs.1373// There wouldn't be enough scratch registers for base+index.1374def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off),1375 (TCRETURNmi64 addr:$dst, timm:$off)>,1376 Requires<[In64BitMode, IsNotWin64CCFunc, NotUseIndirectThunkCalls]>;1377 1378def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off),1379 (TCRETURN_WINmi64 addr:$dst, timm:$off)>,1380 Requires<[IsWin64CCFunc, NotUseIndirectThunkCalls]>;1381 1382def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),1383 (INDIRECT_THUNK_TCRETURN64 ptr_rc_tailcall:$dst, timm:$off)>,1384 Requires<[In64BitMode, IsNotWin64CCFunc, UseIndirectThunkCalls]>;1385 1386def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),1387 (INDIRECT_THUNK_TCRETURN32 ptr_rc_tailcall:$dst, timm:$off)>,1388 Requires<[Not64BitMode, IsNotWin64CCFunc, UseIndirectThunkCalls]>;1389 1390def : Pat<(X86tcret (i64 tglobaladdr:$dst), timm:$off),1391 (TCRETURNdi64 tglobaladdr:$dst, timm:$off)>,1392 Requires<[IsLP64]>;1393 1394def : Pat<(X86tcret (i64 texternalsym:$dst), timm:$off),1395 (TCRETURNdi64 texternalsym:$dst, timm:$off)>,1396 Requires<[IsLP64]>;1397 1398// Normal calls, with various flavors of addresses.1399def : Pat<(X86call (i32 tglobaladdr:$dst)),1400 (CALLpcrel32 tglobaladdr:$dst)>;1401def : Pat<(X86call (i32 texternalsym:$dst)),1402 (CALLpcrel32 texternalsym:$dst)>;1403def : Pat<(X86call (i32 imm:$dst)),1404 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;1405 1406// Comparisons.1407 1408// TEST R,R is smaller than CMP R,01409def : Pat<(X86cmp GR8:$src1, 0),1410 (TEST8rr GR8:$src1, GR8:$src1)>;1411def : Pat<(X86cmp GR16:$src1, 0),1412 (TEST16rr GR16:$src1, GR16:$src1)>;1413def : Pat<(X86cmp GR32:$src1, 0),1414 (TEST32rr GR32:$src1, GR32:$src1)>;1415def : Pat<(X86cmp GR64:$src1, 0),1416 (TEST64rr GR64:$src1, GR64:$src1)>;1417 1418// zextload bool -> zextload byte1419// i1 stored in one byte in zero-extended form.1420// Upper bits cleanup should be executed before Store.1421def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;1422def : Pat<(zextloadi16i1 addr:$src),1423 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;1424def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;1425def : Pat<(zextloadi64i1 addr:$src),1426 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;1427 1428// extload bool -> extload byte1429// When extloading from 16-bit and smaller memory locations into 64-bit1430// registers, use zero-extending loads so that the entire 64-bit register is1431// defined, avoiding partial-register updates.1432 1433def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;1434def : Pat<(extloadi16i1 addr:$src),1435 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;1436def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;1437def : Pat<(extloadi16i8 addr:$src),1438 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;1439def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;1440def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;1441 1442// For other extloads, use subregs, since the high contents of the register are1443// defined after an extload.1444// NOTE: The extloadi64i32 pattern needs to be first as it will try to form1445// 32-bit loads for 4 byte aligned i8/i16 loads.1446def : Pat<(extloadi64i32 addr:$src),1447 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;1448def : Pat<(extloadi64i1 addr:$src),1449 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;1450def : Pat<(extloadi64i8 addr:$src),1451 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;1452def : Pat<(extloadi64i16 addr:$src),1453 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;1454 1455// anyext. Define these to do an explicit zero-extend to1456// avoid partial-register updates.1457def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG1458 (MOVZX32rr8 GR8 :$src), sub_16bit)>;1459def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;1460 1461// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.1462def : Pat<(i32 (anyext GR16:$src)),1463 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;1464 1465def : Pat<(i64 (anyext GR8 :$src)),1466 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;1467def : Pat<(i64 (anyext GR16:$src)),1468 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;1469def : Pat<(i64 (anyext GR32:$src)),1470 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>;1471 1472def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>;1473 1474// In the case of a 32-bit def that is known to implicitly zero-extend,1475// we can use a SUBREG_TO_REG.1476def : Pat<(i64 (zext def32:$src)),1477 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;1478def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)),1479 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;1480 1481//===----------------------------------------------------------------------===//1482// Pattern match OR as ADD1483//===----------------------------------------------------------------------===//1484 1485// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be1486// 3-addressified into an LEA instruction to avoid copies. However, we also1487// want to finally emit these instructions as an or at the end of the code1488// generator to make the generated code easier to read. To do this, we select1489// into "disjoint bits" pseudo ops.1490 1491// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.1492// Try this before the selecting to OR.1493let SchedRW = [WriteALU] in {1494 1495let isConvertibleToThreeAddress = 1, isPseudo = 1,1496 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {1497let isCommutable = 1 in {1498def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),1499 "", // orb/addb REG, REG1500 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>;1501def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),1502 "", // orw/addw REG, REG1503 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;1504def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),1505 "", // orl/addl REG, REG1506 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;1507def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),1508 "", // orq/addq REG, REG1509 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;1510} // isCommutable1511 1512def ADD8ri_DB : I<0, Pseudo,1513 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),1514 "", // orb/addb REG, imm81515 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>;1516def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),1517 "", // orw/addw REG, imm1518 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;1519def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),1520 "", // orl/addl REG, imm1521 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;1522def ADD64ri32_DB : I<0, Pseudo,1523 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),1524 "", // orq/addq REG, imm1525 [(set GR64:$dst, (or_is_add GR64:$src1,1526 i64immSExt32:$src2))]>;1527}1528} // AddedComplexity, SchedRW1529 1530//===----------------------------------------------------------------------===//1531// Pattern match XOR as ADD1532//===----------------------------------------------------------------------===//1533 1534// Prefer to pattern match XOR with min_signed_value as ADD at isel time.1535// ADD can be 3-addressified into an LEA instruction to avoid copies.1536let AddedComplexity = 5 in {1537def : Pat<(xor GR8:$src1, -128),1538 (ADD8ri GR8:$src1, -128)>;1539def : Pat<(xor GR16:$src1, -32768),1540 (ADD16ri GR16:$src1, -32768)>;1541def : Pat<(xor GR32:$src1, -2147483648),1542 (ADD32ri GR32:$src1, -2147483648)>;1543}1544 1545//===----------------------------------------------------------------------===//1546// Some peepholes1547//===----------------------------------------------------------------------===//1548 1549// Odd encoding trick: -128 fits into an 8-bit immediate field while1550// +128 doesn't, so in this special case use a sub instead of an add.1551let Predicates = [NoNDD] in {1552 def : Pat<(add GR16:$src1, 128),1553 (SUB16ri GR16:$src1, -128)>;1554 def : Pat<(add GR32:$src1, 128),1555 (SUB32ri GR32:$src1, -128)>;1556 def : Pat<(add GR64:$src1, 128),1557 (SUB64ri32 GR64:$src1, -128)>;1558 1559 def : Pat<(X86add_flag_nocf GR16:$src1, 128),1560 (SUB16ri GR16:$src1, -128)>;1561 def : Pat<(X86add_flag_nocf GR32:$src1, 128),1562 (SUB32ri GR32:$src1, -128)>;1563 def : Pat<(X86add_flag_nocf GR64:$src1, 128),1564 (SUB64ri32 GR64:$src1, -128)>;1565}1566let Predicates = [HasNDD] in {1567 def : Pat<(add GR16:$src1, 128),1568 (SUB16ri_ND GR16:$src1, -128)>;1569 def : Pat<(add GR32:$src1, 128),1570 (SUB32ri_ND GR32:$src1, -128)>;1571 def : Pat<(add GR64:$src1, 128),1572 (SUB64ri32_ND GR64:$src1, -128)>;1573 1574 def : Pat<(X86add_flag_nocf GR16:$src1, 128),1575 (SUB16ri_ND GR16:$src1, -128)>;1576 def : Pat<(X86add_flag_nocf GR32:$src1, 128),1577 (SUB32ri_ND GR32:$src1, -128)>;1578 def : Pat<(X86add_flag_nocf GR64:$src1, 128),1579 (SUB64ri32_ND GR64:$src1, -128)>;1580}1581def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),1582 (SUB16mi addr:$dst, -128)>;1583def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),1584 (SUB32mi addr:$dst, -128)>;1585def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),1586 (SUB64mi32 addr:$dst, -128)>;1587let Predicates = [HasNDD] in {1588 def : Pat<(add (loadi16 addr:$src), 128),1589 (SUB16mi_ND addr:$src, -128)>;1590 def : Pat<(add (loadi32 addr:$src), 128),1591 (SUB32mi_ND addr:$src, -128)>;1592 def : Pat<(add (loadi64 addr:$src), 128),1593 (SUB64mi32_ND addr:$src, -128)>;1594}1595 1596// The same trick applies for 32-bit immediate fields in 64-bit1597// instructions.1598let Predicates = [NoNDD] in {1599 def : Pat<(add GR64:$src1, 0x0000000080000000),1600 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;1601 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000),1602 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;1603}1604let Predicates = [HasNDD] in {1605 def : Pat<(add GR64:$src1, 0x0000000080000000),1606 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>;1607 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000),1608 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>;1609}1610def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst),1611 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;1612let Predicates = [HasNDD] in {1613 def : Pat<(add(loadi64 addr:$src), 0x0000000080000000),1614 (SUB64mi32_ND addr:$src, 0xffffffff80000000)>;1615}1616 1617// Depositing value to 8/16 bit subreg:1618def : Pat<(or (and GR64:$dst, -256),1619 (i64 (zextloadi8 addr:$src))),1620 (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>;1621 1622def : Pat<(or (and GR32:$dst, -256),1623 (i32 (zextloadi8 addr:$src))),1624 (INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>;1625 1626def : Pat<(or (and GR64:$dst, -65536),1627 (i64 (zextloadi16 addr:$src))),1628 (INSERT_SUBREG (i64 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>;1629 1630def : Pat<(or (and GR32:$dst, -65536),1631 (i32 (zextloadi16 addr:$src))),1632 (INSERT_SUBREG (i32 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>;1633 1634// To avoid needing to materialize an immediate in a register, use a 32-bit and1635// with implicit zero-extension instead of a 64-bit and if the immediate has at1636// least 32 bits of leading zeros. If in addition the last 32 bits can be1637// represented with a sign extension of a 8 bit constant, use that.1638// This can also reduce instruction size by eliminating the need for the REX1639// prefix.1640 1641// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.1642let AddedComplexity = 1 in {1643 let Predicates = [NoNDD] in {1644 def : Pat<(and GR64:$src, i64immZExt32:$imm),1645 (SUBREG_TO_REG1646 (i64 0),1647 (AND32ri1648 (EXTRACT_SUBREG GR64:$src, sub_32bit),1649 (i32 (GetLo32XForm imm:$imm))),1650 sub_32bit)>;1651 }1652 let Predicates = [HasNDD] in {1653 def : Pat<(and GR64:$src, i64immZExt32:$imm),1654 (SUBREG_TO_REG1655 (i64 0),1656 (AND32ri_ND1657 (EXTRACT_SUBREG GR64:$src, sub_32bit),1658 (i32 (GetLo32XForm imm:$imm))),1659 sub_32bit)>;1660 }1661} // AddedComplexity = 11662 1663 1664// AddedComplexity is needed due to the increased complexity on the1665// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all1666// the MOVZX patterns keeps thems together in DAGIsel tables.1667let AddedComplexity = 1 in {1668// r & (2^16-1) ==> movz1669def : Pat<(and GR32:$src1, 0xffff),1670 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;1671// r & (2^8-1) ==> movz1672def : Pat<(and GR32:$src1, 0xff),1673 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>;1674// r & (2^8-1) ==> movz1675def : Pat<(and GR16:$src1, 0xff),1676 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)),1677 sub_16bit)>;1678 1679// r & (2^32-1) ==> movz1680def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),1681 (SUBREG_TO_REG (i64 0),1682 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),1683 sub_32bit)>;1684// r & (2^16-1) ==> movz1685def : Pat<(and GR64:$src, 0xffff),1686 (SUBREG_TO_REG (i64 0),1687 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),1688 sub_32bit)>;1689// r & (2^8-1) ==> movz1690def : Pat<(and GR64:$src, 0xff),1691 (SUBREG_TO_REG (i64 0),1692 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),1693 sub_32bit)>;1694} // AddedComplexity = 11695 1696 1697// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits.1698 1699def BTRXForm : SDNodeXForm<imm, [{1700 // Transformation function: Find the lowest 0.1701 return getI64Imm((uint8_t)N->getAPIntValue().countr_one(), SDLoc(N));1702}]>;1703 1704def BTCBTSXForm : SDNodeXForm<imm, [{1705 // Transformation function: Find the lowest 1.1706 return getI64Imm((uint8_t)N->getAPIntValue().countr_zero(), SDLoc(N));1707}]>;1708 1709def BTRMask64 : ImmLeaf<i64, [{1710 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm);1711}]>;1712 1713def BTCBTSMask64 : ImmLeaf<i64, [{1714 return !isInt<32>(Imm) && isPowerOf2_64(Imm);1715}]>;1716 1717// For now only do this for optsize.1718let AddedComplexity = 1, Predicates=[OptForSize] in {1719 def : Pat<(and GR64:$src1, BTRMask64:$mask),1720 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>;1721 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask),1722 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>;1723 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask),1724 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>;1725}1726 1727 1728// sext_inreg patterns1729def : Pat<(sext_inreg GR32:$src, i16),1730 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;1731def : Pat<(sext_inreg GR32:$src, i8),1732 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>;1733 1734def : Pat<(sext_inreg GR16:$src, i8),1735 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)),1736 sub_16bit)>;1737 1738def : Pat<(sext_inreg GR64:$src, i32),1739 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;1740def : Pat<(sext_inreg GR64:$src, i16),1741 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;1742def : Pat<(sext_inreg GR64:$src, i8),1743 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;1744 1745// sext, sext_load, zext, zext_load1746def: Pat<(i16 (sext GR8:$src)),1747 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;1748def: Pat<(sextloadi16i8 addr:$src),1749 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;1750def: Pat<(i16 (zext GR8:$src)),1751 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;1752def: Pat<(zextloadi16i8 addr:$src),1753 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;1754 1755// trunc patterns1756def : Pat<(i16 (trunc GR32:$src)),1757 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;1758def : Pat<(i8 (trunc GR32:$src)),1759 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),1760 sub_8bit)>,1761 Requires<[Not64BitMode]>;1762def : Pat<(i8 (trunc GR16:$src)),1763 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),1764 sub_8bit)>,1765 Requires<[Not64BitMode]>;1766def : Pat<(i32 (trunc GR64:$src)),1767 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;1768def : Pat<(i16 (trunc GR64:$src)),1769 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;1770def : Pat<(i8 (trunc GR64:$src)),1771 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;1772def : Pat<(i8 (trunc GR32:$src)),1773 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,1774 Requires<[In64BitMode]>;1775def : Pat<(i8 (trunc GR16:$src)),1776 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,1777 Requires<[In64BitMode]>;1778 1779def immff00_ffff : ImmLeaf<i32, [{1780 return Imm >= 0xff00 && Imm <= 0xffff;1781}]>;1782 1783// h-register tricks1784def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),1785 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,1786 Requires<[Not64BitMode]>;1787def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),1788 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,1789 Requires<[Not64BitMode]>;1790def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),1791 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>,1792 Requires<[Not64BitMode]>;1793def : Pat<(srl GR16:$src, (i8 8)),1794 (EXTRACT_SUBREG1795 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),1796 sub_16bit)>;1797def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),1798 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;1799def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),1800 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;1801def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),1802 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;1803def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)),1804 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;1805 1806// h-register tricks.1807// For now, be conservative on x86-64 and use an h-register extract only if the1808// value is immediately zero-extended or stored, which are somewhat common1809// cases. This uses a bunch of code to prevent a register requiring a REX prefix1810// from being allocated in the same instruction as the h register, as there's1811// currently no way to describe this requirement to the register allocator.1812 1813// h-register extract and zero-extend.1814def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),1815 (SUBREG_TO_REG1816 (i64 0),1817 (MOVZX32rr8_NOREX1818 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)),1819 sub_32bit)>;1820def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),1821 (SUBREG_TO_REG1822 (i64 0),1823 (MOVZX32rr8_NOREX1824 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),1825 sub_32bit)>;1826def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),1827 (SUBREG_TO_REG1828 (i64 0),1829 (MOVZX32rr8_NOREX1830 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),1831 sub_32bit)>;1832 1833// h-register extract and store.1834def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),1835 (MOV8mr_NOREX1836 addr:$dst,1837 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>;1838def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),1839 (MOV8mr_NOREX1840 addr:$dst,1841 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,1842 Requires<[In64BitMode]>;1843def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),1844 (MOV8mr_NOREX1845 addr:$dst,1846 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,1847 Requires<[In64BitMode]>;1848 1849// Special pattern to catch the last step of __builtin_parity handling. Our1850// goal is to use an xor of an h-register with the corresponding l-register.1851// The above patterns would handle this on non 64-bit targets, but for 64-bit1852// we need to be more careful. We're using a NOREX instruction here in case1853// register allocation fails to keep the two registers together. So we need to1854// make sure we can't accidentally mix R8-R15 with an h-register.1855def : Pat<(X86xor_flag (i8 (trunc GR32:$src)),1856 (i8 (trunc (srl_su GR32:$src, (i8 8))))),1857 (XOR8rr_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit),1858 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;1859 1860// (shl x, 1) ==> (add x, x)1861// Note that if x is undef (immediate or otherwise), we could theoretically1862// end up with the two uses of x getting different values, producing a result1863// where the least significant bit is not 0. However, the probability of this1864// happening is considered low enough that this is officially not a1865// "real problem".1866let Predicates = [NoNDD] in {1867 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;1868 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;1869 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;1870 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;1871}1872let Predicates = [HasNDD] in {1873 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr_ND GR8 :$src1, GR8 :$src1)>;1874 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr_ND GR16:$src1, GR16:$src1)>;1875 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr_ND GR32:$src1, GR32:$src1)>;1876 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr_ND GR64:$src1, GR64:$src1)>;1877}1878 1879// Shift amount is implicitly masked.1880multiclass MaskedShiftAmountPats<SDNode frag> {1881 // (shift x (and y, 31)) ==> (shift x, y)1882 // (shift x (and y, 63)) ==> (shift x, y)1883 let Predicates = [NoNDD] in {1884 def : Pat<(frag GR8:$src1, (shiftMask32 CL)),1885 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>;1886 def : Pat<(frag GR16:$src1, (shiftMask32 CL)),1887 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>;1888 def : Pat<(frag GR32:$src1, (shiftMask32 CL)),1889 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>;1890 def : Pat<(frag GR64:$src1, (shiftMask64 CL)),1891 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>;1892 }1893 let Predicates = [HasNDD] in {1894 def : Pat<(frag GR8:$src1, (shiftMask32 CL)),1895 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>;1896 def : Pat<(frag GR16:$src1, (shiftMask32 CL)),1897 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>;1898 def : Pat<(frag GR32:$src1, (shiftMask32 CL)),1899 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>;1900 def : Pat<(frag GR64:$src1, (shiftMask64 CL)),1901 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>;1902 }1903 1904 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst),1905 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>;1906 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst),1907 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>;1908 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst),1909 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>;1910 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst),1911 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>;1912 1913 let Predicates = [HasNDD] in {1914 def : Pat<(frag (loadi8 addr:$src), (shiftMask32 CL)),1915 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>;1916 def : Pat<(frag (loadi16 addr:$src), (shiftMask32 CL)),1917 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>;1918 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)),1919 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>;1920 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)),1921 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>;1922 }1923}1924 1925defm SHL : MaskedShiftAmountPats<shl>;1926defm SHR : MaskedShiftAmountPats<srl>;1927defm SAR : MaskedShiftAmountPats<sra>;1928 1929// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and1930// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount1931// because over-rotating produces the same result. This is noted in the Intel1932// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation1933// amount could affect EFLAGS results, but that does not matter because we are1934// not tracking flags for these nodes.1935multiclass MaskedRotateAmountPats<SDNode frag> {1936 // (rot x (and y, BitWidth - 1)) ==> (rot x, y)1937 let Predicates = [NoNDD] in {1938 def : Pat<(frag GR8:$src1, (shiftMask8 CL)),1939 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>;1940 def : Pat<(frag GR16:$src1, (shiftMask16 CL)),1941 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>;1942 def : Pat<(frag GR32:$src1, (shiftMask32 CL)),1943 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>;1944 def : Pat<(frag GR64:$src1, (shiftMask64 CL)),1945 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>;1946 }1947 let Predicates = [HasNDD] in {1948 def : Pat<(frag GR8:$src1, (shiftMask8 CL)),1949 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>;1950 def : Pat<(frag GR16:$src1, (shiftMask16 CL)),1951 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>;1952 def : Pat<(frag GR32:$src1, (shiftMask32 CL)),1953 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>;1954 def : Pat<(frag GR64:$src1, (shiftMask64 CL)),1955 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>;1956 }1957 1958 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst),1959 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>;1960 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst),1961 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>;1962 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst),1963 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>;1964 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst),1965 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>;1966 1967 let Predicates = [HasNDD] in {1968 def : Pat<(frag (loadi8 addr:$src), (shiftMask8 CL)),1969 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>;1970 def : Pat<(frag (loadi16 addr:$src), (shiftMask16 CL)),1971 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>;1972 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)),1973 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>;1974 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)),1975 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>;1976 }1977}1978 1979defm ROL : MaskedRotateAmountPats<rotl>;1980defm ROR : MaskedRotateAmountPats<rotr>;1981 1982multiclass MaskedShlrdAmountPats<string suffix, Predicate p> {1983 let Predicates = [p] in {1984 // Double "funnel" shift amount is implicitly masked.1985 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32)1986 def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)),1987 (!cast<Instruction>(SHLD16rrCL#suffix) GR16:$src1, GR16:$src2)>;1988 def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)),1989 (!cast<Instruction>(SHRD16rrCL#suffix) GR16:$src1, GR16:$src2)>;1990 1991 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y)1992 def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)),1993 (!cast<Instruction>(SHLD32rrCL#suffix) GR32:$src1, GR32:$src2)>;1994 def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)),1995 (!cast<Instruction>(SHRD32rrCL#suffix) GR32:$src1, GR32:$src2)>;1996 1997 // (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y)1998 def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)),1999 (!cast<Instruction>(SHLD64rrCL#suffix) GR64:$src1, GR64:$src2)>;2000 def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)),2001 (!cast<Instruction>(SHRD64rrCL#suffix) GR64:$src1, GR64:$src2)>;2002 }2003}2004 2005defm : MaskedShlrdAmountPats<"", NoNDD>;2006defm : MaskedShlrdAmountPats<"_ND", HasNDD>;2007 2008// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location.2009multiclass OneBitPats<RegisterClass rc, ValueType vt, Instruction btr,2010 Instruction bts, Instruction btc, PatFrag mask> {2011 def : Pat<(and rc:$src1, (rotl -2, GR8:$src2)),2012 (btr rc:$src1,2013 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;2014 def : Pat<(or rc:$src1, (shl 1, GR8:$src2)),2015 (bts rc:$src1,2016 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;2017 def : Pat<(xor rc:$src1, (shl 1, GR8:$src2)),2018 (btc rc:$src1,2019 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;2020 2021 // Similar to above, but removing unneeded masking of the shift amount.2022 def : Pat<(and rc:$src1, (rotl -2, (mask GR8:$src2))),2023 (btr rc:$src1,2024 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;2025 def : Pat<(or rc:$src1, (shl 1, (mask GR8:$src2))),2026 (bts rc:$src1,2027 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;2028 def : Pat<(xor rc:$src1, (shl 1, (mask GR8:$src2))),2029 (btc rc:$src1,2030 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;2031}2032 2033defm : OneBitPats<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>;2034defm : OneBitPats<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>;2035defm : OneBitPats<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>;2036 2037//===----------------------------------------------------------------------===//2038// EFLAGS-defining Patterns2039//===----------------------------------------------------------------------===//2040 2041multiclass EFLAGSDefiningPats<string suffix, Predicate p> {2042 let Predicates = [p] in {2043 // add reg, reg2044 def : Pat<(add GR8 :$src1, GR8 :$src2), (!cast<Instruction>(ADD8rr#suffix) GR8 :$src1, GR8 :$src2)>;2045 def : Pat<(add GR16:$src1, GR16:$src2), (!cast<Instruction>(ADD16rr#suffix) GR16:$src1, GR16:$src2)>;2046 def : Pat<(add GR32:$src1, GR32:$src2), (!cast<Instruction>(ADD32rr#suffix) GR32:$src1, GR32:$src2)>;2047 def : Pat<(add GR64:$src1, GR64:$src2), (!cast<Instruction>(ADD64rr#suffix) GR64:$src1, GR64:$src2)>;2048 2049 // add reg, mem2050 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),2051 (!cast<Instruction>(ADD8rm#suffix) GR8:$src1, addr:$src2)>;2052 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),2053 (!cast<Instruction>(ADD16rm#suffix) GR16:$src1, addr:$src2)>;2054 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),2055 (!cast<Instruction>(ADD32rm#suffix) GR32:$src1, addr:$src2)>;2056 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),2057 (!cast<Instruction>(ADD64rm#suffix) GR64:$src1, addr:$src2)>;2058 2059 // add reg, imm2060 def : Pat<(add GR8 :$src1, imm:$src2), (!cast<Instruction>(ADD8ri#suffix) GR8:$src1 , imm:$src2)>;2061 def : Pat<(add GR16:$src1, imm:$src2), (!cast<Instruction>(ADD16ri#suffix) GR16:$src1, imm:$src2)>;2062 def : Pat<(add GR32:$src1, imm:$src2), (!cast<Instruction>(ADD32ri#suffix) GR32:$src1, imm:$src2)>;2063 def : Pat<(add GR64:$src1, i64immSExt32:$src2), (!cast<Instruction>(ADD64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;2064 2065 // sub reg, reg2066 def : Pat<(sub GR8 :$src1, GR8 :$src2), (!cast<Instruction>(SUB8rr#suffix) GR8 :$src1, GR8 :$src2)>;2067 def : Pat<(sub GR16:$src1, GR16:$src2), (!cast<Instruction>(SUB16rr#suffix) GR16:$src1, GR16:$src2)>;2068 def : Pat<(sub GR32:$src1, GR32:$src2), (!cast<Instruction>(SUB32rr#suffix) GR32:$src1, GR32:$src2)>;2069 def : Pat<(sub GR64:$src1, GR64:$src2), (!cast<Instruction>(SUB64rr#suffix) GR64:$src1, GR64:$src2)>;2070 2071 // sub reg, mem2072 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),2073 (!cast<Instruction>(SUB8rm#suffix) GR8:$src1, addr:$src2)>;2074 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),2075 (!cast<Instruction>(SUB16rm#suffix) GR16:$src1, addr:$src2)>;2076 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),2077 (!cast<Instruction>(SUB32rm#suffix) GR32:$src1, addr:$src2)>;2078 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),2079 (!cast<Instruction>(SUB64rm#suffix) GR64:$src1, addr:$src2)>;2080 2081 // sub reg, imm2082 def : Pat<(sub GR8:$src1, imm:$src2),2083 (!cast<Instruction>(SUB8ri#suffix) GR8:$src1, imm:$src2)>;2084 def : Pat<(sub GR16:$src1, imm:$src2),2085 (!cast<Instruction>(SUB16ri#suffix) GR16:$src1, imm:$src2)>;2086 def : Pat<(sub GR32:$src1, imm:$src2),2087 (!cast<Instruction>(SUB32ri#suffix) GR32:$src1, imm:$src2)>;2088 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),2089 (!cast<Instruction>(SUB64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;2090 2091 // sub 0, reg2092 def : Pat<(X86sub_flag 0, GR8 :$src), (!cast<Instruction>(NEG8r#suffix) GR8 :$src)>;2093 def : Pat<(X86sub_flag 0, GR16:$src), (!cast<Instruction>(NEG16r#suffix) GR16:$src)>;2094 def : Pat<(X86sub_flag 0, GR32:$src), (!cast<Instruction>(NEG32r#suffix) GR32:$src)>;2095 def : Pat<(X86sub_flag 0, GR64:$src), (!cast<Instruction>(NEG64r#suffix) GR64:$src)>;2096 2097 // mul reg, reg2098 def : Pat<(mul GR16:$src1, GR16:$src2),2099 (!cast<Instruction>(IMUL16rr#suffix) GR16:$src1, GR16:$src2)>;2100 def : Pat<(mul GR32:$src1, GR32:$src2),2101 (!cast<Instruction>(IMUL32rr#suffix) GR32:$src1, GR32:$src2)>;2102 def : Pat<(mul GR64:$src1, GR64:$src2),2103 (!cast<Instruction>(IMUL64rr#suffix) GR64:$src1, GR64:$src2)>;2104 2105 // mul reg, mem2106 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),2107 (!cast<Instruction>(IMUL16rm#suffix) GR16:$src1, addr:$src2)>;2108 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),2109 (!cast<Instruction>(IMUL32rm#suffix) GR32:$src1, addr:$src2)>;2110 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),2111 (!cast<Instruction>(IMUL64rm#suffix) GR64:$src1, addr:$src2)>;2112 2113 // or reg/reg.2114 def : Pat<(or GR8 :$src1, GR8 :$src2), (!cast<Instruction>(OR8rr#suffix) GR8 :$src1, GR8 :$src2)>;2115 def : Pat<(or GR16:$src1, GR16:$src2), (!cast<Instruction>(OR16rr#suffix) GR16:$src1, GR16:$src2)>;2116 def : Pat<(or GR32:$src1, GR32:$src2), (!cast<Instruction>(OR32rr#suffix) GR32:$src1, GR32:$src2)>;2117 def : Pat<(or GR64:$src1, GR64:$src2), (!cast<Instruction>(OR64rr#suffix) GR64:$src1, GR64:$src2)>;2118 2119 // or reg/mem2120 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),2121 (!cast<Instruction>(OR8rm#suffix) GR8:$src1, addr:$src2)>;2122 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),2123 (!cast<Instruction>(OR16rm#suffix) GR16:$src1, addr:$src2)>;2124 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),2125 (!cast<Instruction>(OR32rm#suffix) GR32:$src1, addr:$src2)>;2126 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),2127 (!cast<Instruction>(OR64rm#suffix) GR64:$src1, addr:$src2)>;2128 2129 // or reg/imm2130 def : Pat<(or GR8:$src1 , imm:$src2), (!cast<Instruction>(OR8ri#suffix) GR8 :$src1, imm:$src2)>;2131 def : Pat<(or GR16:$src1, imm:$src2), (!cast<Instruction>(OR16ri#suffix) GR16:$src1, imm:$src2)>;2132 def : Pat<(or GR32:$src1, imm:$src2), (!cast<Instruction>(OR32ri#suffix) GR32:$src1, imm:$src2)>;2133 def : Pat<(or GR64:$src1, i64immSExt32:$src2),2134 (!cast<Instruction>(OR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;2135 2136 // xor reg/reg2137 def : Pat<(xor GR8 :$src1, GR8 :$src2), (!cast<Instruction>(XOR8rr#suffix) GR8 :$src1, GR8 :$src2)>;2138 def : Pat<(xor GR16:$src1, GR16:$src2), (!cast<Instruction>(XOR16rr#suffix) GR16:$src1, GR16:$src2)>;2139 def : Pat<(xor GR32:$src1, GR32:$src2), (!cast<Instruction>(XOR32rr#suffix) GR32:$src1, GR32:$src2)>;2140 def : Pat<(xor GR64:$src1, GR64:$src2), (!cast<Instruction>(XOR64rr#suffix) GR64:$src1, GR64:$src2)>;2141 2142 // xor reg/mem2143 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),2144 (!cast<Instruction>(XOR8rm#suffix) GR8:$src1, addr:$src2)>;2145 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),2146 (!cast<Instruction>(XOR16rm#suffix) GR16:$src1, addr:$src2)>;2147 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),2148 (!cast<Instruction>(XOR32rm#suffix) GR32:$src1, addr:$src2)>;2149 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),2150 (!cast<Instruction>(XOR64rm#suffix) GR64:$src1, addr:$src2)>;2151 2152 // xor reg/imm2153 def : Pat<(xor GR8:$src1, imm:$src2),2154 (!cast<Instruction>(XOR8ri#suffix) GR8:$src1, imm:$src2)>;2155 def : Pat<(xor GR16:$src1, imm:$src2),2156 (!cast<Instruction>(XOR16ri#suffix) GR16:$src1, imm:$src2)>;2157 def : Pat<(xor GR32:$src1, imm:$src2),2158 (!cast<Instruction>(XOR32ri#suffix) GR32:$src1, imm:$src2)>;2159 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),2160 (!cast<Instruction>(XOR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;2161 2162 // and reg/reg2163 def : Pat<(and GR8 :$src1, GR8 :$src2), (!cast<Instruction>(AND8rr#suffix) GR8 :$src1, GR8 :$src2)>;2164 def : Pat<(and GR16:$src1, GR16:$src2), (!cast<Instruction>(AND16rr#suffix) GR16:$src1, GR16:$src2)>;2165 def : Pat<(and GR32:$src1, GR32:$src2), (!cast<Instruction>(AND32rr#suffix) GR32:$src1, GR32:$src2)>;2166 def : Pat<(and GR64:$src1, GR64:$src2), (!cast<Instruction>(AND64rr#suffix) GR64:$src1, GR64:$src2)>;2167 2168 // and reg/mem2169 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),2170 (!cast<Instruction>(AND8rm#suffix) GR8:$src1, addr:$src2)>;2171 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),2172 (!cast<Instruction>(AND16rm#suffix) GR16:$src1, addr:$src2)>;2173 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),2174 (!cast<Instruction>(AND32rm#suffix) GR32:$src1, addr:$src2)>;2175 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),2176 (!cast<Instruction>(AND64rm#suffix) GR64:$src1, addr:$src2)>;2177 2178 // and reg/imm2179 def : Pat<(and GR8:$src1, imm:$src2),2180 (!cast<Instruction>(AND8ri#suffix) GR8:$src1, imm:$src2)>;2181 def : Pat<(and GR16:$src1, imm:$src2),2182 (!cast<Instruction>(AND16ri#suffix) GR16:$src1, imm:$src2)>;2183 def : Pat<(and GR32:$src1, imm:$src2),2184 (!cast<Instruction>(AND32ri#suffix) GR32:$src1, imm:$src2)>;2185 def : Pat<(and GR64:$src1, i64immSExt32:$src2),2186 (!cast<Instruction>(AND64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;2187 }2188 2189 // Increment/Decrement reg.2190 // Do not make INC/DEC if it is slow2191 let Predicates = [UseIncDec, p] in {2192 def : Pat<(add GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>;2193 def : Pat<(add GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>;2194 def : Pat<(add GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>;2195 def : Pat<(add GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>;2196 def : Pat<(add GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>;2197 def : Pat<(add GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>;2198 def : Pat<(add GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>;2199 def : Pat<(add GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>;2200 2201 def : Pat<(X86add_flag_nocf GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>;2202 def : Pat<(X86add_flag_nocf GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>;2203 def : Pat<(X86add_flag_nocf GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>;2204 def : Pat<(X86add_flag_nocf GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>;2205 def : Pat<(X86sub_flag_nocf GR8:$src, -1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>;2206 def : Pat<(X86sub_flag_nocf GR16:$src, -1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>;2207 def : Pat<(X86sub_flag_nocf GR32:$src, -1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>;2208 def : Pat<(X86sub_flag_nocf GR64:$src, -1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>;2209 2210 def : Pat<(or_is_add GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>;2211 def : Pat<(or_is_add GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>;2212 def : Pat<(or_is_add GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>;2213 def : Pat<(or_is_add GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>;2214 }2215}2216 2217defm : EFLAGSDefiningPats<"", NoNDD>;2218defm : EFLAGSDefiningPats<"_ND", HasNDD>;2219 2220let Predicates = [HasZU] in {2221 // zext (mul reg/mem, imm) -> imulzu2222 def : Pat<(i32 (zext (i16 (mul GR16:$src1, imm:$src2)))),2223 (SUBREG_TO_REG (i32 0), (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>;2224 def : Pat<(i32 (zext (i16 (mul (loadi16 addr:$src1), imm:$src2)))),2225 (SUBREG_TO_REG (i32 0), (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>;2226 def : Pat<(i64 (zext (i16 (mul GR16:$src1, imm:$src2)))),2227 (SUBREG_TO_REG (i64 0), (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>;2228 def : Pat<(i64 (zext (i16 (mul (loadi16 addr:$src1), imm:$src2)))),2229 (SUBREG_TO_REG (i64 0), (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>;2230}2231 2232// mul reg, imm2233def : Pat<(mul GR16:$src1, imm:$src2),2234 (IMUL16rri GR16:$src1, imm:$src2)>;2235def : Pat<(mul GR32:$src1, imm:$src2),2236 (IMUL32rri GR32:$src1, imm:$src2)>;2237def : Pat<(mul GR64:$src1, i64immSExt32:$src2),2238 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;2239 2240// reg = mul mem, imm2241def : Pat<(mul (loadi16 addr:$src1), imm:$src2),2242 (IMUL16rmi addr:$src1, imm:$src2)>;2243def : Pat<(mul (loadi32 addr:$src1), imm:$src2),2244 (IMUL32rmi addr:$src1, imm:$src2)>;2245def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),2246 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;2247 2248// Bit scan instruction patterns to match explicit zero-undef behavior.2249def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr (i16 (IMPLICIT_DEF)), GR16:$src)>;2250def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr (i32 (IMPLICIT_DEF)), GR32:$src)>;2251def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr (i64 (IMPLICIT_DEF)), GR64:$src)>;2252def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm (i16 (IMPLICIT_DEF)), addr:$src)>;2253def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm (i32 (IMPLICIT_DEF)), addr:$src)>;2254def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm (i64 (IMPLICIT_DEF)), addr:$src)>;2255 2256// When HasMOVBE is enabled it is possible to get a non-legalized2257// register-register 16 bit bswap. This maps it to a ROL instruction.2258let Predicates = [HasMOVBE] in {2259 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;2260}2261