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1//===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the sign and zero extension operations.10//11//===----------------------------------------------------------------------===//12 13let hasSideEffects = 0 in {14 let Defs = [AX], Uses = [AL] in // AX = signext(AL)15 def CBW : I<0x98, RawFrm, (outs), (ins),16 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;17 let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)18 def CWDE : I<0x98, RawFrm, (outs), (ins),19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;20 let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)21 def CDQE : RI<0x98, RawFrm, (outs), (ins),22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;23 24 // FIXME: CWD/CDQ/CQO shouldn't Def the A register, but the fast register25 // allocator crashes if you remove it.26 let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)27 def CWD : I<0x99, RawFrm, (outs), (ins),28 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;29 let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)30 def CDQ : I<0x99, RawFrm, (outs), (ins),31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;32 let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)33 def CQO : RI<0x99, RawFrm, (outs), (ins),34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;35}36 37// Sign/Zero extenders38let hasSideEffects = 0 in {39def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),40 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>,41 TB, OpSize16, Sched<[WriteALU]>;42let mayLoad = 1 in43def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),44 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>,45 TB, OpSize16, Sched<[WriteLoad]>;46} // hasSideEffects = 047def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),48 "movs{bl|x}\t{$src, $dst|$dst, $src}",49 [(set GR32:$dst, (sext GR8:$src))]>, TB,50 OpSize32, Sched<[WriteALU]>;51def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),52 "movs{bl|x}\t{$src, $dst|$dst, $src}",53 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB,54 OpSize32, Sched<[WriteLoad]>;55def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),56 "movs{wl|x}\t{$src, $dst|$dst, $src}",57 [(set GR32:$dst, (sext GR16:$src))]>, TB,58 OpSize32, Sched<[WriteALU]>;59def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),60 "movs{wl|x}\t{$src, $dst|$dst, $src}",61 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>,62 OpSize32, TB, Sched<[WriteLoad]>;63 64let hasSideEffects = 0 in {65def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),66 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>,67 TB, OpSize16, Sched<[WriteALU]>;68let mayLoad = 1 in69def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),70 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>,71 TB, OpSize16, Sched<[WriteLoad]>;72} // hasSideEffects = 073def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),74 "movz{bl|x}\t{$src, $dst|$dst, $src}",75 [(set GR32:$dst, (zext GR8:$src))]>, TB,76 OpSize32, Sched<[WriteALU]>;77def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),78 "movz{bl|x}\t{$src, $dst|$dst, $src}",79 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB,80 OpSize32, Sched<[WriteLoad]>;81def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),82 "movz{wl|x}\t{$src, $dst|$dst, $src}",83 [(set GR32:$dst, (zext GR16:$src))]>, TB,84 OpSize32, Sched<[WriteALU]>;85def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),86 "movz{wl|x}\t{$src, $dst|$dst, $src}",87 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>,88 TB, OpSize32, Sched<[WriteLoad]>;89 90// These instructions exist as a consequence of operand size prefix having91// control of the destination size, but not the input size. Only support them92// for the disassembler.93let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {94def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),95 "movs{ww|x}\t{$src, $dst|$dst, $src}",96 []>, TB, OpSize16, Sched<[WriteALU]>;97def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),98 "movz{ww|x}\t{$src, $dst|$dst, $src}",99 []>, TB, OpSize16, Sched<[WriteALU]>;100let mayLoad = 1 in {101def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),102 "movs{ww|x}\t{$src, $dst|$dst, $src}",103 []>, OpSize16, TB, Sched<[WriteLoad]>;104def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),105 "movz{ww|x}\t{$src, $dst|$dst, $src}",106 []>, TB, OpSize16, Sched<[WriteLoad]>;107} // mayLoad = 1108} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0109 110// These are the same as the regular MOVZX32rr8 and MOVZX32rm8111// except that they use GR32_NOREX for the output operand register class112// instead of GR32. This allows them to operate on h registers on x86-64.113let hasSideEffects = 0, isCodeGenOnly = 1 in {114def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg,115 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),116 "movz{bl|x}\t{$src, $dst|$dst, $src}",117 []>, TB, OpSize32, Sched<[WriteALU]>;118let mayLoad = 1 in119def MOVZX32rm8_NOREX : I<0xB6, MRMSrcMem,120 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),121 "movz{bl|x}\t{$src, $dst|$dst, $src}",122 []>, TB, OpSize32, Sched<[WriteLoad]>;123 124def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg,125 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),126 "movs{bl|x}\t{$src, $dst|$dst, $src}",127 []>, TB, OpSize32, Sched<[WriteALU]>;128let mayLoad = 1 in129def MOVSX32rm8_NOREX : I<0xBE, MRMSrcMem,130 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),131 "movs{bl|x}\t{$src, $dst|$dst, $src}",132 []>, TB, OpSize32, Sched<[WriteLoad]>;133}134 135// MOVSX64rr8 always has a REX prefix and it has an 8-bit register136// operand, which makes it a rare instruction with an 8-bit register137// operand that can never access an h register. If support for h registers138// were generalized, this would require a special register class.139def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),140 "movs{bq|x}\t{$src, $dst|$dst, $src}",141 [(set GR64:$dst, (sext GR8:$src))]>, TB,142 Sched<[WriteALU]>;143def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),144 "movs{bq|x}\t{$src, $dst|$dst, $src}",145 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>,146 TB, Sched<[WriteLoad]>;147def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),148 "movs{wq|x}\t{$src, $dst|$dst, $src}",149 [(set GR64:$dst, (sext GR16:$src))]>, TB,150 Sched<[WriteALU]>;151def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),152 "movs{wq|x}\t{$src, $dst|$dst, $src}",153 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>,154 TB, Sched<[WriteLoad]>;155def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),156 "movs{lq|xd}\t{$src, $dst|$dst, $src}",157 [(set GR64:$dst, (sext GR32:$src))]>,158 Sched<[WriteALU]>, Requires<[In64BitMode]>;159def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),160 "movs{lq|xd}\t{$src, $dst|$dst, $src}",161 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>,162 Sched<[WriteLoad]>, Requires<[In64BitMode]>;163 164// These instructions exist as a consequence of operand size prefix having165// control of the destination size, but not the input size. Only support them166// for the disassembler.167let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {168def MOVSX16rr32: I<0x63, MRMSrcReg, (outs GR16:$dst), (ins GR32:$src),169 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,170 Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>;171def MOVSX32rr32: I<0x63, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),172 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,173 Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>;174let mayLoad = 1 in {175def MOVSX16rm32: I<0x63, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src),176 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,177 Sched<[WriteLoad]>, OpSize16, Requires<[In64BitMode]>;178def MOVSX32rm32: I<0x63, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),179 "movs{lq|xd}\t{$src, $dst|$dst, $src}", []>,180 Sched<[WriteLoad]>, OpSize32, Requires<[In64BitMode]>;181} // mayLoad = 1182} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0183 184// movzbq and movzwq encodings for the disassembler185let hasSideEffects = 0 in {186def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),187 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>,188 TB, Sched<[WriteALU]>;189let mayLoad = 1 in190def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),191 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>,192 TB, Sched<[WriteLoad]>;193def MOVZX64rr16 : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),194 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>,195 TB, Sched<[WriteALU]>;196let mayLoad = 1 in197def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),198 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>,199 TB, Sched<[WriteLoad]>;200}201 202// 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a203// 32-bit register.204def : Pat<(i64 (zext GR8:$src)),205 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;206def : Pat<(zextloadi64i8 addr:$src),207 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;208 209def : Pat<(i64 (zext GR16:$src)),210 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;211def : Pat<(zextloadi64i16 addr:$src),212 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;213 214// The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a215// SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible216// when the 32-bit value is defined by a truncate or is copied from something217// where the high bits aren't necessarily all zero. In such cases, we fall back218// to these explicit zext instructions.219def : Pat<(i64 (zext GR32:$src)),220 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;221def : Pat<(i64 (zextloadi64i32 addr:$src)),222 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;223