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1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the X86 x87 FPU instruction set, defining the10// instructions, and properties of the instructions which are needed for code11// generation, machine code emission, and analysis.12//13//===----------------------------------------------------------------------===//14 15// Some 'special' instructions - expanded after instruction selection.16// Clobbers EFLAGS due to OR instruction used internally.17// FIXME: Can we model this in SelectionDAG?18let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in {19 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),20 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;21 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),22 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;23 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),24 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;25 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),26 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;27 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),28 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;29 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),30 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;31 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),32 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;33 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),34 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;35 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),36 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;37 38 def FP80_ADDr : PseudoI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),39 [(set RFP80:$dst,40 (any_X86fp80_add RFP80:$src1, RFP80:$src2))]>;41 def FP80_ADDm32 : PseudoI<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2),42 [(set RFP80:$dst,43 (any_X86fp80_add RFP80:$src1,44 (f80 (extloadf32 addr:$src2))))]>;45}46 47// All FP Stack operations are represented with four instructions here. The48// first three instructions, generated by the instruction selector, use "RFP32"49// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,50// 64-bit or 80-bit floating point values. These sizes apply to the values,51// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be52// copied to each other without losing information. These instructions are all53// pseudo instructions and use the "_Fp" suffix.54// In some cases there are additional variants with a mixture of different55// register sizes.56// The second instruction is defined with FPI, which is the actual instruction57// emitted by the assembler. These use "RST" registers, although frequently58// the actual register(s) used are implicit. These are always 80 bits.59// The FP stackifier pass converts one to the other after register allocation60// occurs.61//62// Note that the FpI instruction should have instruction selection info (e.g.63// a pattern) and the FPI instruction should have emission info (e.g. opcode64// encoding and asm printing info).65 66// FpIf32, FpIf64 - Floating Point Pseudo Instruction template.67// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.68// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.69// f80 instructions cannot use SSE and use neither of these.70class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :71 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;72class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :73 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;74 75// Factoring for arithmetic.76multiclass FPBinary_rr<SDPatternOperator OpNode> {77// Register op register -> register78// These are separated out because they have no reversed form.79def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,80 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;81def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,82 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;83def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,84 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;85}86// The FopST0 series are not included here because of the irregularities87// in where the 'r' goes in assembly output.88// These instructions cannot address 80-bit memory.89multiclass FPBinary<SDPatternOperator OpNode, Format fp, string asmstring,90 bit Forward = 1> {91// ST(0) = ST(0) + [mem]92def _Fp32m : FpIf32<(outs RFP32:$dst),93 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,94 [!if(Forward,95 (set RFP32:$dst,96 (OpNode RFP32:$src1, (loadf32 addr:$src2))),97 (set RFP32:$dst,98 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;99def _Fp64m : FpIf64<(outs RFP64:$dst),100 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,101 [!if(Forward,102 (set RFP64:$dst,103 (OpNode RFP64:$src1, (loadf64 addr:$src2))),104 (set RFP64:$dst,105 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;106def _Fp64m32: FpIf64<(outs RFP64:$dst),107 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,108 [!if(Forward,109 (set RFP64:$dst,110 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),111 (set RFP64:$dst,112 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>;113def _Fp80m32: FpI_<(outs RFP80:$dst),114 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,115 [!if(Forward,116 (set RFP80:$dst,117 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))),118 (set RFP80:$dst,119 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>;120def _Fp80m64: FpI_<(outs RFP80:$dst),121 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,122 [!if(Forward,123 (set RFP80:$dst,124 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))),125 (set RFP80:$dst,126 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>;127let mayLoad = 1 in128def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),129 !strconcat("f", asmstring, "{s}\t$src")>;130let mayLoad = 1 in131def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),132 !strconcat("f", asmstring, "{l}\t$src")>;133// ST(0) = ST(0) + [memint]134def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2),135 OneArgFPRW,136 [!if(Forward,137 (set RFP32:$dst,138 (OpNode RFP32:$src1, (X86fild16 addr:$src2))),139 (set RFP32:$dst,140 (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>;141def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2),142 OneArgFPRW,143 [!if(Forward,144 (set RFP32:$dst,145 (OpNode RFP32:$src1, (X86fild32 addr:$src2))),146 (set RFP32:$dst,147 (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>;148def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2),149 OneArgFPRW,150 [!if(Forward,151 (set RFP64:$dst,152 (OpNode RFP64:$src1, (X86fild16 addr:$src2))),153 (set RFP64:$dst,154 (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>;155def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2),156 OneArgFPRW,157 [!if(Forward,158 (set RFP64:$dst,159 (OpNode RFP64:$src1, (X86fild32 addr:$src2))),160 (set RFP64:$dst,161 (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>;162def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2),163 OneArgFPRW,164 [!if(Forward,165 (set RFP80:$dst,166 (OpNode RFP80:$src1, (X86fild16 addr:$src2))),167 (set RFP80:$dst,168 (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>;169def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2),170 OneArgFPRW,171 [!if(Forward,172 (set RFP80:$dst,173 (OpNode RFP80:$src1, (X86fild32 addr:$src2))),174 (set RFP80:$dst,175 (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>;176let mayLoad = 1 in177def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),178 !strconcat("fi", asmstring, "{s}\t$src")>;179let mayLoad = 1 in180def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),181 !strconcat("fi", asmstring, "{l}\t$src")>;182}183 184let Uses = [FPCW], mayRaiseFPException = 1 in {185// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling186// resources.187let hasNoSchedulingInfo = 1 in {188defm ADD : FPBinary_rr<any_fadd>;189defm SUB : FPBinary_rr<any_fsub>;190defm MUL : FPBinary_rr<any_fmul>;191defm DIV : FPBinary_rr<any_fdiv>;192}193 194// Sets the scheduling resources for the actual NAME#_F<size>m definitions.195let SchedRW = [WriteFAddLd] in {196defm ADD : FPBinary<any_fadd, MRM0m, "add">;197defm SUB : FPBinary<any_fsub, MRM4m, "sub">;198defm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>;199}200 201let SchedRW = [WriteFMulLd] in {202defm MUL : FPBinary<any_fmul, MRM1m, "mul">;203}204 205let SchedRW = [WriteFDivLd] in {206defm DIV : FPBinary<any_fdiv, MRM6m, "div">;207defm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>;208}209} // Uses = [FPCW], mayRaiseFPException = 1210 211class FPST0rInst<Format fp, string asm>212 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;213class FPrST0Inst<Format fp, string asm>214 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>;215class FPrST0PInst<Format fp, string asm>216 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>;217 218// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion219// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,220// we have to put some 'r's in and take them out of weird places.221let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in {222def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;223def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;224def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;225def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">;226def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">;227def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">;228def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">;229def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;230def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;231} // SchedRW232let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in {233def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;234def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;235} // SchedRW236let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in {237def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">;238def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">;239def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">;240} // SchedRW241let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in {242def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">;243def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">;244def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">;245def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">;246def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">;247def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">;248} // SchedRW249 250// Unary operations.251multiclass FPUnary<SDPatternOperator OpNode, Format fp, string asmstring> {252def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,253 [(set RFP32:$dst, (OpNode RFP32:$src))]>;254def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,255 [(set RFP64:$dst, (OpNode RFP64:$src))]>;256def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,257 [(set RFP80:$dst, (OpNode RFP80:$src))]>;258def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;259}260 261let SchedRW = [WriteFSign] in {262defm CHS : FPUnary<fneg, MRM_E0, "fchs">;263defm ABS : FPUnary<fabs, MRM_E1, "fabs">;264}265 266let Uses = [FPCW], mayRaiseFPException = 1 in {267let SchedRW = [WriteFSqrt80] in268defm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">;269 270let SchedRW = [WriteFCom] in {271let hasSideEffects = 0 in {272def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;273def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;274def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;275} // hasSideEffects276 277def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;278} // SchedRW279} // Uses = [FPCW], mayRaiseFPException = 1280 281let SchedRW = [WriteFTest], Defs = [FPSW] in {282def XAM_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;283def XAM_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;284def XAM_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;285def XAM_F : FPI<0xD9, MRM_E5, (outs), (ins), "fxam">;286} // SchedRW287 288// Versions of FP instructions that take a single memory operand. Added for the289// disassembler; remove as they are included with patterns elsewhere.290let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1,291 mayLoad = 1 in {292def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;293def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;294 295def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;296def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;297 298def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;299def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;300 301def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;302def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;303} // SchedRW304 305let SchedRW = [WriteMicrocoded] in {306let Defs = [FPSW, FPCW], mayLoad = 1 in {307def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins anymem:$src), "frstor\t$src">;308let Predicates = [HasX87] in309def FLDENVm : I<0xD9, MRM4m, (outs), (ins anymem:$src), "fldenv\t$src",310 [(X86fpenv_set addr:$src)]>;311}312 313let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW], mayStore = 1 in {314def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins anymem:$dst), "fnsave\t$dst">;315let Predicates = [HasX87] in316def FSTENVm : I<0xD9, MRM6m, (outs), (ins anymem:$dst), "fnstenv\t$dst",317 [(X86fpenv_get addr:$dst)]>;318}319 320let Uses = [FPSW], mayStore = 1 in321def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;322 323let mayLoad = 1 in324def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;325let Uses = [FPCW] ,mayRaiseFPException = 1, mayStore = 1 in326def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;327} // SchedRW328 329// Floating point cmovs.330class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :331 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMOV]>;332class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :333 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMOV]>;334 335multiclass FPCMov<PatLeaf cc> {336 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),337 CondMovFP,338 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,339 cc, EFLAGS))]>;340 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),341 CondMovFP,342 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,343 cc, EFLAGS))]>;344 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),345 CondMovFP,346 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,347 cc, EFLAGS))]>,348 Requires<[HasCMOV]>;349}350 351let SchedRW = [WriteFCMOV] in {352let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {353defm CMOVB : FPCMov<X86_COND_B>;354defm CMOVBE : FPCMov<X86_COND_BE>;355defm CMOVE : FPCMov<X86_COND_E>;356defm CMOVP : FPCMov<X86_COND_P>;357defm CMOVNB : FPCMov<X86_COND_AE>;358defm CMOVNBE: FPCMov<X86_COND_A>;359defm CMOVNE : FPCMov<X86_COND_NE>;360defm CMOVNP : FPCMov<X86_COND_NP>;361} // Uses = [EFLAGS], Constraints = "$src1 = $dst"362 363let Predicates = [HasCMOV] in {364// These are not factored because there's no clean way to pass DA/DB.365def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),366 "fcmovb\t{$op, %st|st, $op}">;367def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op),368 "fcmovbe\t{$op, %st|st, $op}">;369def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op),370 "fcmove\t{$op, %st|st, $op}">;371def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op),372 "fcmovu\t{$op, %st|st, $op}">;373def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op),374 "fcmovnb\t{$op, %st|st, $op}">;375def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op),376 "fcmovnbe\t{$op, %st|st, $op}">;377def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op),378 "fcmovne\t{$op, %st|st, $op}">;379def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),380 "fcmovnu\t{$op, %st|st, $op}">;381} // Predicates = [HasCMOV]382} // SchedRW383 384let mayRaiseFPException = 1 in {385// Floating point loads & stores.386let SchedRW = [WriteLoad], Uses = [FPCW] in {387let canFoldAsLoad = 1 in {388def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,389 [(set RFP32:$dst, (loadf32 addr:$src))]>;390def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,391 [(set RFP64:$dst, (loadf64 addr:$src))]>;392def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,393 [(set RFP80:$dst, (loadf80 addr:$src))]>;394} // canFoldAsLoad395def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,396 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;397def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,398 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;399def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,400 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;401let mayRaiseFPException = 0 in {402def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,403 [(set RFP32:$dst, (X86fild16 addr:$src))]>;404def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,405 [(set RFP32:$dst, (X86fild32 addr:$src))]>;406def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,407 [(set RFP32:$dst, (X86fild64 addr:$src))]>;408def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,409 [(set RFP64:$dst, (X86fild16 addr:$src))]>;410def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,411 [(set RFP64:$dst, (X86fild32 addr:$src))]>;412def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,413 [(set RFP64:$dst, (X86fild64 addr:$src))]>;414def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,415 [(set RFP80:$dst, (X86fild16 addr:$src))]>;416def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,417 [(set RFP80:$dst, (X86fild32 addr:$src))]>;418def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,419 [(set RFP80:$dst, (X86fild64 addr:$src))]>;420} // mayRaiseFPException = 0421} // SchedRW422 423let SchedRW = [WriteStore], Uses = [FPCW] in {424def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,425 [(store RFP32:$src, addr:$op)]>;426def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,427 [(truncstoref32 RFP64:$src, addr:$op)]>;428def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,429 [(store RFP64:$src, addr:$op)]>;430def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,431 [(truncstoref32 RFP80:$src, addr:$op)]>;432def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,433 [(truncstoref64 RFP80:$src, addr:$op)]>;434// FST does not support 80-bit memory target; FSTP must be used.435 436let mayStore = 1, hasSideEffects = 0 in {437def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;438def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;439def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;440def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;441def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;442} // mayStore443 444def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,445 [(store RFP80:$src, addr:$op)]>;446 447let mayStore = 1, hasSideEffects = 0 in {448def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;449def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,450 [(X86fist32 RFP32:$src, addr:$op)]>;451def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,452 [(X86fist64 RFP32:$src, addr:$op)]>;453def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;454def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,455 [(X86fist32 RFP64:$src, addr:$op)]>;456def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,457 [(X86fist64 RFP64:$src, addr:$op)]>;458def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;459def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,460 [(X86fist32 RFP80:$src, addr:$op)]>;461def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,462 [(X86fist64 RFP80:$src, addr:$op)]>;463} // mayStore464} // SchedRW, Uses = [FPCW]465 466let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in {467def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;468def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;469def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;470let mayRaiseFPException = 0 in {471def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;472def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;473def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;474}475}476let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {477def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;478def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;479def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;480def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;481def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;482def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;483def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;484def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;485def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;486def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;487}488 489// FISTTP requires SSE3 even though it's a FPStack op.490let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in {491def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,492 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>;493def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,494 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>;495def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,496 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>;497def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,498 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>;499def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,500 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>;501def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,502 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>;503def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,504 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>;505def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,506 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>;507def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,508 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>;509} // Predicates = [HasSSE3]510 511let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {512def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;513def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;514def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;515}516 517// FP Stack manipulation instructions.518let SchedRW = [WriteMove], Uses = [FPCW] in {519def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;520def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">;521def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">;522let mayRaiseFPException = 0 in523def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">;524}525 526// Floating point constant loads.527let SchedRW = [WriteZero], Uses = [FPCW], isReMaterializable = 1 in {528def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,529 [(set RFP32:$dst, fpimm0)]>;530def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,531 [(set RFP32:$dst, fpimm1)]>;532def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,533 [(set RFP64:$dst, fpimm0)]>;534def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,535 [(set RFP64:$dst, fpimm1)]>;536def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,537 [(set RFP80:$dst, fpimm0)]>;538def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,539 [(set RFP80:$dst, fpimm1)]>;540}541 542let SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in543def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;544 545let SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in546def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;547 548let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in {549def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;550def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;551def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;552def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>;553def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;554} // SchedRW555 556// Floating point compares.557let SchedRW = [WriteFCom], Uses = [FPCW], hasSideEffects = 0 in {558def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>;559def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>;560def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>;561def COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>;562def COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>;563def COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>;564} // SchedRW565} // mayRaiseFPException = 1566 567let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {568// CC = ST(0) cmp ST(i)569let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {570def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,571 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,572 Requires<[FPStackf32, HasCMOV]>;573def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,574 [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>,575 Requires<[FPStackf64, HasCMOV]>;576def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,577 [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>,578 Requires<[HasCMOV]>;579def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,580 [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>,581 Requires<[FPStackf32, HasCMOV]>;582def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,583 [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>,584 Requires<[FPStackf64, HasCMOV]>;585def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,586 [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>,587 Requires<[HasCMOV]>;588}589 590let Uses = [ST0, FPCW] in {591def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)592 (outs), (ins RSTi:$reg), "fucom\t$reg">;593def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop594 (outs), (ins RSTi:$reg), "fucomp\t$reg">;595def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop596 (outs), (ins), "fucompp">;597}598 599let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in {600def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)601 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">;602def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop603 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">;604 605def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg),606 "fcomi\t{$reg, %st|st, $reg}">;607def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg),608 "fcompi\t{$reg, %st|st, $reg}">;609}610} // SchedRW611 612// Floating point flag ops.613let SchedRW = [WriteALU] in {614let Defs = [AX, FPSW], Uses = [FPSW], hasSideEffects = 0 in615def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags616 (outs), (ins), "fnstsw\t{%ax|ax}", []>;617let Defs = [FPSW], Uses = [FPCW] in618def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world619 (outs), (ins i16mem:$dst), "fnstcw\t$dst",620 [(X86fp_cwd_get16 addr:$dst)]>;621} // SchedRW622let Defs = [FPSW,FPCW], mayLoad = 1 in623def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]624 (outs), (ins i16mem:$dst), "fldcw\t$dst",625 [(X86fp_cwd_set16 addr:$dst)]>,626 Sched<[WriteLoad]>;627 628// FPU control instructions629let SchedRW = [WriteMicrocoded] in {630def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;631def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;632 633let Defs = [FPSW, FPCW] in634def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;635// Clear exceptions636let Defs = [FPSW] in637def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;638} // SchedRW639 640// Operand-less floating-point instructions for the disassembler.641let Defs = [FPSW] in642def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>;643 644let SchedRW = [WriteMicrocoded] in {645let Defs = [FPSW] in {646def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;647def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;648def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;649let Uses = [FPCW], mayRaiseFPException = 1 in {650def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;651def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>;652def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>;653def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>;654def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>;655def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>;656def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>;657def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>;658def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;659def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>;660def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;661def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>;662def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;663def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;664} // Uses = [FPCW], mayRaiseFPException = 1665} // Defs = [FPSW]666 667let Uses = [FPSW, FPCW] in {668def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst),669 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB,670 Requires<[HasFXSR]>;671def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst),672 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>,673 TB, Requires<[HasFXSR, In64BitMode]>;674} // Uses = [FPSW, FPCW]675 676let Defs = [FPSW, FPCW] in {677def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src),678 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>,679 TB, Requires<[HasFXSR]>;680def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src),681 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>,682 TB, Requires<[HasFXSR, In64BitMode]>;683} // Defs = [FPSW, FPCW]684} // SchedRW685 686//===----------------------------------------------------------------------===//687// Non-Instruction Patterns688//===----------------------------------------------------------------------===//689 690// Required for RET of f32 / f64 / f80 values.691def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>;692def : Pat<(X86fldf32 addr:$src), (LD_Fp32m64 addr:$src)>;693def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>;694def : Pat<(X86fldf32 addr:$src), (LD_Fp32m80 addr:$src)>;695def : Pat<(X86fldf64 addr:$src), (LD_Fp64m80 addr:$src)>;696def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>;697 698// Required for CALL which return f32 / f64 / f80 values.699def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>;700def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>;701def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>;702def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>;703def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>;704def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>;705 706// Floating point constant -0.0 and -1.0707def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;708def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;709def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;710def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;711def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;712def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;713 714// FP extensions map onto simple pseudo-value conversions if they are to/from715// the FP stack.716def : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,717 Requires<[FPStackf32]>;718def : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,719 Requires<[FPStackf32]>;720def : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,721 Requires<[FPStackf64]>;722 723// FP truncations map onto simple pseudo-value conversions if they are to/from724// the FP stack. We have validated that only value-preserving truncations make725// it through isel.726def : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,727 Requires<[FPStackf32]>;728def : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,729 Requires<[FPStackf32]>;730def : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,731 Requires<[FPStackf64]>;732