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1//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the X86 MMX instruction set, defining the instructions,10// and properties of the instructions which are needed for code generation,11// machine code emission, and analysis.12//13// All instructions that use MMX should be in this file, even if they also use14// SSE.15//16//===----------------------------------------------------------------------===//17 18//===----------------------------------------------------------------------===//19// MMX Multiclasses20//===----------------------------------------------------------------------===//21 22// Alias instruction that maps zero vector to pxor mmx.23// This is expanded by ExpandPostRAPseudos to an pxor.24// We set canFoldAsLoad because this can be converted to a constant-pool25// load of an all-zeros value if folding it would be beneficial.26let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,27 isPseudo = 1, SchedRW = [WriteZero], Predicates = [HasMMX] in {28def MMX_SET0 : I<0, Pseudo, (outs VR64:$dst), (ins), "",29 [(set VR64:$dst, (x86mmx (MMX_X86movw2d (i32 0))))]>;30}31 32let Constraints = "$src1 = $dst" in {33 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.34 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,35 X86FoldableSchedWrite sched, bit Commutable = 0,36 X86MemOperand OType = i64mem> {37 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),38 (ins VR64:$src1, VR64:$src2),39 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),40 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,41 Sched<[sched]> {42 let isCommutable = Commutable;43 }44 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),45 (ins VR64:$src1, OType:$src2),46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),47 [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,48 Sched<[sched.Folded, sched.ReadAfterFold]>;49 }50 51 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,52 string OpcodeStr, Intrinsic IntId,53 Intrinsic IntId2, X86FoldableSchedWrite sched,54 X86FoldableSchedWrite schedImm> {55 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),56 (ins VR64:$src1, VR64:$src2),57 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),58 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,59 Sched<[sched]>;60 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),61 (ins VR64:$src1, i64mem:$src2),62 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),63 [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,64 Sched<[sched.Folded, sched.ReadAfterFold]>;65 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),66 (ins VR64:$src1, i32u8imm:$src2),67 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),68 [(set VR64:$dst, (IntId2 VR64:$src1, timm:$src2))]>,69 Sched<[schedImm]>;70 }71}72 73/// Unary MMX instructions requiring SSSE3.74multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,75 Intrinsic IntId64, X86FoldableSchedWrite sched> {76 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),77 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),78 [(set VR64:$dst, (IntId64 VR64:$src))]>,79 Sched<[sched]>;80 81 def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),82 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),83 [(set VR64:$dst, (IntId64 (load_mmx addr:$src)))]>,84 Sched<[sched.Folded]>;85}86 87/// Binary MMX instructions requiring SSSE3.88let ImmT = NoImm, Constraints = "$src1 = $dst" in {89multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,90 Intrinsic IntId64, X86FoldableSchedWrite sched,91 bit Commutable = 0> {92 let isCommutable = Commutable in93 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),94 (ins VR64:$src1, VR64:$src2),95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),96 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>,97 Sched<[sched]>;98 def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),99 (ins VR64:$src1, i64mem:$src2),100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),101 [(set VR64:$dst,102 (IntId64 VR64:$src1, (load_mmx addr:$src2)))]>,103 Sched<[sched.Folded, sched.ReadAfterFold]>;104}105}106 107/// PALIGN MMX instructions (require SSSE3).108multiclass ssse3_palign_mm<string asm, Intrinsic IntId,109 X86FoldableSchedWrite sched> {110 def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),111 (ins VR64:$src1, VR64:$src2, u8imm:$src3),112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),113 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,114 Sched<[sched]>;115 def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),116 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),118 [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2),119 (i8 timm:$src3)))]>,120 Sched<[sched.Folded, sched.ReadAfterFold]>;121}122 123multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,124 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,125 string asm, X86FoldableSchedWrite sched, Domain d> {126 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,127 [(set DstRC:$dst, (Int SrcRC:$src))], d>,128 Sched<[sched]>;129 def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,130 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,131 Sched<[sched.Folded]>;132}133 134multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,135 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,136 PatFrag ld_frag, string asm, Domain d> {137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),138 (ins DstRC:$src1, SrcRC:$src2), asm,139 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,140 Sched<[WriteCvtI2PS]>;141 def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),142 (ins DstRC:$src1, x86memop:$src2), asm,143 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,144 Sched<[WriteCvtI2PS.Folded]>;145}146 147//===----------------------------------------------------------------------===//148// MMX EMMS Instruction149//===----------------------------------------------------------------------===//150 151let SchedRW = [WriteEMMS],152 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,153 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in154def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;155 156//===----------------------------------------------------------------------===//157// MMX Scalar Instructions158//===----------------------------------------------------------------------===//159 160// Data Transfer Instructions161def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),162 "movd\t{$src, $dst|$dst, $src}",163 [(set VR64:$dst,164 (x86mmx (MMX_X86movw2d GR32:$src)))]>,165 Sched<[WriteVecMoveFromGpr]>;166def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),167 "movd\t{$src, $dst|$dst, $src}",168 [(set VR64:$dst,169 (x86mmx (MMX_X86movw2d (loadi32 addr:$src))))]>,170 Sched<[WriteVecLoad]>;171 172let mayStore = 1 in173def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),174 "movd\t{$src, $dst|$dst, $src}", []>,175 Sched<[WriteVecStore]>;176 177def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),178 "movd\t{$src, $dst|$dst, $src}",179 [(set GR32:$dst,180 (MMX_X86movd2w (x86mmx VR64:$src)))]>,181 Sched<[WriteVecMoveToGpr]>;182 183let isBitcast = 1 in184def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),185 "movq\t{$src, $dst|$dst, $src}",186 [(set VR64:$dst, (bitconvert GR64:$src))]>,187 Sched<[WriteVecMoveFromGpr]>;188 189let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in190def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),191 (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",192 []>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;193 194let isBitcast = 1 in {195def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,196 (outs GR64:$dst), (ins VR64:$src),197 "movq\t{$src, $dst|$dst, $src}",198 [(set GR64:$dst, (bitconvert VR64:$src))]>,199 Sched<[WriteVecMoveToGpr]>;200let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {201def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),202 "movq\t{$src, $dst|$dst, $src}", []>;203let isCodeGenOnly = 1, ForceDisassemble = 1 in204def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),205 "movq\t{$src, $dst|$dst, $src}", []>;206} // SchedRW, hasSideEffects, isMoveReg207} // isBitcast208 209let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in210def MMX_MOVD64from64mr : MMXRI<0x7E, MRMDestMem,211 (outs), (ins i64mem:$dst, VR64:$src),212 "movq\t{$src, $dst|$dst, $src}", []>,213 Sched<[SchedWriteVecMoveLS.MMX.MR]>;214 215let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in {216let canFoldAsLoad = 1 in217def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),218 "movq\t{$src, $dst|$dst, $src}",219 [(set VR64:$dst, (load_mmx addr:$src))]>;220} // SchedRW221 222let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in223def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),224 "movq\t{$src, $dst|$dst, $src}",225 [(store (x86mmx VR64:$src), addr:$dst)]>;226 227def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,228 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;229def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,230 [SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;231 232let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {233def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),234 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",235 [(set VR64:$dst,236 (x86mmx (MMX_X86movdq2q VR128:$src)))]>;237 238def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),239 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",240 [(set VR128:$dst,241 (v2i64 (MMX_X86movq2dq VR64:$src)))]>;242 243let isCodeGenOnly = 1, hasSideEffects = 1 in {244def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),245 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",246 []>;247 248def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),249 (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",250 []>;251}252} // SchedRW253 254let Predicates = [HasMMX, HasSSE1] in255def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),256 "movntq\t{$src, $dst|$dst, $src}",257 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>,258 Sched<[SchedWriteVecMoveLSNT.MMX.MR]>;259 260// Arithmetic Instructions261defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,262 SchedWriteVecALU.MMX>;263defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,264 SchedWriteVecALU.MMX>;265defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,266 SchedWriteVecALU.MMX>;267// -- Addition268defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,269 SchedWriteVecALU.MMX, 1>;270defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,271 SchedWriteVecALU.MMX, 1>;272defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,273 SchedWriteVecALU.MMX, 1>;274let Predicates = [HasMMX, HasSSE2] in275defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,276 SchedWriteVecALU.MMX, 1>;277defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,278 SchedWriteVecALU.MMX, 1>;279defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,280 SchedWriteVecALU.MMX, 1>;281 282defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,283 SchedWriteVecALU.MMX, 1>;284defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,285 SchedWriteVecALU.MMX, 1>;286 287defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,288 SchedWritePHAdd.MMX>;289defm MMX_PHADDD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,290 SchedWritePHAdd.MMX>;291defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,292 SchedWritePHAdd.MMX>;293 294// -- Subtraction295defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,296 SchedWriteVecALU.MMX>;297defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,298 SchedWriteVecALU.MMX>;299defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,300 SchedWriteVecALU.MMX>;301let Predicates = [HasMMX, HasSSE2] in302defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,303 SchedWriteVecALU.MMX>;304 305defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,306 SchedWriteVecALU.MMX>;307defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,308 SchedWriteVecALU.MMX>;309 310defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,311 SchedWriteVecALU.MMX>;312defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,313 SchedWriteVecALU.MMX>;314 315defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,316 SchedWritePHAdd.MMX>;317defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,318 SchedWritePHAdd.MMX>;319defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,320 SchedWritePHAdd.MMX>;321 322// -- Multiplication323defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,324 SchedWriteVecIMul.MMX, 1>;325 326defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w,327 SchedWriteVecIMul.MMX, 1>;328let Predicates = [HasMMX, HasSSE1] in329defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,330 SchedWriteVecIMul.MMX, 1>;331let Predicates = [HasMMX, HasSSE2] in332defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,333 SchedWriteVecIMul.MMX, 1>;334defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",335 int_x86_ssse3_pmul_hr_sw,336 SchedWriteVecIMul.MMX, 1>;337 338// -- Miscellanea339defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,340 SchedWriteVecIMul.MMX, 1>;341 342defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",343 int_x86_ssse3_pmadd_ub_sw,344 SchedWriteVecIMul.MMX>;345let Predicates = [HasMMX, HasSSE1] in {346defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,347 SchedWriteVecALU.MMX, 1>;348defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,349 SchedWriteVecALU.MMX, 1>;350 351defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,352 SchedWriteVecALU.MMX, 1>;353defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,354 SchedWriteVecALU.MMX, 1>;355 356defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,357 SchedWriteVecALU.MMX, 1>;358defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,359 SchedWriteVecALU.MMX, 1>;360 361defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,362 SchedWritePSADBW.MMX, 1>;363}364 365defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,366 SchedWriteVecALU.MMX>;367defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,368 SchedWriteVecALU.MMX>;369defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,370 SchedWriteVecALU.MMX>;371let Constraints = "$src1 = $dst" in372 defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b,373 SchedWriteShuffle.MMX>;374 375// Logical Instructions376defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,377 SchedWriteVecLogic.MMX, 1>;378defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,379 SchedWriteVecLogic.MMX, 1>;380defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,381 SchedWriteVecLogic.MMX, 1>;382defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,383 SchedWriteVecLogic.MMX>;384 385// Shift Instructions386defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",387 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,388 SchedWriteVecShift.MMX,389 SchedWriteVecShiftImm.MMX>;390defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",391 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,392 SchedWriteVecShift.MMX,393 SchedWriteVecShiftImm.MMX>;394defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",395 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,396 SchedWriteVecShift.MMX,397 SchedWriteVecShiftImm.MMX>;398 399defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",400 int_x86_mmx_psll_w, int_x86_mmx_pslli_w,401 SchedWriteVecShift.MMX,402 SchedWriteVecShiftImm.MMX>;403defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",404 int_x86_mmx_psll_d, int_x86_mmx_pslli_d,405 SchedWriteVecShift.MMX,406 SchedWriteVecShiftImm.MMX>;407defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",408 int_x86_mmx_psll_q, int_x86_mmx_pslli_q,409 SchedWriteVecShift.MMX,410 SchedWriteVecShiftImm.MMX>;411 412defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",413 int_x86_mmx_psra_w, int_x86_mmx_psrai_w,414 SchedWriteVecShift.MMX,415 SchedWriteVecShiftImm.MMX>;416defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",417 int_x86_mmx_psra_d, int_x86_mmx_psrai_d,418 SchedWriteVecShift.MMX,419 SchedWriteVecShiftImm.MMX>;420 421// Comparison Instructions422defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,423 SchedWriteVecALU.MMX>;424defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,425 SchedWriteVecALU.MMX>;426defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,427 SchedWriteVecALU.MMX>;428 429defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,430 SchedWriteVecALU.MMX>;431defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,432 SchedWriteVecALU.MMX>;433defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,434 SchedWriteVecALU.MMX>;435 436// -- Unpack Instructions437defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",438 int_x86_mmx_punpckhbw,439 SchedWriteShuffle.MMX>;440defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",441 int_x86_mmx_punpckhwd,442 SchedWriteShuffle.MMX>;443defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",444 int_x86_mmx_punpckhdq,445 SchedWriteShuffle.MMX>;446defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",447 int_x86_mmx_punpcklbw,448 SchedWriteShuffle.MMX,449 0, i32mem>;450defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",451 int_x86_mmx_punpcklwd,452 SchedWriteShuffle.MMX,453 0, i32mem>;454defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",455 int_x86_mmx_punpckldq,456 SchedWriteShuffle.MMX,457 0, i32mem>;458 459// -- Pack Instructions460defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,461 SchedWriteShuffle.MMX>;462defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,463 SchedWriteShuffle.MMX>;464defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,465 SchedWriteShuffle.MMX>;466 467// -- Shuffle Instructions468defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,469 SchedWriteVarShuffle.MMX>;470 471let Predicates = [HasMMX, HasSSE1] in {472def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,473 (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),474 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",475 [(set VR64:$dst,476 (int_x86_sse_pshuf_w VR64:$src1, timm:$src2))]>,477 Sched<[SchedWriteShuffle.MMX]>;478def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,479 (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),480 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",481 [(set VR64:$dst,482 (int_x86_sse_pshuf_w (load_mmx addr:$src1),483 timm:$src2))]>,484 Sched<[SchedWriteShuffle.MMX.Folded]>;485}486 487// -- Conversion Instructions488defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,489 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",490 WriteCvtPS2I, SSEPackedSingle>, TB, SIMD_EXC;491defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,492 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",493 WriteCvtPD2I, SSEPackedDouble>, TB, PD, SIMD_EXC;494defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,495 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",496 WriteCvtPS2I, SSEPackedSingle>, TB, SIMD_EXC;497defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,498 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",499 WriteCvtPD2I, SSEPackedDouble>, TB, PD, SIMD_EXC;500defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,501 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",502 WriteCvtI2PD, SSEPackedDouble>, TB, PD;503let Constraints = "$src1 = $dst" in {504 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,505 int_x86_sse_cvtpi2ps,506 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",507 SSEPackedSingle>, TB, SIMD_EXC;508}509 510// Extract / Insert511let Predicates = [HasMMX, HasSSE1] in512def MMX_PEXTRWrri : MMXIi8<0xC5, MRMSrcReg,513 (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),514 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",515 [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,516 timm:$src2))]>,517 Sched<[WriteVecExtract]>;518let Constraints = "$src1 = $dst" in {519let Predicates = [HasMMX, HasSSE1] in {520 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,521 (outs VR64:$dst),522 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),523 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",524 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,525 GR32orGR64:$src2, timm:$src3))]>,526 Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;527 528 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,529 (outs VR64:$dst),530 (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),531 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",532 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,533 (i32 (anyext (loadi16 addr:$src2))),534 timm:$src3))]>,535 Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>;536}537}538 539// Mask creation540let Predicates = [HasMMX, HasSSE1] in541def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),542 (ins VR64:$src),543 "pmovmskb\t{$src, $dst|$dst, $src}",544 [(set GR32orGR64:$dst,545 (int_x86_mmx_pmovmskb VR64:$src))]>,546 Sched<[WriteMMXMOVMSK]>;547 548// Misc.549let SchedRW = [SchedWriteShuffle.MMX] in {550let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in551def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),552 "maskmovq\t{$mask, $src|$src, $mask}",553 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;554let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in555def MMX_MASKMOVQ64: MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),556 "maskmovq\t{$mask, $src|$src, $mask}",557 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;558}559 560// 64-bit bit convert.561let Predicates = [HasMMX, HasSSE2] in {562def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),563 (MMX_MOVQ2FR64rr VR64:$src)>;564def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),565 (MMX_MOVFR642Qrr FR64:$src)>;566def : Pat<(x86mmx (MMX_X86movdq2q567 (bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))),568 (MMX_CVTPS2PIrr VR128:$src)>;569def : Pat<(x86mmx (MMX_X86movdq2q570 (bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))),571 (MMX_CVTTPS2PIrr VR128:$src)>;572def : Pat<(x86mmx (MMX_X86movdq2q573 (bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),574 (MMX_CVTPD2PIrr VR128:$src)>;575def : Pat<(x86mmx (MMX_X86movdq2q576 (bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),577 (MMX_CVTTPD2PIrr VR128:$src)>;578}579 580let AddedComplexity = 400 in { // Prefer non-temporal version581 582// Non-temporal store (no alignment required).583let Predicates = [HasMMX] in {584 def : Pat<(nontemporalstore (x86mmx VR64:$src), addr:$dst),585 (MMX_MOVNTQmr addr:$dst, VR64:$src)>;586}587 588} // AddedComplexity589