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1//===------- X86InstrOperands.td - X86 Operand Definitions --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9def x86_ptr_rc : RegClassByHwMode<10 [X86_32, X86_64, X86_64_X32],11 [GR32, GR64, LOW32_ADDR_ACCESS]>;12 13// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for14// the index operand of an address, to conform to x86 encoding restrictions.15def ptr_rc_nosp : RegClassByHwMode<16 [X86_32, X86_64, X86_64_X32],17 [GR32_NOSP, GR64_NOSP, GR32_NOSP]>;18 19// *mem - Operand definitions for the funky X86 addressing mode operands.20//21def X86MemAsmOperand : AsmOperandClass {22 let Name = "Mem";23}24let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in {25 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }26 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }27 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }28 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }29 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }30 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }31 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }32 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }33 // Gather mem operands34 def X86Mem32_RC128Operand : AsmOperandClass { let Name = "Mem32_RC128"; }35 def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; }36 def X86Mem32_RC256Operand : AsmOperandClass { let Name = "Mem32_RC256"; }37 def X86Mem64_RC256Operand : AsmOperandClass { let Name = "Mem64_RC256"; }38 39 def X86Mem32_RC128XOperand : AsmOperandClass { let Name = "Mem32_RC128X"; }40 def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; }41 def X86Mem32_RC256XOperand : AsmOperandClass { let Name = "Mem32_RC256X"; }42 def X86Mem64_RC256XOperand : AsmOperandClass { let Name = "Mem64_RC256X"; }43 def X86Mem32_RC512Operand : AsmOperandClass { let Name = "Mem32_RC512"; }44 def X86Mem64_RC512Operand : AsmOperandClass { let Name = "Mem64_RC512"; }45 46 def X86Mem512_GR16Operand : AsmOperandClass { let Name = "Mem512_GR16"; }47 def X86Mem512_GR32Operand : AsmOperandClass { let Name = "Mem512_GR32"; }48 def X86Mem512_GR64Operand : AsmOperandClass { let Name = "Mem512_GR64"; }49 50 def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; }51}52 53def X86AbsMemAsmOperand : AsmOperandClass {54 let Name = "AbsMem";55 let SuperClasses = [X86MemAsmOperand];56}57 58class X86MemOperand<string printMethod,59 AsmOperandClass parserMatchClass = X86MemAsmOperand,60 int size = 0> : Operand<iPTR> {61 let PrintMethod = printMethod;62 let MIOperandInfo = (ops x86_ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);63 let ParserMatchClass = parserMatchClass;64 let OperandType = "OPERAND_MEMORY";65 int Size = size;66}67 68// Gather mem operands69class X86VMemOperand<RegisterClass RC, string printMethod,70 AsmOperandClass parserMatchClass, int size = 0>71 : X86MemOperand<printMethod, parserMatchClass, size> {72 let MIOperandInfo = (ops x86_ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);73}74 75def anymem : X86MemOperand<"printMemReference">;76 77// FIXME: Right now we allow any size during parsing, but we might want to78// restrict to only unsized memory.79def opaquemem : X86MemOperand<"printMemReference">;80 81def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>;82 83def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8>;84def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>;85def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>;86def i64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>;87def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>;88def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>;89def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>;90def f16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>;91def f32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>;92def f64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>;93def f80mem : X86MemOperand<"printtbytemem", X86Mem80AsmOperand, 80>;94def f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>;95def f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>;96def f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>;97 98// 32/64 mode specific mem operands99def i512mem_GR16 : X86MemOperand<"printzmmwordmem", X86Mem512_GR16Operand, 512>;100def i512mem_GR32 : X86MemOperand<"printzmmwordmem", X86Mem512_GR32Operand, 512>;101def i512mem_GR64 : X86MemOperand<"printzmmwordmem", X86Mem512_GR64Operand, 512>;102 103// Gather mem operands104def vx32mem : X86VMemOperand<VR128, "printdwordmem", X86Mem32_RC128Operand, 32>;105def vx64mem : X86VMemOperand<VR128, "printqwordmem", X86Mem64_RC128Operand, 64>;106def vy32mem : X86VMemOperand<VR256, "printdwordmem", X86Mem32_RC256Operand, 32>;107def vy64mem : X86VMemOperand<VR256, "printqwordmem", X86Mem64_RC256Operand, 64>;108 109def vx32xmem : X86VMemOperand<VR128X, "printdwordmem", X86Mem32_RC128XOperand, 32>;110def vx64xmem : X86VMemOperand<VR128X, "printqwordmem", X86Mem64_RC128XOperand, 64>;111def vy32xmem : X86VMemOperand<VR256X, "printdwordmem", X86Mem32_RC256XOperand, 32>;112def vy64xmem : X86VMemOperand<VR256X, "printqwordmem", X86Mem64_RC256XOperand, 64>;113def vz32mem : X86VMemOperand<VR512, "printdwordmem", X86Mem32_RC512Operand, 32>;114def vz64mem : X86VMemOperand<VR512, "printqwordmem", X86Mem64_RC512Operand, 64>;115 116def shmem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>;117def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>;118def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>;119 120// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead121// of a plain GPR, so that it doesn't potentially require a REX prefix.122def ptr_rc_norex : RegClassByHwMode<123 [X86_32, X86_64, X86_64_X32],124 [GR32_NOREX, GR64_NOREX, GR32_NOREX]>;125 126def ptr_rc_norex_nosp : RegClassByHwMode<127 [X86_32, X86_64, X86_64_X32],128 [GR32_NOREX_NOSP, GR64_NOREX_NOSP, GR32_NOREX_NOSP]>;129 130 131def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> {132 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm,133 SEGMENT_REG);134}135 136// GPRs available for tailcall.137// It represents GR32_TC, GR64_TC or GR64_TCW64.138def ptr_rc_tailcall : RegClassByHwMode<139 [X86_32, X86_64, X86_64_X32],140 [GR32_TC, GR64_TC, GR64_TC]>;141 142// Special i32mem for addresses of load folding tail calls. These are not143// allowed to use callee-saved registers since they must be scheduled144// after callee-saved register are popped.145def i32mem_TC : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32> {146 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,147 i32imm, SEGMENT_REG);148}149 150// Special i64mem for addresses of load folding tail calls. These are not151// allowed to use callee-saved registers since they must be scheduled152// after callee-saved register are popped.153def i64mem_TC : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64> {154 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,155 ptr_rc_tailcall, i32imm, SEGMENT_REG);156}157 158def i64mem_w64TC : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64> {159 let MIOperandInfo = (ops GR64_TCW64, i8imm,160 GR64_TCW64, i32imm, SEGMENT_REG);161}162 163// Special parser to detect 16-bit mode to select 16-bit displacement.164def X86AbsMemMode16AsmOperand : AsmOperandClass {165 let Name = "AbsMemMode16";166 let RenderMethod = "addAbsMemOperands";167 let SuperClasses = [X86AbsMemAsmOperand];168}169 170def X86AbsMem8AsmOperand : AsmOperandClass {171 let Name = "AbsMem8";172 let RenderMethod = "addAbsMemOperands";173 let SuperClasses = [X86AbsMemAsmOperand];174}175 176// Branch targets print as pc-relative values.177class BranchTargetOperand<ValueType ty> : Operand<ty> {178 let OperandType = "OPERAND_PCREL";179 let PrintMethod = "printPCRelImm";180 let ParserMatchClass = X86AbsMemAsmOperand;181}182 183def i32imm_brtarget : BranchTargetOperand<i32>;184def i16imm_brtarget : BranchTargetOperand<i16>;185def i8imm_brtarget : BranchTargetOperand<i8> {186 let ParserMatchClass = X86AbsMem8AsmOperand;187}188 189// 64-bits but only 32 bits are significant, and those bits are treated as being190// pc relative.191def i64i32imm_brtarget : BranchTargetOperand<i64>;192 193def brtarget : BranchTargetOperand<OtherVT>;194def brtarget8 : BranchTargetOperand<OtherVT>;195def brtarget16 : BranchTargetOperand<OtherVT> {196 let ParserMatchClass = X86AbsMemMode16AsmOperand;197}198def brtarget32 : BranchTargetOperand<OtherVT>;199 200let RenderMethod = "addSrcIdxOperands" in {201 def X86SrcIdx8Operand : AsmOperandClass {202 let Name = "SrcIdx8";203 let SuperClasses = [X86Mem8AsmOperand];204 }205 def X86SrcIdx16Operand : AsmOperandClass {206 let Name = "SrcIdx16";207 let SuperClasses = [X86Mem16AsmOperand];208 }209 def X86SrcIdx32Operand : AsmOperandClass {210 let Name = "SrcIdx32";211 let SuperClasses = [X86Mem32AsmOperand];212 }213 def X86SrcIdx64Operand : AsmOperandClass {214 let Name = "SrcIdx64";215 let SuperClasses = [X86Mem64AsmOperand];216 }217} // RenderMethod = "addSrcIdxOperands"218 219let RenderMethod = "addDstIdxOperands" in {220 def X86DstIdx8Operand : AsmOperandClass {221 let Name = "DstIdx8";222 let SuperClasses = [X86Mem8AsmOperand];223 }224 def X86DstIdx16Operand : AsmOperandClass {225 let Name = "DstIdx16";226 let SuperClasses = [X86Mem16AsmOperand];227 }228 def X86DstIdx32Operand : AsmOperandClass {229 let Name = "DstIdx32";230 let SuperClasses = [X86Mem32AsmOperand];231 }232 def X86DstIdx64Operand : AsmOperandClass {233 let Name = "DstIdx64";234 let SuperClasses = [X86Mem64AsmOperand];235 }236} // RenderMethod = "addDstIdxOperands"237 238let RenderMethod = "addMemOffsOperands" in {239 def X86MemOffs16_8AsmOperand : AsmOperandClass {240 let Name = "MemOffs16_8";241 let SuperClasses = [X86Mem8AsmOperand];242 }243 def X86MemOffs16_16AsmOperand : AsmOperandClass {244 let Name = "MemOffs16_16";245 let SuperClasses = [X86Mem16AsmOperand];246 }247 def X86MemOffs16_32AsmOperand : AsmOperandClass {248 let Name = "MemOffs16_32";249 let SuperClasses = [X86Mem32AsmOperand];250 }251 def X86MemOffs32_8AsmOperand : AsmOperandClass {252 let Name = "MemOffs32_8";253 let SuperClasses = [X86Mem8AsmOperand];254 }255 def X86MemOffs32_16AsmOperand : AsmOperandClass {256 let Name = "MemOffs32_16";257 let SuperClasses = [X86Mem16AsmOperand];258 }259 def X86MemOffs32_32AsmOperand : AsmOperandClass {260 let Name = "MemOffs32_32";261 let SuperClasses = [X86Mem32AsmOperand];262 }263 def X86MemOffs32_64AsmOperand : AsmOperandClass {264 let Name = "MemOffs32_64";265 let SuperClasses = [X86Mem64AsmOperand];266 }267 def X86MemOffs64_8AsmOperand : AsmOperandClass {268 let Name = "MemOffs64_8";269 let SuperClasses = [X86Mem8AsmOperand];270 }271 def X86MemOffs64_16AsmOperand : AsmOperandClass {272 let Name = "MemOffs64_16";273 let SuperClasses = [X86Mem16AsmOperand];274 }275 def X86MemOffs64_32AsmOperand : AsmOperandClass {276 let Name = "MemOffs64_32";277 let SuperClasses = [X86Mem32AsmOperand];278 }279 def X86MemOffs64_64AsmOperand : AsmOperandClass {280 let Name = "MemOffs64_64";281 let SuperClasses = [X86Mem64AsmOperand];282 }283} // RenderMethod = "addMemOffsOperands"284 285class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>286 : X86MemOperand<printMethod, parserMatchClass> {287 let MIOperandInfo = (ops x86_ptr_rc, SEGMENT_REG);288}289 290class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>291 : X86MemOperand<printMethod, parserMatchClass> {292 let MIOperandInfo = (ops x86_ptr_rc);293}294 295def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;296def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;297def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;298def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;299def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;300def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;301def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;302def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;303 304class X86MemOffsOperand<Operand immOperand, string printMethod,305 AsmOperandClass parserMatchClass>306 : X86MemOperand<printMethod, parserMatchClass> {307 let MIOperandInfo = (ops immOperand, SEGMENT_REG);308}309 310def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",311 X86MemOffs16_8AsmOperand>;312def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",313 X86MemOffs16_16AsmOperand>;314def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",315 X86MemOffs16_32AsmOperand>;316def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",317 X86MemOffs32_8AsmOperand>;318def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",319 X86MemOffs32_16AsmOperand>;320def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",321 X86MemOffs32_32AsmOperand>;322def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",323 X86MemOffs32_64AsmOperand>;324def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",325 X86MemOffs64_8AsmOperand>;326def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",327 X86MemOffs64_16AsmOperand>;328def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",329 X86MemOffs64_32AsmOperand>;330def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",331 X86MemOffs64_64AsmOperand>;332 333def ccode : Operand<i8> {334 let PrintMethod = "printCondCode";335 let OperandNamespace = "X86";336 let OperandType = "OPERAND_COND_CODE";337}338 339class ImmSExtAsmOperandClass : AsmOperandClass {340 let SuperClasses = [ImmAsmOperand];341 let RenderMethod = "addImmOperands";342}343 344def X86GR32orGR64AsmOperand : AsmOperandClass {345 let Name = "GR32orGR64";346}347def GR32orGR64 : RegisterOperand<GR32> {348 let ParserMatchClass = X86GR32orGR64AsmOperand;349}350 351def X86GR16orGR32orGR64AsmOperand : AsmOperandClass {352 let Name = "GR16orGR32orGR64";353}354def GR16orGR32orGR64 : RegisterOperand<GR16> {355 let ParserMatchClass = X86GR16orGR32orGR64AsmOperand;356}357 358def AVX512RCOperand : AsmOperandClass {359 let Name = "AVX512RC";360}361def AVX512RC : Operand<i32> {362 let PrintMethod = "printRoundingControl";363 let OperandNamespace = "X86";364 let OperandType = "OPERAND_ROUNDING_CONTROL";365 let ParserMatchClass = AVX512RCOperand;366}367 368// Sign-extended immediate classes. We don't need to define the full lattice369// here because there is no instruction with an ambiguity between ImmSExti64i32370// and ImmSExti32i8.371//372// The strange ranges come from the fact that the assembler always works with373// 64-bit immediates, but for a 16-bit target value we want to accept both "-1"374// (which will be a -1ULL), and "0xFF" (-1 in 16-bits).375 376// [0, 0x7FFFFFFF] |377// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]378def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {379 let Name = "ImmSExti64i32";380}381 382// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |383// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]384def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {385 let Name = "ImmSExti16i8";386 let SuperClasses = [ImmSExti64i32AsmOperand];387}388 389// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |390// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]391def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {392 let Name = "ImmSExti32i8";393}394 395// [0, 0x0000007F] |396// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]397def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {398 let Name = "ImmSExti64i8";399 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,400 ImmSExti64i32AsmOperand];401}402 403// 4-bit immediate used by some XOP instructions404// [0, 0xF]405def ImmUnsignedi4AsmOperand : AsmOperandClass {406 let Name = "ImmUnsignedi4";407 let RenderMethod = "addImmOperands";408 let DiagnosticType = "InvalidImmUnsignedi4";409}410 411// Unsigned immediate used by SSE/AVX instructions412// [0, 0xFF]413// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]414def ImmUnsignedi8AsmOperand : AsmOperandClass {415 let Name = "ImmUnsignedi8";416 let RenderMethod = "addImmOperands";417}418 419// A couple of more descriptive operand definitions.420// 16-bits but only 8 bits are significant.421def i16i8imm : Operand<i16> {422 let ParserMatchClass = ImmSExti16i8AsmOperand;423 let OperandType = "OPERAND_IMMEDIATE";424}425// 32-bits but only 8 bits are significant.426def i32i8imm : Operand<i32> {427 let ParserMatchClass = ImmSExti32i8AsmOperand;428 let OperandType = "OPERAND_IMMEDIATE";429}430 431// 64-bits but only 32 bits are significant.432def i64i32imm : Operand<i64> {433 let ParserMatchClass = ImmSExti64i32AsmOperand;434 let OperandType = "OPERAND_IMMEDIATE";435}436 437// 64-bits but only 8 bits are significant.438def i64i8imm : Operand<i64> {439 let ParserMatchClass = ImmSExti64i8AsmOperand;440 let OperandType = "OPERAND_IMMEDIATE";441}442 443// Unsigned 4-bit immediate used by some XOP instructions.444def u4imm : Operand<i8> {445 let PrintMethod = "printU8Imm";446 let ParserMatchClass = ImmUnsignedi4AsmOperand;447 let OperandType = "OPERAND_IMMEDIATE";448}449 450def cflags : Operand<i8> {451 let PrintMethod = "printCondFlags";452 let ParserMatchClass = ImmUnsignedi4AsmOperand;453 let OperandType = "OPERAND_IMMEDIATE";454}455 456// Unsigned 8-bit immediate used by SSE/AVX instructions.457def u8imm : Operand<i8> {458 let PrintMethod = "printU8Imm";459 let ParserMatchClass = ImmUnsignedi8AsmOperand;460 let OperandType = "OPERAND_IMMEDIATE";461}462 463// 16-bit immediate but only 8-bits are significant and they are unsigned.464// Used by BT instructions.465def i16u8imm : Operand<i16> {466 let PrintMethod = "printU8Imm";467 let ParserMatchClass = ImmUnsignedi8AsmOperand;468 let OperandType = "OPERAND_IMMEDIATE";469}470 471// 32-bit immediate but only 8-bits are significant and they are unsigned.472// Used by some SSE/AVX instructions that use intrinsics.473def i32u8imm : Operand<i32> {474 let PrintMethod = "printU8Imm";475 let ParserMatchClass = ImmUnsignedi8AsmOperand;476 let OperandType = "OPERAND_IMMEDIATE";477}478 479// 64-bit immediate but only 8-bits are significant and they are unsigned.480// Used by BT instructions.481def i64u8imm : Operand<i64> {482 let PrintMethod = "printU8Imm";483 let ParserMatchClass = ImmUnsignedi8AsmOperand;484 let OperandType = "OPERAND_IMMEDIATE";485}486 487def lea64_8mem : Operand<i8> {488 let PrintMethod = "printMemReference";489 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i8imm, SEGMENT_REG);490 let ParserMatchClass = X86MemAsmOperand;491}492 493def lea64_16mem : Operand<i16> {494 let PrintMethod = "printMemReference";495 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i16imm, SEGMENT_REG);496 let ParserMatchClass = X86MemAsmOperand;497}498 499def lea64_32mem : Operand<i32> {500 let PrintMethod = "printMemReference";501 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG);502 let ParserMatchClass = X86MemAsmOperand;503}504 505// Memory operands that use 64-bit pointers in both ILP32 and LP64.506def lea64mem : Operand<i64> {507 let PrintMethod = "printMemReference";508 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG);509 let ParserMatchClass = X86MemAsmOperand;510}511 512let RenderMethod = "addMaskPairOperands" in {513 def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; }514 def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; }515 def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; }516 def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; }517 def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; }518}519 520def VK1Pair : RegisterOperand<VK1PAIR, "printVKPair"> {521 let ParserMatchClass = VK1PairAsmOperand;522}523 524def VK2Pair : RegisterOperand<VK2PAIR, "printVKPair"> {525 let ParserMatchClass = VK2PairAsmOperand;526}527 528def VK4Pair : RegisterOperand<VK4PAIR, "printVKPair"> {529 let ParserMatchClass = VK4PairAsmOperand;530}531 532def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> {533 let ParserMatchClass = VK8PairAsmOperand;534}535 536def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> {537 let ParserMatchClass = VK16PairAsmOperand;538}539